DESIGN AND ANALYSIS OF CHARGE PUMP

FOR PLL AT 90nm CMOS TECHNOLOGY

PRESENTED BY :
RAVI CHANDRA
CDAC MOHALI
 OUTLINE
Introduction
Literature Survey
Need And Significance Of Charge Pump
Objectives
Design and analysis of Charge Pump
Results and Discussions
Conclusion And Future Scope
References
Introduction of Charge pump
Charge pump is a kind of DC to DC converter and high efficiency device.
CP usually operate at a high- frequency
CP use some form of switching device(s) to control the connection of
voltages to the capacitor
 Charge pump is used in PLL to translate error
UP and DOWN signal into equal sourcing and
sinking current

advantages.pptx
 Non-ideality in PLL due to Charge Pump bring some challenging
problem to the efficient design and implementation

 Due to unequal sourcing and sinking currents in charge pump ,

results in a static phase error in PLL

 With reduced power supplies and feature sizes, circuits built in

nano-meter scale technologies suffer from an increased susceptibility
to performance degradation with process, voltage, and temperature
variability.
 Objectives

 Design a modified and optimized charge pump at 90nm technology.

 Reduce charge sharing in charge pump and their injection in different
transistors
 Use Monte Carlo simulation to analyse the reduction in mismatching
behaviour of charge pump.
 Analyse the variation of current mismatching and output voltage of charge
pump on PVT variation.
Methodology of charge pump design and analysis

Analyses of charge
Study of the basic Designing of Designing of pump current
concept of charge conventional charge proposed charge matching-
pump and their pump pump. mismatching and
designing topology charging-discharging
waveform

Effect of PVT
variation on charge
pump output
voltage
Design and Analysis of Charge pump
 Conventional charge pump

 The conventional CP has 4

PMOS and 4 NMOS transistor
 Two MOS transistor work as
switching device as ON-OFF
 others two equalize the charging
and discharging current
 Schematic design of Conventional charge pump with
capacitive load
 MOS transistor PM5 and NM5 is
remain always in ON state.
 Transistor PM1 and NM4 ON-OFF
according to apply UP and DOWN
signal respectively.
 When switch PM1 is in ON state,
charging of load capacitor takes place
and NM5 is in ON state, discharging of
load capacitor occurs.
 When both the switch is in OFF state
the output hold the pervious value.
 Designed Charge Pump

 The designed CP consists of current

mirror circuit and two low power high
gain operational amplifiers.
 Complementary connection of two
operational amplifiers are used to
equalize the charging and discharging
current of CP to reduce mismatching.

 current mirror circuit to provide wide

output voltage ranges and feedback
mechanism which help to equalize
charging and discharging current of CP.
 Designed Charge Pump continue…
Difference in charge transfer in CP
during charging and discharging has
an effect on transient response and
their proportional effect on current
mismatching. Presence of long
channel MOS transistors has a large
input capacitance in CP caused
decrease in speed of switching and
their operation while presence of
two complementary high gain &
low power amplifier keep the
charging and discharging current
equal.
 Result and Discussion
 All the resultant waveforms and histogram diagrams of the schematic of the CP

have been obtained using cadence virtuoso ADE and ADE XL tools. The
designed schematics are conventional CP, reference CP and proposed design of
CP. All schematics of different CPs have been designed using 90nm CMOS
process technology and power supply applied for schematic is in range of 1.0V
to 1.2V. The current mismatching through Monte Carlo simulation and output
voltage range variation by PVT variation method is analysed and discussed.
Conventional charge pump output voltage
Proposed charge pump output voltage
Conventional charge pump charging
Conventional charge pump discharging
Proposed charge pump charging
Proposed charge pump discharging
Conventional charge pump current matching
Proposed charge pump current matching
Power dissipation conventional charge pump
Power dissipation of proposed charge pump
 Comparison between conventional and proposed
charge pump
Result & Specification Conventional CP Proposed CP

CMOS Technology 90nm 90nm

Operating voltage 1V 1V
Output swing voltage 0.3V- 0.9V 0.5V – 1V
NMOS W/L ratio 120/90 120/90
PMOS W/L ratio 340/90 340/90
Stop time 300n second 300n second
Current matching range 0.3V – 1.2V 0.4 – 1.35 V

Current gain KCP 0.11μA/rad. 7.96μA/rad.

Power Dissipation 30μW 320μW

 Monte Carlo simulation
 To know the behaviour of circuit which is combination of different device

 Its result is used to analyse the tolerance in the circuit due to mismatch error

 Here observe the mismatching between device to device

 Here we mainly focus on random variation that is difference between two

identical designed closely ideal device.

new waveform\montecarlo.png
 Conventional charge pump
 In Conventional charge pump, Monte
Carlo simulation consider PM6 and NM2
transistor .
 This histogram presented current
mismatching at random1 and random14
of cadence virtuoso ADE XL tool. The
percentage current mismatching of
random1 is better than random14.

new waveform\conventinalmon
te1.jpg
 Proposed charge pump
 In Proposed CP, Monte Carlo
simulation consider PM8 and NM9
transistor.
 This histogram presented current
mismatching at random1 and
random14 of cadence virtuoso tool.
The percentage current mismatching
of random1 is better than random14.

new waveform\monte carloa1.jpg

 PVT variation
 PVT variation measures the changes in output with respect of different
process corners like tt, ff, ss, fs, sf, different range of voltages (0V,
0.5V, 0.75V, 1V, 1.25V, 1.5V and 1.8V) and temperatures (-40,-20, 0, 20,
40, 60, 80) in oC of CP.
 It help to find the limitation of circuit at different supply, temperature and
corner.

new waveform\pvt process.png

new waveform\convpvt.png
PVT Variation on conventional charge pump output
voltage
PVT Variation on proposed charge pump output
voltage
Example of PVT variation in proposed charge pump

new waveform\PVT
Comparison of different charge pump design with
proposed design

References Technology Output Operating Current Dynamic Maximum

voltage voltage mismatching glitches power
swing percentage dissipation

[3] 130nm 0.2~1 1.2V <3.2 Medium X

[14] 180nm 0.2~1.1 1.8V 1 Medium X

[8] 90nm 0.2~0.8 1V 1 Low 713 µW

[12] 90nm 0.2~1 1.2V <0.5 Low X

My work 90nm 0.5~1 1V 0.5 Low 320 µW

 Conclusion
In this thesis work, I have studied the behaviour and their functionality of

CP, which are used in designing of PLL. All the schematic of CP is done
at operating voltage 1V at 90nm CMOS technology.The proposed CP of
this thesis provides less power consumption of 320 µW, wide output
voltage swing of 0.5V to 1V, less current mismatching, PVT immunity at
1V to 1.3V at temperature range -30oC to 80oC and low Dynamic glitches.
 Future scope
 PLL and CP are vast topic of research due to numerous applications and it is an

important component of many communication systems. In this thesis work,

designed CP has improved output voltage swing, decreased the power
consumption and current mismatching, but further improvement in circuit by
using high slew rate operational amplifier with less power consumption and can
be made CP have improved switching operation and reduced charge sharing. To
make adjustable W/L ratio of transistor glitches in CP can reduce.
 Application
 A common application for charge pump circuits is in RS-232 level shifter where they are
used to derive positive and negative voltages (often +10 V and −10 V) from a single 5 V
or 3 V power supply rail.
 It can also be used as LCD or white LED drivers, generating high bias voltages from a
single low-voltage supply, such as a battery.
 It is extensively used in NMOS memories and microprocessors, to generate a negative
voltage "VBB" (approximate −3 V).
 charge pumps are integrated into almost all EEPROM and flash memory integrated circuit,
it used to erase cells.
 Charge pumps are used in H-Bridges in high side drivers for gate driving n-channel power
MOSFETs and IGBTs.
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Thank you