A Novel Current Steering Charge Pump with Low
Current Mismatch and Variation
Aya G. Amer, Sameh A. Ibrahim, and Hani F. Ragai
Department of Electronics and Communication Engineering
Ain Shams University, Cairo, Egypt
Email: aya.galal@eng.asu.edu.eg, sameh.ibrahim@eng.asu.edu.eg
Abstract—A charge pump circuit to minimize current
mismatch and current variation over a wide voltage compliance
range is proposed. A feedback loop is used to cancel both
deterministic and random mismatches between charging and
discharging current to minimize PLL reference spurs and static
phase offset. A current compensation circuit is used to minimize
current variation to avoid bandwidth variation and loop
instability. The circuit can operate at low supply voltage. The
power overhead due to added circuitry is 3.36% making it
suitable for low-power and low-voltage applications. The
proposed current-steering charge pump circuit achieves
mismatch lower than 0.44% over the output voltage range from
0.06 V to 0.85 V. Also the current variation is reduced to less than
1.19% when the output voltage varies from 0.06 V to 0.85 V in
the 65 nm CMOS process with 1 V supply.
Keywords—charge pump; current mismatch; PLL
I. INTRODUCTION
Conventional charge pump (CP) circuit non-idealities, such
as charge injection, charge sharing, clock feedthrough, and
charging and discharging current variation, greatly degrade the
performance in phase locked loops (PLLs). These non-
idealities worsen PLL stability, phase noise and increase
reference spurs. Also, random and systematic mismatches
between charging and discharging currents develop a phase
offset in the PLL resulting in increasing the PLL reference
spurs, phase noise, and jitter [1].
To overcome charge sharing, charge injection and clock
feedthrough, current steering charge pump (CSCP) shown in
Fig. 1 can be used [2]. The UP and DN switches are far from
the output node. Also, the current sources (M2, M7) are always
on, and this current is steered to the output or to other branches
depending on UP and DN signals. CSCP eliminates current
glitches and enhances switching speed among other topologies
reported in literature [3,4] since we do not need more time for
activating the current sources. This in turns enhances PLL
phase noise performance and reduces reference spurs.
Moreover, it is compatible with CML based PFD with
differential operation for inherent common mode rejection,
better noise immunity, and reduce sensitivity to power supply
noise.
However, the conventional CSCP suffers from current
variation and current mismatch between the charging and
discharging currents; Iup and Idn respectively. This is because of
the channel-length modulation effect of the output transistors
978-1-4799-5341-7/16/$31.00 ©2016 IEEE 1666
(M14, M15). This can be solved using long transistors in the
output stage to increase the output impedance. However, long
transistors can’t completely eliminate the effect and large
parasitic capacitance limits the speed and operation. A current-
compensation circuit can be used to extend the flat range of
output voltage significantly to minimize the current variation
[5,6]. Gain-boosted charge pumps use regulated cascodes to
increase the output resistance [7] for minimizing current
variation keeping the charging and discharging currents
approximately constant with the control voltage. However, this
lowers the voltage compliance range and a higher supply
voltage is needed for proper operation. This solution also
increases the power consumption since the op amps used
should have very large GBW.
Fig. 1. Conventional Current Steering CP
This paper presents a new technique for current-mismatch
cancellation and current-variation reduction in CSCP over a
wide voltage range. The paper is organized as follows: Section
II presents the proposed circuit with mismatch-cancellation and
current-compensation techniques. Detailed design is presented
in Section III. Section IV reports the simulation results. Finally,
Section V draws the conclusions.
II. PROPOSED CHARGE-PUMP CIRCUIT
The proposed CP is shown in Fig. 2. It utilizes a mismatch-
cancellation circuit to reduce current mismatch and a current-
compensation circuit to compensate for current variations. The
current-compensation circuit senses the output voltage and
controls part of the charging current, so that the total charging
current Iup is nearly constant over a wide output voltage range.
On the other hand, the mismatch-cancellation circuit senses any
mismatch between charging and discharging current. Then
according to this mismatch, the biasing of Idn is automatically
adjusted so that discharging current Idn follows any change in
the charging current Iup. At steady state, there is a very low
mismatch between the charging and discharging currents. The
complete circuit diagram of the proposed CSCP is shown in
Fig. 3.
Fig. 2. Proposed Charge Pump Concept
Fig. 3. Proposed Charge Pump Circuit (Icomp circuit is detailed in Fig. 4)
A. Mismatch Cancellation
A replica from charge pump circuit (Ma, Mb, Mc, Md) with
an integrating capacitor Cx, and an opamp A0 are used in a
negative feedback loop for cancelling random and deterministic
mismatches between charging and discharging current [8]. The
difference between I1 and I2, which is similar to the difference
between Iup and Idn, flows through the capacitor Cx increasing
(decreasing) Vx when I1 is larger (smaller) than I2. The opamp
A0 compares Vx with the average control voltage (voltage on
capacitor C1 in the PLL loop filter). The opamp output adjusts
Idn to follow variations in Iup. At steady state, Vx equals to Vout
which means that I2 is equal to I1 and so is Idn is equal to Iup.
Transistors (Me, Mf) are added to keep the feedback loop
working when UP or DN signal is high.
B. Current Compensation
The proposed current-compensation circuit is shown in Fig.
4. This technique compensates for current variation using
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transistors in triode region (Mc5 and Mc4) and current mirrors.
Mc5 and Mc4 are controlled by the output voltage of charge
pump Vout. Without current compensation, the charging current
decreases when output voltage increases because of the
channel-length-modulation effect, and Idn follows Iup variation
due to the negative-feedback loop used. With the current-
compensation circuit, the current mirrored to the CP output
(ICP) is Iref + Icomp with mirroring ratio (M), where Icomp=Ic2-Ic1.
The idea is based on increasing Icomp when Vout increases, or
decreasing Icomp when Vout decreases to account for ICP decrease
with the increase of Vout. When Vout is higher than Vth of MC5
(0.5 V), the transistors (Mc5, Mc6, Mc2) are activated, increasing
Ic2 and consequently increasing Icomp and ICP. On the other hand,
when Vout decreases towards zero, the transistors (Mc4, Mc3,
Mc1) are activated increasing Ic1, so Icomp decreases and
consequently decreasing ICP.
Fig. 4. Current Compensation Circuit
III. CIRCUIT DESIGN ISSUES
The negative feedback loop used must be stable for proper
operation. Frequency compensation is done using Rc and
Cc for a phase margin more than 45 degrees across corners.
The dominant pole of the loop (fpd) is located at node Vx
(opamp positive terminal). It can be expressed as in (1)
1
f =
gm
2π (r // r ) ∗ [C + C 1+A ∗ ]
gm
f ≅ (1)
( // )∗ ∗
where roc, and rod are the output resistance of transistors Mc,
and Md, respectively. gm7 and gm8 are the transconductance of
transistors M7 and M8, respectively. For perfect current
matching the DC open-loop gain, expressed in (2), should be
high enough. However, the speed is not very important because
no rapid changes occur. Also, the bandwidth of the loop given
in (3) must be at least 10 times the PLL bandwidth; such that
the PLL stability and settling behavior are not affected by this
loop. In this design, the DC open-loop gain is designed to be 80
dB, and the dominant pole is located at 2.7 kHz. Also, the loop
is stable with phase margin of 54o, whereas, the BW of the loop
has been adjusted to be 24 MHz which is about 40 times the
PLL BW (600 kHz).
 −gm gm −gm MHz which is higher than 10 times the PLL BW (600 kHz).
Aβ = A ∗ ∗ ∗ ∗ (−gm (r //r ))
gm gm gm Also, the DC open loop gain varies from 57.6 dB to 84.12 dB
which is high enough to reduce the current mismatch
Aβ (@DC) ≅ −A ∗ gm ∗ (r //r ) (2) significantly.

100
∗ ∗( )
( )
BW = ≅ (3)
∗ ∗
50

Gain(dB)
The opamp A0 plays an important role in the current
matching. It should have high enough gain to achieve very low 0
gain error and hence perfect matching between charging and
discharging currents. Also, it should be designed to support
rail-to-rail input common mode voltage. Moreover, it is -50

preferred to consume very low power. In this work, folded- 200 2 4 6 8

cascode topology with rail-to-rail input common mode has

been used for its simple design and high gain. The opamp 100
achieves gain of 51 dB, whereas the bandwidth is 1.6 MHz,

while consuming only 4.3 μW.
The current-compensation circuit should account for ICP
variation with Vout. Without current compensation, ICP
decreases when Vout increases according to (4)
I =I α 1+V α (1 +  (V −V
where  is the channel-length-modulation parameter. If ICP
changes from (I + ∆ ) to (I − ∆ ) in the voltage
compliance range, then Icomp, I , and I ranges can be
expressed in (5)
∆1 ∆2
− ≤(I =I −I )≤
M M
∆2
0≤I ≤ &I = 0, when 0.5 V ≤ V ≤V
M shows the current variation of the proposed CSCP when the
∆ current compensation technique is used under nominal
0≤I ≤ &I = 0, when V ≤V
where M is the mirroring ratio and equals to
The proposed technique can be used for low-voltage low-
power applications. It can operate at supply voltage down to
0.8 volts since there are no more than three transistors in the
stack. Also, the current flowing in the added branches can be
reduced to a very small value such that Iup is a multiplier from
I1 and the same for I2 and Idn. However, if the supply voltage is
reduced to be lower than 0.8 V, the folded-cascode opamp
should be replaced with another opamp that can work at lower
supplies.
IV. SIMULATION RESULTS
The proposed charge pump circuit was implemented in a
65-nm CMOS technology to be used in a PLL of 600 kHz
bandwidth. Stability analysis across temperature, process, and
supply corners has been done to the negative feedback loop to
ensure that loop is stable and the proposed technique works
properly under different conditions. Fig. 5 shows the open loop
gain and phase versus frequency under process variations when
the supply varies from 0.9 V to 1.1 V and temperature varies
from 0o to 85o. The phase margin of the loop varies from 45.83o
to 57.91o, whereas, the loop BW varies from 6.8 MHz to 37.2
Phase(degree)
0
-100
)) (4) -200 2
10 10
4 6
10
8
10
Freq(Hz)
Fig. 5. Loop Stability Analysis
Fig. 6(a) shows the charging current Iup and discharging
current Idn variation with the output control voltage Vout of the
conventional CSCP. Fig. 6(b) shows current variation in
proposed CSCP when the current compensation circuit is not
used. As shown, Iup decreases when Vout increases and Idn
follows Iup due to the negative feedback loop used. Fig. 6(c)
≤ 0.5 V (5) conditions. Fig. 6(d) shows current variation under process and
temperature variations. As shown, the current variation has
. been reduced significantly. Iup and Idn variation is from 150.78
μΑ to 148.22 μΑ, which is less than 1.19% when Vout varies
from 0.06 V to 0.85 V at nominal conditions, whereas the
variation is less than 7% across process and temperature
corners. Moreover, the current mismatch ratio of the proposed
CSCP varies from 0.435% to –0.023% while the percentage
mismatch in the conventional CSCP varies from 46.55% to
–16.2%, when Vout varies from 0.06 V to 0.85 V.
A conventional CMOS PFD circuit [1] followed by a
CMOS to CML conversion stage were designed to derive the
CSCP (a conventional CML PFD [2] can be used instead, but
this consumes more power). Noise analysis has been done to
the PFD/CP circuits (PSS & PNOISE) where the input signals
to PFD are in phase (PLL Locking at steady state), and the
output current noise versus frequency at 150 μA is shown in
Fig. 7. The proposed technique for CSCP increased the current
noise by less than 0.5 dB. Monte Carlo simulation has been
done to estimate the effect of random mismatch on the
conventional and proposed CSCP. As shown in Fig. 8, the
mean of current mismatch (Iup –Idn) has been reduced from 16.8
uA in the conventional CSCP to -46 nA in the proposed CSCP,
also the standard deviation is reduced from 1.9 uA to 0.9 uA.

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 The power consumption of the proposed CSCP is 0.332
mW at 1 V supply including the 150 μΑ current source. The
power overhead due to added circuitry for cancelling mismatch
and reducing current variation is 3.36%. The proposed
technique is one of the best solutions for mismatch cancellation
and current variation reduction without affecting the power,
noise, or PLL settling and stability. The layout of the proposed
CSCP is shown in Fig. 9, whereas the active area is 82 * 53
μm2. Table I summarizes the performance of the proposed
CSCP compared to other charge pump circuits reported in Fig. 9. Layout of the proposed CSCP
literature.
TABLE I. Performance Summary
REF [4] [6] [7] This Work
150 150
Tech. (nm) 65 130 180 65
Iup,Idn(uA)

Iup,Idn(uA)

100
Supply (Volt) 1 1.2 1.8 1
100
ICP (μA) 150 100 100 150
50 50 Iup
Compliance range 0.1-0.85V 0.2 - 1 V 0.4 – 1.4 V 0.1 – 0.85 V
Iup
Idn Idn I-Mismatch <0.03% 3.2 % NA < 0.03%
0 0 I-Variation <1.2 % 1.7 % <1 % < 1.2 %
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Vcontrol(volt) Vcontrol(volt)

(a) (b) V. CONCLUSION

A new technique for current-mismatch cancellation and
150 150 current-variation reduction in CSCP over a wide voltage range
is presented. Deterministic and random Current mismatch can
Iup,Idn (uA)
Iup,Idn(uA)

100 100 be cancelled using a negative feedback loop to adjust

50
discharging current to follow any changes in charging current.
50
Iup A current compensation circuit is used to minimize current
Idn
0 0 variation. This technique is suitable for low-supply operation
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
Vcontrol(volt) Vcontrol(volt) down to 0.8 V and low-power PLL since the power overhead is
3.36%. As a result, this charge pump is a suitable solution for
(c) (d) low reference spurs, low-power PLLs.
Fig. 6. CSCP charging and discharging current variation (a) conventional, (b)
proposed without current compensation, and (c) proposed with current ACKNOWLEDGMENT
compensation (nominal) (d) across process and temperature corners. This work was supported by the Egyptian Information
-200 Technology Industry Development Agency (ITIDA) under the
ITAC Program CFP#79.
Conventional
Current Noise(dB)

-210
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Fig. 8. Monte Carlo Simulation Results

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