1022 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO.
10, OCTOBER 2006
Gain-Boosting Charge Pump for Current Matching in
Phase-Locked Loop
Young-Shig Choi and Dae-Hyun Han
Abstract—The charge pump (CP) circuit is a key element in a
phase-locked loop (PLL). Its function is to transform the Up and
Down signals from the phase/frequency detector into current. In
CMOS CPs, which have Up and Down switches made of p-channel
MOS and n-channel MOS, respectively, a current mismatch
occurs when dumping the charge to the loop filter. This current
mismatch of the CP in the PLL generates fluctuations in the
voltage-controlled-oscillator input and subsequently, a large phase
noise on the PLL output signals. In this brief, a new CP with good
current matching characteristics is proposed. By using a simple
gain-boosting circuit, good current matching characteristics can
be achieved with less than 0.1% difference of the Up/Down current
over the CP output voltage ranges of 0.8–2.2 V and 0.5–1.2 V on
0.35- m 3.3-V and 0.18- m 1.8-V CMOS processes, respectively.
The proposed CP circuit is simulated and verified by HSPICE
with 0.35- m 3.3-V and 0.18- m 1.8-V CMOS parameters.
Index Terms—Gain-boosting charge pump (CP), phase-locked
loop (PLL), voltage-controlled resistor.
I. INTRODUCTION
P HASE-locked loops (PLLs) consist of a phase/frequency
detector (PFD), a charge pump (CP), a loop filter (LF), and
a voltage-controlled oscillator (VCO), whose output is fed back
to the PFD. The PFD compares an external reference signal and
the VCO output signal and produces two digital signals (Up
and Down), with the width of these two signals being deter-
mined by their frequency and phase. The CP converts the PFD
output signal into a current that is fed into the LF, which deter-
mines the output LF voltage. The LF output voltage causes the
VCO to generate a single frequency signal. Any fluctuation in
the LF output voltage due to current mismatch in the CP causes
a proportional variation in the VCO signal. The drain–source
voltage of the n-channel MOS (nMOS) and p-channel MOS
(pMOS) in the conventional CP can vary depending on the latter
one’s output voltage, thereby causing the magnitude of the cur-
rents in the pMOS (Up) and nMOS (Down) to differ. The LF
output voltage fluctuates due to the current mismatch in the CP
when the PLL is in the locking state; this causes the VCO output
signal to have a large amount of phase noise with spurs [1].
Manuscript received March 15, 2005; revised December 14, 2005. This paper
was recommended by Associate Editor T. Ueta.
Y. S. Choi is with the Division of Electronic, Computer, and Telecommunica-
tions Engineering, Pukyong National University, Busan 608-737, Korea (e-mail:
choiys@pknu.ac.kr).
D. H. Han is with the Department of Electronic Engineering, Dongeui Uni-
versity, Busan 614-714, Korea (e-mail: dhan@deu.ac.kr).
Digital Object Identifier 10.1109/TCSII.2006.882122
1057-7130/$20.00 © 2006 IEEE
The classical approach to CP employs a cascode [2], [3] and
low-voltage cascode topology [4] to reduce the current mis-
match by increasing its output resistance. These CPs show the
current matching characteristics down to 2% of the sourcing/
sinking current difference. CPs with operational amplifiers show
good current matching characteristics of less than 1% of the
sourcing/sinking current difference; however, these CP circuits
require a large and oscillation-prone operational amplifier [5],
[6]. A differential CP with an active LF and common-mode
feedback scheme has been used to reduce the current mismatch
[7]. However, it requires operational amplifiers, a reference-
voltage circuit, and an analog adder. A replica CP circuit and
a bias generator are added to compensate the current mismatch
down to 1% [8]. It makes the locking time longer and requires
more complicated circuits. An additional CP with a modified
PFD is included to compensate the current mismatch [9]. Fabri-
cation mismatches between two CPs can cause the unexpected
current mismatch in [9].
In this brief, we propose a new CP circuit with a gain-boosting
circuit to increase the output resistance of the CP. In this way,
good current matching characteristics can be achieved without
the need for stacking more cascode devices, operational ampli-
fiers, a feedback circuit, a complicated replica CP, or an addi-
tional compensation CP.
II. GAIN-BOOSTING CP
Conventional CMOS CPs usually have Up and Down
switches made of pMOS and nMOS, respectively. In this case,
a current mismatch occurs due to the difference between the
drain–source voltages of the pMOS and nMOS when dumping
the charge to the LF. In this brief, we propose a new CP circuit
with a gain-boosting circuit, which requires only a few more
transistors than the conventional CP. Fig. 1(a) and (b) shows
the concept of the gain-boosting circuit and the simplified
gain-boosting circuit, respectively [10]. The idea is to drive the
gate of M2 by an amplifier that forces to be equal to .
Thus, voltage variations at the drain of M2 affect to a lesser
extent because regulates this voltage. Due to the smaller
variations at node X, the current through and hence the
output current remain more constant, thereby yielding higher
output impedance. The output resistance of the gain-boosting
circuit is given as follows:
(1)
Therefore, can be boosted substantially without the need
to stack more cascode devices on top of M2. Since is set to
zero for small-signal operation, the circuit can be simplified as
CHOI AND HAN: GAIN-BOOSTING CHARGE PUMP FOR CURRENT MATCHING
Fig. 1. (a) Concept of the gain-boosting circuit. (b) Simplified gain-boosting
circuit.
Fig. 2. Gain-boosting circuit.
Fig. 3. Proposed CP circuit.
shown in Fig. 1(b). The circuit can be implemented with the
single transistor amplifier (M3) shown in Fig. 2, exhibiting an
output resistance equal to
(2)
which is similar to the output resistance of a triple-cascode cir-
cuit. By using this gain-boosting circuit, a new CP can be de-
signed, in which the channel length modulation effect is less-
ened. In Fig. 3, which shows the proposed CP, MP4, and MN4,
are the current sources for the single-transistor amplifiers MN3
and MP3, respectively. The output resistances of MN1 and MP1
are used as , as shown in Fig. 2. When the DN signal is active,
MN2 and MN3 operate in conjunction with MN1 to provide a
1023
Fig. 4. Current matching characteristics of CP without gain-boosting circuit (a)
at a 0.35-m 3.3-V CMOS process and (b) at a 0.18-m 1.8-V CMOS process
[Up current (solid line) and Down current (dashed line)].
gain-boosting circuit. This increases the output resistance of the
CP circuit and enhances the current matching characteristics.
This gain-boosting CP circuit is suitable for a low power supply
voltage because it does not require stacking more cascode de-
vices to increase the output resistance. Since the transconduc-
tance and output resistance of the nMOS and pMOS are dif-
ferent, the enhancement of the output resistance of the two tran-
sistors in (1) cannot be the same, and this can result in cur-
rent mismatch. Therefore, the of both DN and UP circuits
should be designed so that they are identical by carefully se-
lecting the value of each component.
III. SIMULATION RESULTS
The proposed CP and the conventional CP without a gain-
boosting circuit are simulated by HSPICE with 0.35- m 3.3-V
and 0.18- m 1.8-V CMOS parameters. Fig. 4 shows the varia-
tion of the Up/Down current without a gain-boosting circuit as
the CP output voltage sweeps from 0 to 3.3 V with 0.35- m
3.3-V and from 0 to 1.8 V with 0.18- m 1.8-V CMOS pa-
rameters, respectively. These CPs show the current matching
characteristics around 5% of the sourcing/sinking current dif-
ference. Fig. 5 shows the variation of the Up/Down current with
a gain-boosting circuit as the CP output voltage sweeps like
1024 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006
Fig. 5. (a) Current matching characteristics of CP with gain-boosting circuit.
Differences in Up/Down current (b) at 0.35-m 3.3-V CMOS process and (c)
at 0.18-m 1.8-V CMOS process [Up current (solid line) and Down current
(dashed line)].
TABLE I
TRANSISTOR SIZES OF THE PROPOSED CHARGE PUMP IN FIG. 3
(Length = 0:45 m WITH THE 0.35-m PROCESS AND Length = 0:3 m
WITH THE 0.18-m PROCESS)
the conventional CP. Good current matching characteristics are
observed over the CP output voltage ranges of 0.8–2.2 V and
0.5–1.2 V with 0.35- m 3.3-V and 0.18- m 1.8-V CMOS pro-
cesses, respectively. The maximum difference of the Up/Down
current is less than 0.1%, as shown in Fig. 5(b) and (c). The sizes
Fig. 6. Simulation results of the current matching characteristics with a
0.18-m CMOS process when the transconductance and output resistance of
the MN2 and MP2 are not identical.
of the transistors that affect the most the current matching char-
acteristics are listed in Table I. The longer the channel length,
the better the current matching characteristics. Fig. 6 shows the
simulation result of the current matching characteristics when
the transconductance and output resistance of the nMOS and
pMOS are not identical and that the maximum difference of the
Up/Down current is less than 0.15% when only one of MP2’s
and MN2’s widths changes to 2%. In the case of MP3 and MN3
used as amplifiers, it shows less than 0.25%. When the width
of MN1, MN2, and MN3, and MP1, MP2, and MP3 changes to
or 5% together, the absolute value of the current changes
to 0.35%, but it shows good current matching characteristics of
less than 0.15%.
IV. CONCLUSION
In this brief, a gain-boosting CP that has good current
matching characteristics in the PLL is proposed. By using a
simple gain-boosting circuit to increase its output resistance,
a CP with good current matching characteristics is achieved
without the need for stacking more cascode devices, opera-
tional amplifiers, a feedback circuit, a complicated replica CP,
or an additional compensation CP. The maximum difference
of the Up/Down current over the CP output voltage range of
0.8–2.2 V and 0.5–1.2 V with 0.35- m 3.3-V and 0.18- m
1.8-V processes, respectively, is less than 0.1%. It shows a
current mismatch of less than 0.15% when the 5% variation
in the size of transistors is introduced to assume the process
variation. It is still better than that of other CP circuits, which
show the best current mismatch down to 1%. The proposed CP
has good current matching characteristics and is also suitable
for low-power-supply-voltage operation because it does not
require stacking more cascode devices.
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