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An improved Valley-Fill passive Power-Factor-Correction circuit for

electronic ballast

Conference Paper · May 2008

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 ELECTRIC POWER ENGINEERING 2008

An improved Valley-Fill passive Power-Factor-Correction circuit

for electronic ballast
Jiří Drápela1), Jaromír Bok
Brno University of Technology, Faculty of Electrical engineering and Communication, Department of Electrical Power
Engineering, Technická 8, 616 00 Brno, Czech Republic, www.feec.vutbr.cz/UEEN
1)
tel: +420 5 4114 9234, email: drapela@feec.vutbr.cz

ABSTRACT
The paper deals with an improvement of the Valley-
Fill (VF) Power Factor Correction (PFC) circuit for Elec-
tronic Ballast (EB), which reduces input harmonic current
emissions in compliance with EN 61000-3-2 standard and
at the same time keeps an output voltage ripple at minimal
value as it is necessary for possible assurance of good op-
eration characteristics of an electronic ballast with such
type of the power factor correction circuit.
Keywords: Harmonic current limits, passive PFC tech-
niques, Valley-Fill passive PFC, Electronic ballast
1 INTRODUCTION
Electronic ballasts are generally required to comply, as
many other electrical equipment types, with electromagnetic
compatibility (EMC) specifications such as EN 61000-3-2
[1], which determines maximum limits for harmonic compo-
nents in input current for electrical appliances with input
current RMS value up to 16A per phase.
For 230 VRMS distribution systems, the electronic ballast
generally consists of a Half Bridge (HB) resonant inverter,
which has to be supplied from a source of DC voltage and
consequently in direction to supply network, of an AC/DC
feeding converter. As the AC/DC converter, in simplest case,
there is used a bridge-diode rectifier with a large bulk capaci-
tor connects to its output (Fig. 1). That diode rectifier is asso-
ciated with high level of input current harmonics emission.
Concerning the limits of the EN 61000-3-2 standard for light-
ing devices, such low power factor supplying circuit is not
sufficient for electronic ballast with input power P>25 W.
S1 Lr
IC
CDC
Cr
S2
EMI filter
Fig. 1. Electronic ballast
For this reason, many active and passive power factor cor-
rection techniques have been proposed and are used. Al-
though the active power factor correction circuits generally
have higher Power Factor (PF) (>0.98), lower Total Har-
monic Distortion (THD) (< 10%), excellent lamp operation
DRÁPELA, J. and BOK, J., 2008. "An improved valley-fill passive power-factor-correction circuit for electronic
ballast", Proceedings of the 9th International Scientific Conference Electric Power Engineering 2008, EPE
2008, 2008, pp. 149-155, ISBN 978-80-214-3650-3.
characteristics and are smaller in size over the passive PFC
circuit, the disadvantages are higher cost, more complicated
circuit design, potentially lower efficiency, and many EMI
problems. The passive PFC approach is attractive for low
power applications due to low cost, possible high efficiency,
excellent reliability, simple circuit design and very low gen-
erated EMI. In general, the passive power factor correction
approach is suitable for low-power low-cost light sources,
because the used chokes and storage capacitors can be kept to
feasible sizes and costs.
The passive PFC circuits can be generally divided into an
inductive and capacitive type [8]. The passive inductive PFC
circuit is simply the use of an inductor in the input circuit,
which forms with the bulk DC bus capacitor a serial LC filter.
But in case of the electronic ballast with input active power
over 25 W, a large LC filter has to be used to achieve the
compliance with EN 61000-3-2. It means usage of large
heavy chokes, since they work at the mains frequency.
The passive capacitive PFC based circuit employing ca-
pacitor-diode block and named passive Valley-Fill PFC can
improve power factor and reduce harmonic distortion of the
input line current with reduction in volume [2] (Fig. 2). How-
ever the VF-PFC circuit operating principle causes an enor-
mous output DC voltage ripple. So a lamp current waveform
of such ballast is highly modulated due to this high level DC
bus voltage ripple. The high lamp current waveform modula-
tion and moreover possible lamp re-strikes every half cycle
lead to reduction in the lamp life [5]. To overcome the disad-
vantage of the very high lamp current crest factor, an addi-
tional circuit can be used to modulate the Half Bridge
frequency versus the bus voltage [5] [6]. The system works at
a minimum frequency when the bus voltage is low and in-
crease the frequency while the bus voltage increases. This can
stabilize the lamp power versus the AC line changes and
improve the current crest factor. Nevertheless this system can
work effectively only if the DC bus voltage ripple magnitude
is not oversized [6].
2 ORIGINAL VALLEY-FILL PFC CIRCUIT
The original Valley-Fill circuit is shown in Fig. 2. The
capacitors CVF1 and CVF2 are charged in series, and dis-
charged, via the diodes DVF1 and DVF2, in parallel. Each ca-
pacitor is charged to ½ of the AC peak voltage (Us,m), minus
three diode drops - two in the bridge rectifier and one in the
diode between the two capacitors. Indeed symmetrical VF
network (CVF1=CVF2) is supposed. Diode DVF3 is inserted to
prevent CVF2 from discharging via CVF1.

iS CVF1 DVF2 iL
~ uS uDC RL
DVF3
DVF1 CVF2
Fig. 2. Original passive Valley-Fill PFC circuit
Since each capacitor is charged to half the peak AC volt-
age, they supply output current only after the bus voltage
follows the sinusoidal waveform down to Us,m /2. At this time
the capacitors are essentially in parallel and supply load cur-
rent until the rectified AC input again exceeds Us,m /2 on the
next half cycle. The discharge duty cycle for the capacitors is
approximately 37% followed by an idle period during which
time the load is being supplied directly from the rectified AC
input. At the peak of the input AC voltage there is an addi-
tional current to re-charge the capacitors up to Us,m. The mag-
nitude and duration of this current is a function of the depth
of discharge. So the input AC current is discontinuous and in
ideal case is drawn from the line for 120° in each half period
of the fundamental system frequency. It mean the input cur-
rent conduction is from 30° to 150°, and then from 210° to
330°.
The H-B resonant inverter loaded by a Fluorescent Lamp
(FL) is replaced with load RL in Fig. 2. This simplification
definitely affects waveform of the line current because of
nonlinear static VA characteristic of the FL. But for such
analysis, that influence can be neglected in first step.
Fig. 3 shows the input current and DC bus voltage wave-
forms, obtained by simulations in PSpice, for original VF-
PFC with different VF network capacitors value. The circuit
load has been set by RL to 23 W. As can be seen from Fig. 3,
the input current conduction duration and the DC bus voltage
ripple magnitude is indirectly proportional to VF capacitors
value or more precisely to VF capacitors value and their
loading. The VF-PFC circuit capacitance has to be designed
with respect to optimal ratio between acceptable minimum of
the DC bus voltage, the input current distortion level and the
capacitors volume. It results in CVF1=CVF2= (0.4-0.25) μF/W.
Fig. 3. Waveforms of the output DC voltage and input line
current of the original VF PFC circuit (PL=23W)
Relative amplitude spectrum of the input current of the
original VF-PFC circuit (Fig. 3 - CVF1=CVF2=6.8μF, PL=23W)
is in percentage of fundamental harmonic component at Fig.
4. Total harmonic distortion of the line current is close to
35% and power factor is 0.942. Using the original VF-PFC
circuit, the line current distortion of electronic ballast (Fig. 1)
is significantly reduced. However the high order line current
harmonics limiting is not sufficient in comparison with limits
of the standard [1] for lighting devices. Actually, the ballast
with active power up to 25 W can meet the standard specifi-
cations as it is shown in Fig. 4, because of additional condi-
tions given by the standard [1].
80 simulation Limits of EN 61000-3-2 table 3
(Iν/I1).100 (%)
60
40
20
0
3 5 7 9 11 13 15 17 19 21 23 25 ν27
(-) 29
Fig. 4. Comparison of the original VF-PFC circuit input
line current harmonics (Fig. 3 - CVF1=CVF2=6.8μF,
PL=23W) with limits of the standard EN 61000-3-2
But for lighting devices with input power over 25 W, the
limits for harmonic current emissions are much more strict
and electronic ballast power factor correction using original
VF-PFC circuit is not satisfactory.
3 VALLEY-FILL PFC CIRCUIT MODIFICATIONS
For a next decreasing of the line current distortion level
and corresponding harmonics emission, the current conduc-
tion time in half-period has to be enlarged. The peak charging
pulse is also a major contributor of current harmonics and its
suppression reduces line current harmonics level as well.
One of the possible solutions, there is VF bridge stages
expansion to 3, 4 or more capacitors type VF rectifier [4].
The three capacitors type VF-PFC circuit is at Fig. 5
iS DVF2 iL
CVF1
DVF3 DVF5
~ uS
DVF1 CVF2
uDC RL
DVF6
DVF4 CVF3
Fig. 5. Three capacitors type VF-PFC circuit
The capacitors in the modified VF rectifier are also
charged in series and discharged in parallel. It stands to rea-
son that this modification again increase the DC bus voltage
ripple magnitude. Minimum value of the DC bus voltage
depends on number of VF net capacitors nC according to
following equation, at best:
max[u DC ]
min[u DC ] = (1)
nC
That means the electrical characteristics changes are of dis- Fill rectifier network [3][6]. Resulting modified VF-PFC
crete pattern. And as it is expected, the line current distortion circuit is on Fig. 8.
level becomes less also with the number of VF rectifier ca-
pacitors. Minimal line current conduction time can be ex- iS CVF1 DVF2 iL
pressed as follows:
⎛ 1 ⎞ ~ uS uDC RL
d min = 2 ⋅ arccos⎜⎜ ⎟ for nC=2,3,4, .., (rad;-) (2)
⎟ DVF3 RVF
⎝ nC ⎠
Simulation results of the 2, 3 and 4-capacitors type VF- DVF1 CVF2
PFC circuit are shown in Fig. 6. Relative amplitude spectrum
of the 3-capacitors type VF-PFC circuit input current is Fig. 8. VF-PFC circuit with smoothing resistor
shown in Fig. 7.
The smoothing resistor, which is in series with the capaci-
tors during their charging process, decreases the maximal
voltage on capacitors and in compliance with VF-PFC circuit
operation principle described above, the input current con-
duction time is continuously extended in dependence on RVF
value. Moreover the charging spike in input current is
smoothed. The resistor also reduces commutating spikes, but
at the same time increases the circuit losses. However, since
the power content of this charging spike is not so high, it can
be suppressed without too much reduction in efficiency.
Simulation results of the VF-PFC circuit with smoothing
resistor of three values are shown in Fig. 9. As it can be seen,
the bigger resistance RVF the lower input current distortion is,
but at the same time it means the bigger DC bus voltage rip-
ple magnitude.
Fig. 6. Waveforms of the output DC voltage and input line
current of the 2, 3 and 4–capacitors type VF-PFC circuit
(PL=36W)
30 Simulationí Limits of EN 61000-3-2 table 2
25
(Iν/I1).100 (%)

20
15
10

5
0
3 5 7 9 11 13 15 17 19 21 23 25 ν27
(-) 29
Fig. 9. Waveforms of the DC bus voltage and input line
Fig. 7. Comparison of the three capacitors type VF-PFC current of the VF-PFC circuit with smoothing resistor of
circuit input line current harmonics (Fig. 6) with limits of 0.1, 2 and 500 kΩ (PZ=36W, CVF1=CVF2=10μF )
the standard EN 61000-3-2
30 Simulation Limits of EN 61000-3-2 table 2
Even if the input current THD is lower then before
(15.6%), requirements of the standard [1] are not fulfilled 25
(Iν/I1).100 (%)

again because of the 9th harmonic magnitude (Fig. 7). More- 20

over increase in the DC bus voltage ripple magnitude is unac-
ceptable. 15
The reason of sequential variation of the current harmon-
10
ics in magnitude is a dependence of the each input current
harmonic component magnitude on input current conduction 5
time for this waveform type, which is not monotone decreas-
0
ing. Mathematical derivation of that cause is performed in
[8]. Because of that relation, the optimal input current wave- 3 5 7 9 11 13 15 17 19 21 23 25 ν 27
(-) 29
form fulfilling the standard [1] requirements has to be find Fig. 10. Comparison of the modified VF-PFC circuit input
out using a VF-PFC circuit modification with continuous
line current harmonics (Fig. 9-CVF1=CVF2=10μF, RVF=2kΩ,
input current conduction time extension. It can be realized by
PZ=36W) with limits of the standard EN 61000-3-2
connecting a smoothing resistor RVF into the original Valley-
 So there is necessary to find out the optimal RVF value. In
this case, the input current harmonic magnitudes comply with
the standard [1] limits for smoothing resistor value of 2 kΩ.
Relative amplitude spectrum of the input current is shown in
Fig. 10. Total harmonic distortion of the line current is close
to 17.1% and power factor is 0.985. Apparently the current
THD is relatively low, but the resulting uDC ripple magnitude
is still too high for effective working of the frequency modu-
lated H-B resonant inverter [6], even if it is less than for the
VF-PFC circuit type at Fig. 5. Comparison of each simulated
VF-PFC circuit significant electrical characteristics is in
Table 1.
Simulation results of the VF-PFC circuit with voltage
doubler are shown in Fig. 12 and relative amplitude spectrum
of input current is in Fig. 13. Even if the VD do not causes
additional DC bus voltage drop, decrease in the input current
distortion is insufficient and that rectifier cannot meets the
requirements on harmonic current emission, mainly because
of the 11th harmonic component magnitude (Fig. 13). The line
current THD is 26.1%
30 Simulation Limits of EN 61000-3-2 table 2
25

(Iν/I1).100 (%)
20
4 VF-PFC CIRCUIT WITH VOLTAGE DOUBLER 15
All VF-PFC circuits’ modifications to improve line cur- 10
rent waveform described before are based on simultaneous
decreasing of the minimum DC bus voltage. So another tech- 5
nique stretching the conduction time of the current drawn
0
form line without additional drop in DC bus voltage should
be used. In [3], to maintain the flow of input current a Volt- 3 5 7 9 11 13 15 17 19 21 23 25 ν27
(-) 29
age Doubler (VD) is inserted to feed the valley-fill circuit.
Fig. 13. Comparison of the input line current harmonics
The VF-PFC circuit with the voltage doubler is in Fig. 11.
(Fig. 12) with limits of the standard EN 61000-3-2

iS CVF1 DVF2 iL So for fulfilling the standard [1], the smoothing resistor
RVF has to be employed again, with all the consequences. In
CVD1 this case, the optimal resistance RVF is also 2kΩ, then the line
~ uS
DVF3 RVF
uDC RL
current THD goes to 10.8% and the minimal DC bus voltage
CVD2 is still lower than it is acceptable. Results are in Table 1.
DVF1 CVF2

5 VF-PFC CIRCUIT WITH CHARGE PUMP

Fig. 11. VF-PFC circuit with smoothing resistor and volt-
In all above described VF based rectifiers, the input cur-
age doubler
rent waveform improvement to meet the EN 61000-3-2 stan-
The voltage doubler is designed to contribute a very small dard requirements means the perceptible reduction in
amount of power to the main circuit, just enough to improve minimum DC bus voltage. For this reason, a novel Valley-
the current waveform at the moment of current cross-over. Fill Power Factor Corrector has been proposed and simulated.
That means the capacitors CVD1 and CVD2 used for the voltage The new VF based rectifier consists mainly of modified two
doubler are small in value against to the VF stage capacitors. capacitors VF-PFC circuit and of a Charge Pump (CP), which
Under normal operating conditions, the energy from the volt- is connected between neutral conductor and center of sym-
age doubler is fully absorbed by the main circuit and the VD metrized VF network. Proposed circuit topology is shown in
capacitors are recharged again during the current cross-over, Fig. 14.
thus further it extends the input current conduction angle.
iS
D1 D2
CpH RpH CVF1 DVF2
DVF4 iL
i VFH
i CPH RVF1
~ uS
CpL RpL RVF2 uDC RL
i VFL
DVF3
D3 D4 i CPL DVF1 CVF2

Fig. 14. Proposed Valley-Fill based rectifier with charge

Fig. 12. Waveforms of the DC bus voltage and input line
current of the VF-PFC circuit with voltage doubler
(PZ=37W, CVF1=CVF2=10μF, CVD1=CVD2=330nF )
pump
The CP Lower branch (CpL) positively compensates
changes between current drain from the line and charging
current of the VF bridge, and consequently improves the
input current and DC bus voltage waveforms. At the suitable
capacitance of CpL, the spike in input current waveform,
which is typical for original VF-PFC, can be removed com-
pletely. Fig. 15 shows simulation results of the proposed VF-
PFC circuit.
Fig. 15. Waveforms of the DC bus voltage and input line
current of the Valley-Fill based rectifier with charge pump
(CVF1=CVF2=10μF, RVF1=RVF2= 0Ω, CpH=0nF,
RpH=0Ω, CpL=1.2μF, RpL=0Ω, PZ=37W)
The operation principle can be explained with the help of
the waveforms given in Fig. 16 and is depicted as follows.
At time t0-t1: At t0, uDC is higher than uS , so all bridge recti-
fier diodes D1-D4 are off. At the same time discharging of
CVF2 via DVF2 to RL is almost finished (iVFL). Actual voltage
on CpL is at maximum and prevents simultaneous CVF1 dis-
charging (iVFH); all other VF net diodes are off. After t0, uS
increases form zero in a sine waveform and then a sum of uS
and the voltage on CpL become bigger than the DC bus volt-
age. So D1, DVF1 and DVF3 become conducting, while DVF2,
DVF4 and D2-D4 are off, and CpL is discharged via D1, DVF1 Fig. 16. Important waveforms of the proposed VF-PFC
and DVF3 to RL (iCPL), until the line voltage is lower than the circuit (CVF1=CVF2=10μF, RVF1=RVF2=0Ω, CpH=0nF,
DC bus voltage. At the same time CFV1 is charged by extra RpH=0Ω, CpL=1.2μF, RpL=0Ω, PZ=37W)
current from the line via D1, DVF3 and CpL (iVFH), while the
voltage on CVF1 and DC bus voltage increase (uDC) and volt-
age on CpL becomes in sine shape to zero. Even if the supply
network voltage is lower then the DC bus voltage in this
period, the CpL allows current drain from supply network (iS).
At time t1-t2: After t1, the line voltage is bigger than the DC
bus voltage, D4 begins conduct, while DVF1 becomes reverse
biased and the load is supplied directly from the line. More-
over, increasing line voltage causes extra charging of the
capacitor CVF1 and charging of CpL, which are connected in
series via DVF3 (iVFH, iCPL). Because the capacitance of CpL is
much smaller compared to the each VF capacitors and charg-
ing current flows until the line voltage achieves the peak
value (t1-t2), the charging spike drawn from the line is rela-
tively small in magnitude (iS).
At time t2-t3: After t2, the line voltage now decreases but is
still higher than DC bus voltage and the load is continuously
supplied directly from the line (iS). However DVF3 becomes
reverse biased, while the capacitors CpL and CVF1 have been
charged on maximum voltages, which are in relation as fol-
lows: uVF1>uVF2>uCPL. The actual DC bus voltage prevents all
of those capacitors from discharging to the load (iVFH, iVFL,
iCPL). Diodes DVF1-DVF2 are off.
At time t3-t4: After t3, the rectified line voltage becomes
lower than the voltage on CVF1, so DVF1 is switching on, while
D1 and D4 are reverse biased (iS), and CVF1 is discharged to
the load (iVFH). Consequently the voltage on CVF1 and DC bus
voltage decreases, till the voltages on CVF1 and on CVF2 are Fig. 17. Important waveforms of the proposed VF-PFC
equal (t4). circuit (CVF1=CVF2=10μF, RVF1=RVF2=0Ω, CpH=220nF,
RpH=0Ω, CpL=1.2μF, RpL=0Ω, PZ=37W)
At time t4-t5: After t4, uS starts form zero in a sine waveform
to the negative half-wave and then the sum of uS and the
voltage on CpL become bigger than the DC bus voltage. So
D3, DVF2 and DVF4 become conducting, while DVF1 is becomes
reverse biased and DVF3, D1, D2 and D4 are still off, and CpL is
discharged via DVF4, DVF2 and D3 to RL (iCPL), until the line
voltage is lower than the DC bus voltage. At the same time
CFV2 is charged by extra current from the line via DFV4, D3
and CpL (iVFL), while the voltage on CVF1 and DC bus voltage
increase (uDC) and voltage on CpL becomes in sine shape to
zero.
For intervals t5-t6, t6-t7, t7-t8 can be performed a similar
conclusions as in intervals t1-t2, t2-t3 and t3-t4, respectively.
simulations, the optimal resistors values of the final CP-VF-
PFC circuit, which are necessary to meeting the standard [1]
requirements for lighting devices, are as follows:
RVF1=RVF2=200Ω, RpH=0Ω and RpL=82Ω. The input current
and DC bus voltage waveforms of the proposed CP-VF-PFC
type rectifier, obtained by simulations, are in Fig. 18. And
finally, the relative amplitude spectrum of input current is in
Fig. 19. The circuit operates with efficiency of 97%. Com-
parison of each simulated circuit significant electrical charac-
teristics is in Table 1.
30 Simulation Limits of EN 61000-3-2 table 2
25

As it is obvious the VF capacitor are no more charged in
series and discharged in parallel, but charging and discharg-
ing of that capacitors alternate with the help of the charge
pump capacitor CpL. The optimal capacitance of the CpL is as
follows
PL
C pL =
2πf 1U S2, RMS
Even if the DC bus voltage ripple magnitude is lower than
in case of the original VF-PFC (Table 1) and input current
distortion is at relatively low level (15%), compliance with
standard [1] is not achieved yet.
The CP upper branch (Fig. 14) consists mainly of a ca-
pacitor CpH. Influence of the capacitor CpH on the circuit
electrical characteristics is shown in Fig. 17. As it can be
seen, CpH is the next input current shaper. Actually its func-
tion is to compensate a conduction angle of the current which
flows between the CP and the VF network centre and to adapt
that way the input current waveform in start of each half-
period. Capacitance of CpH should be five times smaller in
value than CpL. The resulting change in input current wave-
form leads to reduction of the lower frequency harmonics. As
it is necessary, but it is still not enough to meet the EN
61000-3-2 limits.
Fig. 18. Waveforms of the DC bus voltage and input line
current of the Valley-Fill based rectifier with smoothing
resistors and with charge pump (CVF1=CVF2=10μF,
RVF1=RVF2=200Ω, CpH=220nF, RpH=0Ω, CpL=1.2μF,
RpL=82Ω, PZ=37W)
So the smoothing resistors have to be applied again. The
smoothing resistors (RpL, RpH, RVF1 and RVF2) are connected
in series with all CP and VF stage capacitors (Fig. 14). Using
(Iν/I1).100 (%)
20
15
10
5
(3)
0
3 5 7 9 11 13 15 17 19 21 23 25 ν27
(-) 29
Fig. 19. Comparison of the input line current harmonics
(Fig. 18) with limits of the standard EN 61000-3-2
6 CONCLUSION
An original valley-filled PFC circuit, its modifications,
VF-PFC with voltage doubler based shaper and finally a new
VF based rectifier with charge pump (denoted as CP-VF-
PFC) have been described, simulated, and compared with the
standard EN 61000-3-2 specifications.
This circuit types are ideally suited for constant load ap-
plications such as fluorescent lamp electronic ballasts. But
there is a disadvantage that consists in very high level of
output voltage ripple related to valley-fill circuit operation
principle. Application of this type circuit for electronic ballast
feeding results in high lamp current crest factor. The possible
solution is to use frequency modulated half-bridge resonant
inverter. However this system can work effectively only if the
DC bus voltage ripple magnitude is not oversized.
Moreover the original valley-fill power factor corrector
circuit on its own is not able to meet EN 61000-3-2 require-
ments. But previously proposed VF based rectifier modifica-
tions to comply with the standard leads to perceptible
decrease in minimum output voltage. The newly proposed
charge pump valley fill based power factor circuit, which
operation principle has been depicted in details, is capable of
fulfilling all that requirements.
There is necessary to take into account that the results
should be different when the H-B resonant inverter is applied
on the VF rectifier output instead of resistive load.
ACKNOWLEDGEMENTS
This paper contains the results of research works funded
from project No. MSM0021630516 of the Ministry of Educa-
tion, Youth and Sports of the Czech Republic.
Table 1. Comparison of significant electrical characteristics of simulated Valley-Fill based rectifiers
Conduction Compliance with
Description and parameters of the Valley-Fill passive THDIs UDC,min
iS angel PF (-) EN 61000-3-2
PFC circuit (%) (V)
d/π (-) table 2
Original circuit – CVF1=CVF2=6.8μF, PZ=23W Fig. 3 0.690 34.0 0.942 N (table 3) 160
Original circuit – CVF1=CVF2=10μF, PZ=37W - 0.689 33.6 0.946 N 145
Three capacitors type – CVF1=CVF2= CVF3=6.66μF,
Fig. 6 0.795 15.6 0.988 N 103
PZ=36W
With smoothing resistor – CVF1=CVF2=10μF,
Fig. 9 0.750 17.1 0.985 Y 122
RVF=2kΩ, PZ=36W
Basic circuit and voltage doubler - CVF1=CVF2=10μF,
Fig. 12 0.836 26.1 0.951 N 148
CVD1=CVD2=330nF, PZ=37W
Basic circuit, voltage doubler and smoothing resistor -
CVF1=CVF2=10μF, CVD1=CVD2=330nF, RVF=2kΩ, - 0.865 10.8 0.982 Y 124
PZ=36W
Valley-Fill based rectifier with charge pump -
CVF1=CVF2=10μF, CpH=0nF, RpH=0Ω, CpL=1,2μF, Fig. 15 0.821 15.0 0.957 N 153
RpL=0Ω, PZ=37W
Valley-Fill based rectifier with smoothing resistors
and with charge pump - CVF1=CVF2=10μF, RVF1=
Fig. 18 - 14.4 0.964 Y 140
RVF2=200Ω, CpH=220nF, RpH=0Ω, CpL=1,2μF,
RpL=82Ω, PZ=37W

REFERENCES

[1] EN 61000-3-2. Electromagnetic Compatibility, Part 3,

Section 2. Limits for harmonic current emissions
(equipment input current ≤16A per phase)
[2] Spangler, J., et al. Electronic Fluorescent Ballast using
Power Factor Correction Techniques for Loads Greater
than 300 Watts. Proc. Sixth Annual Applied Power
Electronics Conf., Hyatt Regency, Dallas, Texas, 1991,
pp. 393-399.
[3] SUM, K. K. Improved Valley-Fill Passive Current
Shaper [on line]. PowerSystem World’97, 8pp.
[4] Dalapati, S., Chakraborty, Ch., Biswas, S. K. A Compara-
tive Assessment of Passive and Active Power Factor
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