A Nanoscale CMOS Charge Pump with Near Perfect

Current Matching
Sleiman Bou-Sleiman Mohammed Ismail
Analog VLSI Laboratory Analog VLSI Laboratory
The Ohio State University The Ohio State University
Columbus, OH 43202 Columbus, OH 43202
bousles@ece.osu.edu ismail@ece.osu.edu
Currently with Intel Corporation Currently with KUSTAR, UAE

voltage, and temperature (PVT). Moreover, the incongruent

Abstract— A drain-switching charge pump (CP) design is scaling of power supplies versus threshold voltages limits the
presented with near perfect current matching and extended flat operating ranges of many analog circuits, one of which is the
current response over a range of process, voltage, and charge pump.
temperature variations. Current mismatch is compensated In this paper, we describe a CP with simple dynamic
dynamically without the need for a replica charge pump or feedback compensation to provide excellent current flatness
extended digitally-assisted calibration routines. The self-
and matching over a wide range of operating conditions.
regulated circuit uses several simple yet effective feedback
mechanisms to overcome the basic shortcomings of nanometer
devices and reduced power supplies. The circuit is designed in II. CHARGE PUMP CIRCUITS FOR PLLS
90nm CMOS and simulated extensively using Monte Carlo Charge pump designs fall into two major architectures: drain-
analysis while sweeping the operating temperature to provide switched and source-switched. The difference lies in the
statistically relevant operating conditions. The proposed design
location of the switch with respect to the current carrying
achieves near perfect current matching at output voltages
between 0.16V and 0.98V for temperatures ranging from -30 to device. Fig. 1 shows a conventional drain-switching CP
90 degrees Celsius and a power supply between 1.08V and 1.32V. design. Switches SW1 and SW2, tied to the drains of the main
devices (P1/N1), are controlled by the digital output of the
Index Terms— Charge Pump, Frequency synthesizers, Phase Phase-Frequency Detector in the PLL. This control enables P1
locked loops to inject current into – or N1 to sink current from – the loop
filter thus changing the voltage stored on the filter (and the CP
I. INTRODUCTION output). Although a constant current is desired, nanometer
MOS current characteristics have a dependency on the drain
A charge pump (CP) circuit forms a critical block in many
analog Phase-Locked Loop (PLL) systems. It is
essentially used to transform an error signal that encodes
voltage. This results in slanted output currents, due to channel-
length modulation, as shown in Fig.1 (right). The current
temporal phase differences into a correction voltage through deviation gives rise to current mismatch that can be quite large
the charging and discharging of an oscillator’s voltage control
line. The feedback action of the PLL results in a regulated
output frequency with respect to a stable input reference
oscillation. The regulation, however, is prone to several non-
idealities that enter the loop from many of the PLL’s
constituent blocks and manifest as unwanted output noise.
Being highly analog in nature, the CP tends to be a major
source of disturbance to the overall loop, affecting both the
loop’s locking condition as well as its stability. Several CP
non-idealities come into play, such as charge sharing, charge Fig.1. Conventional drain-switching charge pump circuit and its current
injection, transient response, current deviation and current characteristics
mismatches. The latter two non-idealities’ effects are further
exacerbated with the use of complementary devices, i.e.
pMOS and nMOS, to provide the charging and discharging
currents. Unequal sourcing and sinking currents result in
increased reference spurs in integer-N PLLs and second-order
effects such as elevated close-in noise floor in fractional-N
PLLs [1]. Therefore, it is highly desirable to achieve matching
sourcing and sinking currents, IUP and IDN, respectively.
However, the continuous scaling of semiconductor devices
increases their susceptibility to variability with process, Fig.2. Current matching: forcing current equality through modulation [3]

978-1-4799-0066-4/13/$31.00 ©2013 IEEE 1100

at high or low operating voltages. Since the effect is
synonymous to a reduced output resistance, the classical
solution is to use long channel devices at the output; however
at the expense of loss of speed and increased area and
parasitics. Other techniques, such as gain-boosting [2] and
cascoding, have also been employed. The more critical aspect
though is current matching between the sourcing and sinking
paths to which several designs have been proposed. Instead of
flattening the current response, op-amps have been employed
to provide negative feedback compensation mainly to
modulate one of the currents to match the other. Fig. 2 shows
such an implementation [3] where the sinking current is forced
to follow the sourcing current’s output voltage dependence,
thereby reducing mismatch. Although current mismatch is
reduced, current deviation (non-flat response) is still present.
The same forcing technique can be compounded, i.e. with two
such loops, to create a flat characteristic as shown in [4] but
with significant added complexity and power.
Most CP current matching techniques rely on the presence of
replica CPs to quantify the mismatch and correct for it, either
through forced matching or injection of a correction current
[5]. The replica CPs are exact copies of the main output
branch (note that also in Fig. 2, the biasing branch is
essentially an always-on replica of the output branch.) As they
are not part of the normal operation, they can be used as
proxies to measure and then alter the main output currents.
Mismatch can still be present as what is being observed is
either the current in the biasing branch or in a replica output
stage; the real output currents are not measured. Some non-
replica techniques have been also devised where the main
output currents (or some observable directly related to them)
are measured, albeit at the expense of breaking open the PLL
[6] or performing one-time calibration [7] – both of which do
not dynamically track environmental changes.
Whereas all these techniques strive to match the currents,
little effort is done to sustain that matching over changing
operating conditions. The CP current characteristics are
affected not only by its output voltage but also process
mismatches and temperature fluctuations. The same also
applies for the performance of any added compensation
circuitry thus making current matching a difficult issue to
Fig. 3. Proposed Charge Pump: a) circuit and operating techniques of b) range extension and c) current flattening
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tackle. In the next section, we propose a CP designed in a
nanometer process with simple and effective techniques to
enhance its capabilities and provide it increased immunity to
PVT.
III. PROPOSED METHOD AND CIRCUIT
The proposed CP circuit is shown in Fig. 3a. It comprises a
current-steering drain-switching topology with a number of
modifications to enable an extended operating range, flexible
biasing to overcome PVT, and mismatch control to detect and
correct unequal sinking and sourcing currents. Two major
downsides to the conventional drain-switching topologies
(Fig. 1) are charge sharing and switch charge injection.
Current steering is a widely used modification to reduce the
first effect when the main switches are turned on and off. By
steering the unused current to a side-branch through
complimentarily driven switches, the voltages at the drains of
the current-supplying devices are not disrupted much and held
approximately constant. As for switch charge injection, half-
dummy switches or smaller switches are usually the most
commonly used approaches [8]. The major benefit of such a
topology is the inherent presence of a replica through the
steering branch. In other words, a free replica is created when
the main branch is not operational and the side branch is fully
turned on. This also has the added advantage of having the
actual, not copy, currents as observables – eliminating
concerns with main/replica, as well as main/bias, mismatches.
In the proposed implementation, the sourcing and sinking
devices P1/N1 have somewhat independent current controls
(N5-7/P2-4 and N2-4/P5-7, respectively) to enable a high
degree of flexibility in tuning them in order to match. Two
voltages, VnBias and VpBias, are supplied to the two branch bias
blocks. Using a combination of control knobs, the proposed
CP has the ability to extend the output operating range, reduce
the effects of channel length modulation, and force current
matching over PVT variations well beyond the original
capabilities of the nanometer devices. While the original
current characteristic of the main transistors remain
unchanged, composite modulation of the currents enable the
desirable flat and matched current profile, as described next.
 Fig. 4. Current mismatch control: a) input/output characteristics of mismatch control circuit; b) example curves for mismatched current correction at two
different CP output voltages; c) Simulation result of replica node voltage matching the output voltage
A. Operating range extension
As power supplies and threshold voltages are not scaling
proportionally, the output devices’ delay in entering their
saturation region reduces the operation range of the CP, where
its output currents can be of comparable magnitudes. To
extend the range, the output voltage VCPout is used to tune the
output currents by allowing it to increase the sinking (IDN) and
decrease the sourcing (IUP) current at low and high voltages,
respectively. A depiction of the effect is shown in Fig.3b: IDN
naturally exhibits ohmic-region characteristics at low output
voltages, but if the main bias voltage used to generate IDN is to
be modulated to increase the output current at low VCPout, an
extended saturation region can be obtained. Although still in
the linear region, the current supplied is boosted to result in a
composite response resembling a lower Vth device (IDNextended).
To achieve this effect on both output currents, VCPout (or
preferably its filtered equivalent, tapped along the subsequent
loop filter) is fed to two simple inverting circuits (N9/P8 and
N8/P9) that modify the biasing of VnBias and VpBias through N10
and P10, respectively. The inverting circuits are skewed to the
edges of the operating range: P10 increases VnBias at high CP
output voltage to boost IUP and, conversely, N10 decreases
VpBias at low CP output voltage to achieve the same for IDN.
B. Reduction of channel-length modulation
In a similar fashion, the characteristic curve is flattened by
modulating the output current along the output range such that
a constant current is supplied at each output voltage. This
time, the CP output is fed to two feedback transistors in the
branch biases, N4 and P4 [9]. This feedback, depicted in Fig.
3c, reduces IDN and IUP at low and high CP output voltages,
respectively, making them seem linear over a wide range of
output voltages without the use of long channel devices.
C. Current Matching
The two earlier feedback mechanisms affect each current
independently, working together to create an extended-range
flat response. However, they do not respond to matching
between the two nor do they account for the non-deterministic
PVT variations that compromise the matching. Here the
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current-steering enabled replica is used to detect the matching
quality. When the replica is established and both IUP and IDN
flow through it, its output (VCPoutrep) will settle to the voltage
where the two currents are equal. This voltage provides an
indication of where the two current cross over and are
identical. That cross-over voltage, along with the main output
voltage, constitute the inputs to a mismatch control circuit (in
grey in Fig.3). Instead of using op-amps, we propose a very
simple circuit acting as a modulated inverting buffer with
transfer characteristics as shown in Fig. 4a. The output of the
circuit, VCPctrl, controls variable resistances (N7 and P7) at the
sources of N5 and P5 in the branch biases, changing IDN and
IUP in opposite directions, reducing one while increasing the
other. The eventual effect of this feedback circuit is to ensure
that VCPoutrep, i.e. the cross-over voltage, is identical to the
actual output voltage of the CP, meaning the currents are equal
at that voltage. Fig. 4b shows a simplified progression of the
self-calibration for two example values of VCPout, at and below
mid-range. A large mismatch can exist at the output voltage;
however, the feedback reaction of the circuit strives to reduce
that mismatch. The proposed mismatch control circuit enables
as close to rail-to-rail matching as possible, allowing current
matching for a wide range of output voltages. Fig. 4c shows
how the replica output voltage follows the actual output
voltage for most of the usable range, ensuring the output
currents are identical at all these voltages.
IV. SIMULATION RESULTS
The circuit is designed and extensively simulated in 90nm
CMOS technology at a 1.2V power supply. For comparison, a
conventional CP is also designed. Time domain simulations
are performed with realistic UP and DN pulses. Measurements
of the current flowing out of the CP are taken at different
output voltages in order to build the current profile of the
sourcing and sinking currents along the range.
The output currents of both the conventional and proposed
CP are shown in Fig. 5. As expected the conventional CP
exhibits a strong channel-length modulation effect and its
output currents can be quite mismatched across most of the
operating range – averaging 8% across the 0.3-0.9V range. In
 Fig. 5. Current characteristics and mismatches of the conventional versus
proposed CP (w/o mismatch reduction)
contrast, the proposed CP with its dynamic adjustments shows
a flat response and extended operating range – averaging
<0.5% across 0.3-0.9V. Also, to qualify the effectiveness of
the current mismatch control circuitry, mismatch currents are
injected into the circuit on both its sourcing and sinking
currents. Fig. 6 shows the mismatch reduction capability of the
proposed CP with its mismatch control circuit enabled
compared to the uncorrected currents (mismatch control can
be disabled by connecting N7 and P7 to mid-rail). The
feedback mechanism succeeds in bringing disparate current
curves closer together therefore reducing their mismatch, as
seen in Fig. 6. For non-typical process corners and
temperatures, the current mismatch can become quite
significant. The matching results observed in Fig. 6 also hold
true for wide temperature (-30 to +90ºC), process/mismatch
(±3σ), and supply voltage (90% to 100% Vdd) variations. The
CP is subjected to Monte Carlo analysis to quantify its
capabilities and qualify its proper operation. Fig. 7 shows the
mismatch distribution of both simulated CPs at room
temperature (30°C). The proposed CP has a tight distribution
and very low mismatch across the output range (~0.5%) as
compared to the conventional CP showing a wider distribution
hovering around 8%. Several hundred runs are performed
under varying temperature settings and a ±10% variation in
power supply voltage. The results are depicted in Fig. 8. The
average mismatch has been greatly reduced with the addition
of the simple tuning knobs and mismatch control circuit from
>8% on average to <1.5%, across temperature.
V. CONCLUSION
In this paper we present a charge pump design with dynamic
current-mismatch reduction capabilities and increased
Fig. 7. Monte Carlo statistical simulation results for CP mismatch percentage
(200 simulation runs, 30 degrees temperature, and 1.2V supply)
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Fig. 6. Proposed CP current characteristics under forced mismatch with and
without its current mismatch control circuits enabled
immunity to random variations in process, temperature, and
supply voltage. The circuit is designed in 90nm CMOS and
verified in simulation using Monte Carlo analysis.
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Fig. 8. Mean and distribution of CP mismatch percentage with temperature