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Logic Gates

Logic Gates
 Basic Building Blocks

 Logic Gate Symbol

 Unique Function
 Two ways to express

 Truth or Function Table


 Function Expression

 Timing Diagram
 Performance for a certain period of time
Three Basic Gates

1. AND Gate

2. OR Gate

3. NOT Gate
AND Gate
 1 output

 2 inputs
 3 inputs
 4 inputs 0 &
 Multiple inputs 0
0
AND Gate function

 Logical Multiplication function

Input Output
F  A B
A B F
0 0 0 F  A  B  C  ....  N
0 1 0
1 0 0
1 1 1

Truth table/ Function Table explaining the operation of the AND gate
AND Gate function

 What if we have four inputs of an AND gate?


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AND Gate Timing Diagram

 A timing diagram is a graph of the output of a logic


gate with respect to the inputs of the gate.

 A timing diagram plots voltage (vertical) with


respect to time (horizontal).

 A timing can also be seen as waveforms on an


oscilloscope or on a logic analyzer.
AND Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
OR Gate

 1 output

 2 inputs
 3 inputs
 4 inputs
>=1
 Multiple inputs
0
0
0
OR Gate function

 Boolean Add function

Input Output F  A B
A B F
0 0 0
0 1 1
F  A  B  C  ..  N
1 0 1
1 1 1
OR Gate function

 What if we have four inputs of an OR gate?


OR Gate function
OR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

Time intervals
Two Questions

 Why AND gate is called AND gate ?

 Why OR gate is called OR gate?

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Why AND gate is called AND gate ?
 The AND gate is so named because, if 0 is called
"false" and 1 is called "true," the gate acts in the
same way as the logical "and" operator.

 The output is "true" when both inputs are "true."


Otherwise, the output is "false."

 In other words, the output is 1 only when both


inputs one AND two are 1.

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Why OR gate is called OR gate ?
 The OR gate gets its name from the fact that it
behaves after the fashion of the logical inclusive "or."

 The output is "true" if either or both of the inputs are


"true." If both inputs are "false," then the output is
"false."

 In other words, for the output to be 1, at least input


one OR two must be 1

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INVERTER / NOT Gate

 1 input
 1 output
NOT Gate function

 Invert function

Input Output
A F
0 1
1 0

FA
NOT Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
Use of Logic Gates
 There are many important uses of Logic Gates.

 All modern electronic devices use logic gates as their basic


component. Most of the useful works behind an electronic
device performed by logic gates.

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Applications of Logic Gates
 The important applications of Logic Gates in Digital
Electronics are Flip-Flop circuit, register, digital counter,
Microprocessor, Microcontroller, etc.

 Flip Flop
 Memory Element
 A flip flop is an electronic circuit with two stable states that
can be used to store binary data. The stored data can be
changed by applying varying inputs. Flip-flops and latches
are fundamental building blocks of digital electronics
systems used in computers, communications, and many
other types of system

 Register
 A Register is a collection of flip flops. A flip flop is used to
store single bit digital data. For storing a large number of
bits, the storage capacity is increased by grouping more
than one flip flops

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Applications of Logic Gates
 Counter
 It is a sequential circuit.
 A digital circuit which is used for a counting
pulses is known counter.
 Counter is the widest application of flip-flops.
It is a group of flip-flops with a clock signal
applied.
 Counters are used not only for counting
but also for measuring frequency and
time ; increment memory addresses
 Counters are well known to us as “Timers”.
Counter circuits are the best example for the
flip flop applications.
 Counters are designed by grouping of flip
flops and applying a single clock signal to
them

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Use of AND Gate

 The AND gate is used


• for data transmission control in digital electronics.
• in digital measuring instruments.
• in alarm circuits.

 AND gate allows or disallows the transmission of


data through a channel.

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Use of AND Gate
 AND gate is Used to enable/Disable a Device
 How does a Counter counts ?
 Counter counts when it receives pulses  Up/down (U/D) input
• It controls the direction of the count. These counters count
up when U/D is high and count down when U/D is low
 Enable pin
Clock Pulses U/D
Counter

B1
• The counter circuit will receive the clock inputs only if this
pin is set to HIGH.
 Reset :
• It resets and starts again.
A
Reset B8
• This is the reset pin of counter 1 which should be LOW for
normal operation of the counter and HIGH if you want to
Carry out reset the output of counter 1 to zero. Reset pin acts as
switch
B ENB
 Carry-out and a carry-in pin
• Synchronous counters usually have a carry-out and a
Disable carry-in pin for linking counters together without introducing

Enable any propagation delays.

 Clock Pulse –A of AND Gate


 Switch –B of AND Gate
 Counter increments as it receives a clock pulse
Use of AND Gate

 Enable and disable in logic gates?


 AND and OR gates can both be used to enable or
disable a transmitted waveform.
 For a two input AND gate, one input is the signal (clock
pulse here ) and the other input is the enable pulse
(switch here).
 The enable of an AND gate is high active.
 That is, when the enable is high the input signal will
appear on the output.

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Use of OR Gate
 Car door open alarm

 Let us have a circuit which generates 5V (corresponding to Logic 1) when any door is opened.
 If all doors closed. All four circuits will generate 0V (Corresponding to Logic 0)

Front left door


Rear left door
Alarm
Front right door
Rear right door
Use of NOT Gate
 1’s Complement

1 1 0 0 1 0 1 0

0 0 1 1 0 1 0 1

 Note:
 We have studied calculating of 2s Complement of a number and the pre requisite is 1’s Complement
Alternative Logic Gates-
 Alternative logic gate is an alternate logic gate that produces
the same output as the original logic gate and can be used
during the unavailability of the original logic gate to serve
the same purpose.

 Alternative logic gates are also called as Alternate Gates.

 Alternative logic gates are also called as Bubbled Gates since


they contain bubbles in them
Rules To Memorize Alternative Logic Gates-
 For AND, NAND, OR & NOR Gates-
 Both the inputs of alternative gate will have bubbles (which

represents NOT gate).


 For AND structured original gate, alternative gate will be

OR structured.
 For OR structured original gate, alternative gate will be

AND structured.
 If bubble is present at the output of original gate, then no

bubble will be present at the output of alternative gate.


 If bubble is not present at the output of original gate, then a

bubble will be present at the output of alternative gate

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NAND Gate and NAND gate as Universal
Gate
NAND Gate
 1 output

 2 inputs
 3 inputs
 4 inputs
 Multiple inputs
NAND Gate function

 NOT-AND function

Input Output
A B F F  A B
0 0 1 F  A  B  C  ....  N
0 1 1
1 0 1
1 1 0
NAND Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6

F
Universal Gate – NAND
 How a NAND gate can be used to replace
 an AND gate
 an OR gate
 or an INVERTER gate ?
 How a logic circuit implemented with AOI (AND-OR-invert ) logic
gates can be re-implemented using only NAND gates.
 That using a single gate type, in this case NAND, will reduce
the number of integrated circuits (IC) required to implement a
logic circuit.
AOI Logic NAND Logic

More ICs = More $$ Less ICs = Less $$ 36


NAND Gate

X
Z XYXY
Y

X Y Z
0 0 1
0 1 1
1 0 1 • Overview of basic NAND gate :
1 1 0 Logic Symbol, Logic Expression
(using DeMorgan’s) and Truth
Table.
• Bubble is an inverter..
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1. NAND Gate as Inverter Gate

X  X  X (Before Bubble)

X ZX

X Z
0 1
Equivalent to Inverter
1 0

When we tie the inputs on a NAND gate


together, the output will be the complement
of the input.

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2. NAND Gates as AND Gate

XY
X
Z XYXY
Y

NAND Gate Inverter

• NAND gate is an
AND gate with the
output inverted.
• If we invert the X Y Z
output again, we 0 0 0
will get an AND 0 1 0
gate. Equivalent to AND Gate
• Note that we are 1 0 0
using a NAND gate 1 1 1
for the inverter.
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2. NAND Gates as AND Gate

Input Output Output


A B F1 F
0 0 1 0
0 1 1 0
1 2
1 0 1 0
1 1 0 1
3. NAND Gates as OR Gate

X Y
Z XY XY  XY
Y

Inverters NAND Gate

• If we invert both of the X Y Z


inputs of a NAND gate,
we will get an OR gate. 0 0 0
• Note that we’re using 0 1 1
NAND gates as Equivalent to OR Gate
1 0 1
inverters.
1 1 1

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3. NAND Gates as OR Gate

Input Output
A B F
0 0 0
0 1 1 1
1 0 1 3
2
1 1 1
Summary_ NAND Gates Equivalent to AOI
Gates

AND OR INVERTER

Summary of the three AOI gates and their NAND equivalent. 43


NOR Gate and NOR Universal Gate
NOR Gate

 1 output

 2 inputs
 3 inputs
 4 inputs
 Multiple inputs
NOR Gate function

 NOT-OR function

Input Output
A B F
F  A  B
0 0 1 F  A  B  C  ....  N
0 1 0
1 0 0
1 1 0
NOR Gate function

 What if we have three input NOR gate ?


NOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
Universal Gates

Universal logic gates are the logic gates that are


capable of implementing any Boolean function
without requiring any other type of gate.

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Universal Gate – NOR
 How an NOR gate can be using to replace an
 AND gate
 OR gate
 INVERTER gate ?
 How a logic circuit implemented with AOI logic gates could be
re-implemented using only NOR gates ?
 That using a single gate type, in this case NOR, will reduce the
number of integrated circuits (IC) required to implement a logic
AOI Logic NOR Logic
circuit.

More ICs = More $$ Less ICs = Less $$

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NOR Gate

X
ZXYX Y
Y

X Y Z
0 0 1
0 1 0
1 0 0
1 1 0

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1. NOR Gate as an Inverter Gate

X  X  X (Before Bubble)

X ZX

X Z
0 1
Equivalent to Inverter
1 0

When you tie the inputs on a NOR gate


together, the output will be the complement
of the input.

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2. NOR Gates as OR Gate

XY
X
Z XY XY
Y

NOR Gate “Inverter”

• This one is easy to see, a


NOR gate is in NOR gate X Y Z
with the output inverted.
• So if we invert the output 0 0 0
again we will get an OR 0 1 1
Equivalent to OR Gate
gate. 1 0 1
• Note we’re using a NOR
gate for the inverter. 1 1 1

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3. NOR Gates as AND Gate

X Y
ZXYXYXY
Y

“Inverters” NOR Gate

This one is a bit harder to X Y Z


see. If you invert both the 0 0 0
inputs of a NOR gate you will
get an AND gate. Note 0 1 0
Equivalent to AND Gate
we’re using NOR gates as 1 0 0
inverters. 1 1 1

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Summary_ NOR Gate Equivalent of AOI Gates

AND OR INVERTER

Summary of the three AOI gates and their NOR equivalent.

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Note: NAND-NOR Universal Gate
• How to Use a combination of NOR gates to implement NAND gate
• How to Use a combination of NAND gates to implement NOR gate

1 1
3 4 3 4
2 2
NAND Gates and NOR Gates are two Universal
Gates.
Types of Logic Gates

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Use of NAND Gate
 Device Failure Alarm
• Toxic fumes produced by the chemicals are removed from the
ware house and dispersed in the atmosphere through three
exhaust fans.
• When all fans are working the input to the NAND gate is 111 and
the output is 0 (Interface circuit generates a 1).
• When any one fan fails the output of NAND gate becomes 1
sounding an alarm connected tot the output of the NAND gate

ALARM
Use of NOR Gate
• Washing Machine Controller
 Three sensors check for
washing machine lid open,
washing tub filled to minimum
level and weight of cloths and
water in the tub.
 If the lid is open or the water is

below the minimum level or the


washing machine has been
overloaded the appropriate
sensor sets its output to 1.
 The NOR gate output is set to 0

switching off the washing Switch

machine.
Two More Gates
XOR Gate
XNOR Gate

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XOR Gate
 1 output

 2 inputs

 Multiple inputs

 Note: It is a combination of other gates


XOR Gate function

Input Output
F  A  B
A B F
0 0 0
0 1 1
1 0 1
1 1 0
XOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
XNOR Gate

 1 output

 2 inputs

 Multiple inputs
XNOR Gate function

Input Output
A B F F  A  B
0 0 1
0 1 0
1 0 0
1 1 1
XNOR Gate Timing Diagram

t0 t1 t2 t3 t4 t5 t6
Use of XOR Gate

• Detecting odd number of 1’s in Parity Check


• Consider the three XOR gate logic circuit which is used
to detect odd number of 1’s in a 4-bit binary input
combination
• Consider the 4-bit binary number 0000 applied at
the inputs A, B, C and D respectively of XOR gates 1
and 2.
• The output of XOR Gates 1 and 2 is 0 and 0. The
output of XOR gate 3 is also zero.
• Consider the binary number 0011 applied at the
inputs A, B, C and D respectively. A
• The output of XOR gate 1 with inputs 00 is 0. The
B 1
output of XOR gate 2 with inputs 11 is 0. The
output of gate 3 is 0. Thus the output indicates that
the binary number 0011 does not have odd number 3
C
of 1’s
• Consider the binary number 1011 applied at the D 2
inputs A, B, C and D respectively.
• The output of XOR gate 1 with inputs 10 is 1. The
output of XOR gate 2 with inputs 11 is 0. The
output of gate 3 is 1. Thus the output indicates that
the binary number 1011 has odd number of 1’s
Use of XNOR Gate

• Detecting even number of 1’s in Parity


Check
• Consider the two XOR and a single XNOR gate based logic circuit
used to detect even number of 1’s in a 4-bit binary input combination
• Consider the 4-bit binary number 0000 applied at the inputs A, B,
C and D respectively of XOR gates 1 and 2.
• The output of XOR Gates 1 and 2 is 0 and 0. The output of XNOR gate 3
is a 1.
• Consider the binary number 0011 applied at the inputs A, B, C
and D respectively.
• The output of XOR gate 1 with inputs 00 is 1. The output of XOR gate 2
with inputs 11 is 1. The output of XNOR gate 3 is also a 1. Thus the A
output indicates that the binary number 0011 has even number of 1’s B 1
• Consider the binary number 1011 applied at the inputs A, B, C
and D respectively. 3
C
• The output of XOR gate 1 with inputs 10 is 1. The output of XOR gate 2 2
D
with inputs 11 is 0. The output of XNOR gate 3 is 0 because of dissimilar
inputs. Thus the output indicates that the binary number 1011 does not
have even number of 1’s
Rules To Memorize Alternative Logic Gates-

 For X-OR & X-NOR Gates-


 One of the inputs of alternative gate will have a bubble
(which represents NOT gate).
 For X-OR structured original gate, alternative gate will be X-
NOR structured.
 For X-NOR structured original gate, alternative gate will be X-
OR structured.
 If bubble is present at the output of original gate, then no
bubble will be present at the output of alternative gate.
 If bubble is not present at the output of original gate, then a
bubble will be present at the output of alternative gate

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Thanks

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