Department of ECE

ASIC & FPGA CHIP DESIGN

20EC3063
Topic:

VERILOG PROGRAMMING

Session - 9

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION

To familiarize students with the basic concept of Verilog programming

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Demonstrate the types of Verilog programming
2. Describe behavioral and data flow level programming

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define the various blocks in Verilog programming
2. Summarize the behavioral and data flow level Verilog programming for various logic design

CREATED BY K. VICTOR BABU

 SESSION INTRODUCTION

• Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a

digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by using
a HDL we can describe any digital hardware at any level.

• Designs, which are described in HDL are independent of technology, very easy for designing and
debugging, and are normally more useful than schematics, particularly for large circuits.

Verilog supports a design at many levels of abstraction. The major three are −

1. Behavioral level

2. Register-transfer level

3. Gate level

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION

// Define the sequential block

module simple (Clock, Resetn, w, z); always @(negedge Resetn, posedge Clock)
input Clock, Resetn, w; if (Resetn = = 0) y <= A;
output z; else y <= Y;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10; // Define output
assign z = (y = = C);
// Define the next state combinational circuit
always @(w, y) endmodule
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION (Cont..)

Verilog code for a one-digit BCD adder.

module bcdadd (Cin, X, Y, S, Cout);
input Cin;
input [3:0] X, Y;
output [3:0] S;
output Cout;
reg [3:0] S;
reg Cout;
reg [4:0] Z;
always@ (X or Y or Cin)
begin
Z = X + Y + Cin;
if (Z < 10)
{Cout, S} = Z;
else
{Cout, S} = Z + 6;
end
endmodule

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION (Cont..)
case (y)
Verilog for the Serial Adder G: begin
s = QA[0] ^ QB[0];
module serial_adder (A, B, Reset, Clock, Sum); if (QA[0] & QB[0]) Y = H;
input [7:0] A, B; else Y = G;
input Reset, Clock; end
output wire [7:0] Sum; H: begin
reg [3:0] Count; s = QA[0] ~^ QB[0];
reg s, y, Y; if (~QA[0] & ~QB[0]) Y = G;
wire [7:0] QA, QB; else Y = H;
wire Run; end
parameter G = 1’b0, H = 1’b1; default: Y = G;
shiftrne shift_A (A, Reset, 1’b1, 1’b0, Clock, QA); endcase
shiftrne shift_B (B, Reset, 1’b1, 1’b0, Clock, QB); // Sequential block
shiftrne shift_Sum (8’b0, Reset, Run, s, Clock, Sum); always @(posedge Clock)
// Adder FSM if (Reset) y <= G;
// Output and next state combinational circuit else y <= Y;
always @(QA, QB, y) // Control the shifting process
always @(posedge Clock)
if (Reset) Count = 8;
else if (Run) Count = Count - 1;
assign Run = |Count;
CREATED BY K. VICTOR BABU
 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION

CREATED BY K. VICTOR BABU

 EXAMPLES

Code for a left-to-right shift register with an enable input

module shiftrne (R, L, E, w, Clock, Q);
parameter n = 8;
input [n-1:0] R;
input L, E, w, Clock;
output reg [n-1:0] Q;
integer k;
always @(posedge Clock)
if (L)
Q <= R;
else if (E)
begin
for (k = n-1; k > 0; k = k-1)
Q[k-1] <= Q[k];
Q[n-1] <= w;
end
endmodule

CREATED BY K. VICTOR BABU

 SUMMARY

• A number of facilities in Verilog relate to the management of simulation; starting and stopping of
simulation, selectively monitoring the activities, testing the design for timing constraints, etc., are
amongst them. Although a variety of such constructs is available in Verilog.

• Most of the behavioral modeling is done using two important constructs: initial and always. All the other
behavioral statements appear only inside these two structured procedure constructs. Switch level
modeling forms the basic level of modeling digital circuits.

• The switches are available as primitives in Verilog; they are central to design description at this level.
Basic gates can be defined in terms of such switches. By repeated and successive instantiation of such
switches, more involved circuits can be modeled – on the same lines as was done with the gate level
primitives.

CREATED BY K. VICTOR BABU

 SELF-ASSESSMENT QUESTIONS

… To suspend a simulation, what system command can be used in Verilog programming?

(a) … $finish

(b) … $stop

(c) … $end

(d) … $close

2. …. The phenomenon of clock skew is found in ______

(a) … Asynchronous circuit

(b) … All
(c) … Synchronous circuit
(d) … Neither

CREATED BY K. VICTOR BABU

 TERMINAL QUESTIONS

1. Summarize the initial and always blocks in Verilog

2. Differentiate the blocking and non-blocking assignment statements in Verilog
3. Write the Verilog code for full adder using always block

CREATED BY K. VICTOR BABU

 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. 1. Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8.
2. Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill.
3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”,
Pearson Education – 2009
Sites and Web links:
1. https://archive.nptel.ac.in/courses/108/104/108104091/
2. http://www.referencedesigner.com/tutorials/verilog/verilog_01.php

CREATED BY K. VICTOR BABU

 THANK YOU

Team – ASIC & FPGA

CREATED BY K. VICTOR BABU