Department of ECE

ASIC & FPGA CHIP DESIGN

20EC3063
Topic:

DESIGN PROCEDURE

Session - 8

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION

To familiarize students with the basic concept of the various design procedure for the digital logic circuits

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Demonstrate the design steps for any applications with logic circuits
2. Describe ASM chart for designing the circuit

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Describe ASM chart
2. Summarize the various design procedure for the digital logic circuits

CREATED BY K. VICTOR BABU

 SESSION INTRODUCTION

• An Algorithmic State Machine (ASM) diagram offers several advantages over conventional state
diagrams. For larger state diagrams, ASM diagrams are easier to interpret. Conditions for a proper state
diagram are automatically satisfied. ASM diagrams are easily converted to other forms.

• It is a special type of flow chart that is used to describe the sequential operations of a digital circuit. The
ASM chart determines the sequence of events, timing relationship between the states of sequential
controller and the events that happen while going from one state to another.

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION

Design methodology using ASM chart

ASM Chart Elements

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION (Cont..)

ASM Chart for the Simple Moore Machine

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 SESSION DESCRIPTION (Cont..)

ASM Chart for the Simple Mealy Machine

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 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION

CREATED BY K. VICTOR BABU

 EXAMPLES

Reaction-timer Circuit
ASM Chart for the Reaction Timer
CREATED BY K. VICTOR BABU
 SUMMARY

• Operation of a digital system can be easily understood by inspection of the SM chart. ASM charts
represent physical hardware. The ASM chart are equivalent to a state graph, and it leads directly to a
hardware realization.

• ASM charts can be described the operation of both combinational and sequential circuits. ASM charts
are easier to understand and can be converted several equivalent forms. The ASM chart may be
equivalently expressed as a state and output table.

CREATED BY K. VICTOR BABU

 SELF-ASSESSMENT QUESTIONS

1. … The timing for all flip-flops in the digital system is controlled by

(a) … Memory

(b) … Latches

(c) … Master clock Generator

(d) … Flip-flop

2. In designing ASM with multiplexers, the registers hold

(a) … Present binary state

(b) … input
(c) … next binary state
(d) … output

CREATED BY K. VICTOR BABU

 TERMINAL QUESTIONS

1. Summarize the principle components of the ASM chart.

2. Draw the ASM chart for the combinational network Z = A(B+C).
3. List out the steps involved in conversion of state diagram to an ASM chart.

CREATED BY K. VICTOR BABU

 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. 1. Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8.
2. Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill.
3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”,
Pearson Education – 2009
Sites and Web links:
1. https://archive.nptel.ac.in/courses/108/104/108104091/
2. https://www.youtube.com/watch?v=mHvV_Tv8HDQ

CREATED BY K. VICTOR BABU

 THANK YOU

Team – Course Name

CREATED BY K. VICTOR BABU