Department of ECE

ASIC & FPGA CHIP DESIGN

20EC3063
Topic:

FLIP FLOP EXCITATION TABLE

Session - 7

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION

To familiarize students with the basic concept of flip flop excitation table

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Demonstrate how to form the excitation table
2. Describe the various types of flipflop excitation table

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define excitation tables in digital logic circuits
2. Summarize the steps to form the flip flop excitation table

CREATED BY K. VICTOR BABU

 SESSION INTRODUCTION

• In electronics design, an excitation table shows the minimum inputs that are necessary to generate a
particular next state (in other words, to “excite” it to the next state) when the current state is known.

• The excitation tables are used to determine the inputs of the flip-flop when the present state and the
next state to which the flip-flop goes after the occurrence of the clock pulse are known

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION

K-maps for the Counter with J-K Flip-flops

Implementation using J -K Flip Flop
Circuit Diagram for the Counter
1. If FF in state 0 to remain 0, J=0 and K=d.
2. If FF in state 0 to change to 1, J=1 and K=d.
3. If FF in state 1 to remain 1, J=d and K=0.
4. If FF in state 1 to change to 0, J=d and K=1.

CREATED BY K. VICTOR BABU

Excitation Table for the Counter with J-K Flip-flops
 SESSION DESCRIPTION (Cont..)

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION (Cont..)

Circuit Diagram for the Counter with J-K Flip-flops

CREATED BY K. VICTOR BABU

 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION

CREATED BY K. VICTOR BABU

 EXAMPLES

Circuit Diagram for the Counter

CREATED BY K. VICTOR BABU
 SUMMARY

The excitation tables are used to determine the inputs of the flip-flop when the present state and the next
state to which the flip-flop goes after the occurrence of the clock pulse are known. The flip flop must be
excited or triggered by the JK Flip-Flop excitation table to move from its current state to the next one.

CREATED BY K. VICTOR BABU

 SELF-ASSESSMENT QUESTIONS

1. …The functional difference between an S-R flip flop and J-K flip flop is that

(a) …JK flip flop is faster than SR flip flop

(b) …JK flip flop accepts both inputs as 1

(c) …JK flip flop has a feedback path

(d) JK flipflop does not require external clock

2. …A ring counter with 5 flip-flops will have.

(a) …5 states
(b) …32 states
(c) …10 states
(d) …infinite

CREATED BY K. VICTOR BABU

 TERMINAL QUESTIONS

1. List out List out the Counting sequence of the following counter.

2. Describe the steps to form D flip-flop from a J-K flip-flop

3. Summarize the use of PRESET and CLEAR in J-K flip flop

CREATED BY K. VICTOR BABU

 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. 1. Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8.
2. Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill.
3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”,
Pearson Education – 2009
Sites and Web links:
1. https://archive.nptel.ac.in/courses/108/104/108104091/
2. https://www.youtube.com/watch?v=mHvV_Tv8HDQ

CREATED BY K. VICTOR BABU

 THANK YOU

Team – ASIC & FPGA

CREATED BY K. VICTOR BABU