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Flip-Flop timing diagrams Exercices

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 Exercices-Digital Systems-Flip-Flop-2021-2022- Pr. S. BELATTAR

Flip-Flop timing diagrams

Exercices
1) From the inputs, complete the following timing diagrams:
a) of a RS flip-flop
b) of a RSH flip-flop (with clock)
a) b)

Solution

RS Flip-Flop RSH Flip-Flop

2) Complete the timing diagram of the following RS flip-flops:

Solution

Timing diagram of RS flip-flops

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 Exercices-Digital Systems-Flip-Flop-2021-2022- Pr. S. BELATTAR
3) Complete the timing diagram of the Q output of the RSH Flip-Flop

Solution

Timing diagram of RSH Flip-Flop

4) Comparison of different D Flip-Flop

Solution
4) Comparison of different D Flip-Flop in the following cases:
HIGH, LOW, Rising edge and Falling edge Flip-Flop.

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 Exercices-Digital Systems-Flip-Flop-2021-2022- Pr. S. BELATTAR
5) JK Flip-Flop
a) Recall the truth table of a JK flip-flop

Solution
Truth table of a JK flip-flop

b) Establish the logical equation of Q+.

Solution
Equation of Q+,
Truth and Karnaugh tables,

Logical equation of Q+.

c) Complete the following timing diagram:

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 Exercices-Digital Systems-Flip-Flop-2021-2022- Pr. S. BELATTAR
Solution
Timing diagram

d) Compare the switching frequency of Q+ with that of the clock in the case where J = K = 1

Solution
The switching frequency of Q+ when J = K = 1 is half that of the clock

Frequency Q+ = FClock/2

6) Complete the timing diagram of the following D flip-flop:

Solution
Timing diagram of D flip-flop

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 Exercices-Digital Systems-Flip-Flop-2021-2022- Pr. S. BELATTAR

7) Complete the chronogram of the following JK flip-flop synchronized on a positive

(rising) edge:

Solution
Chronogram of JK flip-flop synchronized on a positive

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