1.

Sketch the architecture of CPLD and list its major blocks and design a macro cell for given
Boolean equation Y = AB’+BC+AC+AB’C+A’B’C.
2. Construct Macrocell for Y (A,B,C)= ∑m(1,2,3,6,7) SOP logic. Explain registered and non-registered
output operation.
3. Describe the operation of AMD Mach5 CPLD architecture with neat diagram?
4. Draw and explain the working principle of SRAM-based crosspoint switch matrix.
5. With the help of block diagram explain cypress FLASH 370 device technology?