Department of ECE

ASIC & FPGA CHIP DESIGN

20EC3063
Topic:

STATE ASSIGNMENT

Session - 6

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION

To familiarize students with the basic concept of assigning states

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Demonstrate state assignments
2. Describe the various steps to assigning the states

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define various states for serial adder
2. Describe state assignments in serial adder

CREATED BY K. VICTOR BABU

 SESSION INTRODUCTION

State assignment rules are as follows:

Rule 1: States having the same next state for a given input condition should have assignments that can be
grouped into logically adjacent cells in a K-map.

Rule 2: States that are the next states of a single state should have assignments that can be grouped into
logically adjacent cells in a K-map.

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION

Block Diagram for a Serial Adder

State Diagram for a Serial Adder

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 SESSION DESCRIPTION (Cont..)

State Table for a Serial Adder

State-assigned Table for a Serial Adder Circuit for the Adder FSM

CREATED BY K. VICTOR BABU

 SESSION DESCRIPTION (Cont..)
State Diagram for a Moore-type Serial Adder
State Table for a Moore-type Serial Adder

State-assigned Table for a Moore-type Serial Adder

CREATED BY K. VICTOR BABU

 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION

CREATED BY K. VICTOR BABU

 EXAMPLES

Circuit for a Moore-type Serial Adder

CREATED BY K. VICTOR BABU

 SUMMARY

The state-assignment problem of finite-state machines (FSMs) is addressed. State assignment is a mapping
from the set of states (symbolic names) of an FSM to the set of binary codes with the objective of
minimising the area of the combinational circuit required to realise the FSM.

CREATED BY K. VICTOR BABU

 SELF-ASSESSMENT QUESTIONS

1. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features
is called as?

(a) …Tristate

(b) …End around

(c) …Universal

(d) …Conversion

2. …. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift
register with an initial state 01110. After three clock pulses, the register contains ________

(a) …01110
(b) …00001
(c) …00101
(d) …00110

CREATED BY K. VICTOR BABU

 TERMINAL QUESTIONS

A sequential circuit with two D Flip-Flops, A and B; two inputs, x and y; and one

output, z, is specified by the following next-state and output equations:

A(t+1) = x′y + xA
B(t+1) = x′B + xA
z=B
1) Draw the logic diagram of the circuit.
2) List the state table for the sequential circuit.
3) Draw the corresponding state diagram.

CREATED BY K. VICTOR BABU

 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Reference Books:
1. 1. Bob Zeidman, “Designing with FPGAs and CPLDs”, CMP Books, ISBN: 1-57820-112-8.
2. Stephen Brown and Zvonko Vranesic “Fundamentals of Digital Logic with Verilog Design”
McGraw-Hill.
3. Pak K. Chan, Samiha Mourad, “Digital Design Using Field Programmable Gate Array”,
Pearson Education – 2009
Sites and Web links:
1. https://youtu.be/YgtJlUXdCjI

CREATED BY K. VICTOR BABU

 THANK YOU

Team – ASIC & FPGA CHIP DESIGN

CREATED BY K. VICTOR BABU