• The various functional units are as follows:

• Bus unit
• Paging unit
• Control ROM
• Prefetch buffer
• Execution unit with two integer pipeline (U-pipe and V-pipe)
• Code cache
• Data cache
• Instruction decode
• Branch target buffer
• Dual processing logic
• Advanced programmable interrupt controller
• The Pentium processors have a data bus of 64 bits.
• This is a 32 bit CPU due to having 32 bits registers.
• A standard Single Transfer Cycle can read or write up
to 64 bits at a time (8 bytes)
• Burst read and burst write-back cycles are
supported by the Pentium processors.
• Burst Mode cycles are used for Cache operations
and transfer 32 bytes in 4 clocks
(4 * 8 bytes = 4 * 64 bits =256 bits).
• 32 bytes is the size of the Pentium Cache line.
• For the Pentium, all cache operations are burst
cycles.
• Pentium Architecture

• It has data bus of bit 64 bit and address bus of

32 bit
• There are two separate 8 KB caches one for
code and one for data.
• Each cache has a separate address translation
TLB which translate linear address to physical.
• Code cache
• It is an 8 KB cache dedicated to supply
instructions to processor’s execution pipeline.
• 2 way set associative cache with a line size of
32 bytes
• Prefetch Buffers:
• Four prefetch buffers within the processor
works as two independent pairs.
• When instructions are prefetched from cache,
they are placed into one set of prefetch buffers.
• The other set is used as when a branch
operation is predicted.
• Prefetch buffer sends a pair of instructions to
instruction decoder
• Instruction Decode Unit:
• It occurs in two stages – Decode1 (D1) and
Decode2(D2)
• D1 checks whether instructions can be paired
• D2 calculates the address of memory resident
operands
• Control Unit :
• This unit interprets the instruction word and
microcode entry point fed to it by Instruction
Decode Unit
• It handles exceptions, breakpoints and
interrupts.
• It controls the integer pipelines and floating
point sequences
• Microcode ROM :
• Stores microcode sequences
• Arithmetic/Logic Units (ALUs) :
• There are two parallel integer instruction
pipelines: u- pipeline and v-pipeline
• The u-pipeline has a barrel shifter
• The two ALUs perform the arithmetic and
logical operations specified by their
instructions in their respective pipeline
 Integer Pipeline Stages
• 1)Prefetch (PF)
• 2)Decode1 (D1)
• 3)Deccode2 (D2)
• 4)Execute (EX)
• 5)Write Back (WB)
• Floating Point Pipeline
Branch Prediction Logic
• Cache Organization of
Pentium
• 1. Page/Block Size = 2 KB
• 2. Main Memory Size = 16 KB
• 3. Cache Size = 8 KB
• 4. Number of Lines in Cache = ( Cache Size ) / ( Page Size ) = 4
• 5. Number of Blocks in Main Memory = ( Main Memory Size ) / ( Page Size ) = 8
• The data and instruction caches on
the Pentium processor are each 8 KB,
two-way associative designs with 32
byte lines.
• Each cache has a dedicated
translation lookaside Buffer (TLB) to
translate linear addresses to physical
addresses.
• Code cache
• Total Size of cache = 8 KB
• Size of each way = 4 KB
• Cache line size = 32 bytes (8K/256)
• Total number of lines in one way = 128
(Total 256 entries)
• The 4 GB memory space is assumed to be
divided into pages each of size 4KB .
• Hence total number of pages = 1MB or 220
• Thus ,each cache directory entry stores this
20 bits tag (page no) address A[31-12].
• The entry also consists of one state bit (to
indicate S/I) and a parity bit P.
• The parity bit is used to detect errors when
reading each entry
• The cache directories are triple ported to allow
three simultaneous directory accesses.
• Two of port support the split line access
capability, while the third port is used for
snooping.
• Each cache line holds four quad words and a
parity bit for each quad word.
Data Cache
• Data Cache
• Total size of cache = 8 KB
• Size of each way = 4 KB
• Cache line size = 32 lines
• Number of lines = 128
• Each 4 KB cache way is divided into 128 lines
• Thus 128 entries in each tag directoty
• Each directory stores a 20 bit tag (Page)
address A[31-12]. The entry also consists of
two state bits (to indicate one of four states M-
E-S-I ) and a parity bit P.
• Each data cache line is 32 byte. Parity is
generated for each byte within a data cache
line.
• When a byte of information is read from the
data cache , the parity is checked.
• The data cache itself is single ported ,
• but the cache directories are triple ported to
allow access form both pipelines ( U & V ) and
to allow an external snoop simultaneously
• The data cache is write back or
write through configured on a
line-by-line basis and follows the
MESI protocol. The data cache
tags are triple ported
 • Code cache
• Split Line Access
 • MESI Protocol
MESI protocol (known also as Illinois
protocol) is a widely used cache coherency
and memory coherence protocol, which was
later introduced by Intel in the Pentium
processor to "support the more efficient
write-back cache in addition to the write-
through cache