CHAPTER 14 CMOS DIGITAL LOGIC CIRCUITS

Chapter Outline
14.1 Digital Logic Inverters
14.2 The CMOS Inverter
14.3 Dynamic Operation of the CMOS Inverter
14.4 CMOS Logic-Gate Circuits
14.5 Implications of Technology Scaling: Issues in Deep-Submicron Design
NTUEE Electronics III 14-1
14.1 DIGITAL LOGIC INVERTERS
The Voltage-Transfer Characteristic (VTC)
The function of the inverter is to invert the logic value of its input signal
The voltage-transfer characteristic is used to evaluate the quality of inverter operation
NTUEE Electronics III 14-2
VTC parameters
V
OH
: output high level
V
OL
: output low level
V
IH
: the minimum value of input interpreted by the inverter as a logic 1
V
IL
: the maximum value of input interpreted by the inverter as a logic 0
Transition region: input level between V
IL
and V
IH
Noise Margins
The VTC is generally non-linear
V
IH
and V
IL
are defined as the points at which the slope of the VTC is 1
Robustness (noise margin at a high level): NM
H
=V
OH
V
IH
Robustness (noise margin at a low level): NM
L
=V
IL
V
OL
Static inverter characteristics for ideal VTC:
V
OH
=V
DD
V
OL
=0
V
IH
=V
IL
=V
DD
/2
NM
H
=NM
L
=V
DD
/2
NTUEE Electronics III 14-3
NM
H
NM
L
V
DD
/2
Ideal VTC
Power Dissipation
Static power dissipation: power dissipated when the inverter stays in logic 0 or logic 1
Dynamic power dissipation: power dissipated as the output is switching
Propagation Delay
t
PHL
: high-to-low propagation delay
t
PLH
: low-to-high propagation delay
t
P
(propagation delay) =( t
PLH
+t
PHL
)/2
Maximum switching frequency f
max
=1/2t
P
Theoutputtransientof theinverter canbecharacterizedbyaRC charge/dischargemodel
2

DD D
CV f P =
NTUEE Electronics III 14-4
The output transient of the inverter can be characterized by a RC charge/discharge model
RC t
O
e V V V t v
/
0
) ( ) (

+
=
Power-Delay Product and Energy-Delay Product
Power and delay are often in conflict for inverter operation
Power-delay product is a figure-of-merit for comparing logic-circuit technologies or families
Power-delay product is defined as
Energy-delay product is defined as
Silicon Area
Area reduction through advances in processing technology
Area reduction through advances in circuit design techniques
Area reduction through careful chip layout
2 /
2
DD P D
CV t P PDP = =
2 /
2
P DD
t CV EDP =
NTUEE Electronics III 14-5
Fan-In and Fan-Out
Fan-in of a gate is the number of its inputs
Fan-out is the maximum number of similar gates that a gate can drive
Logic-Circuit Families
Inverter Implementation
Simplest implementation of the inverter with a MOSFET and a load
Inverter implementation with complementary switches
NTUEE Electronics III 14-6
Inverter implementation with a double-throw switch
14.2 THE CMOS INVERTER
Circuit Operation
A CMOS inverter consists of an n-channel and a p-channel MOSFET
The n-channel device turns on and the p-channel device turns off as the input level goes high
The p-channel device turns on and the n-channel device turns off as the input level goes low
The turn-on device is modeled by a resistance:
V
OH
=V
DD
and V
OL
=0 for any CMOS inverter
( ) | |
1
'
) ( /

=
tn DD n n DSN
V V L W k r ( ) | |
1
'
|) | ( /

=
tp DD p p DSP
V V L W k r
and
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The Voltage-Transfer Characteristic
The transistors go through five different operation regions as the input goes from 0 to V
DD
The operating point is obtained by making i
DN
=i
DP
Region I: (Q
N
off; Q
P
tri.)
Region II: (Q
N
sat.; Q
P
tri.)
Region III: (Q
N
sat; Q
P
sat)
Region IV: (Q
N
tri.; Q
P
sat.)
RegionV: (Q tri ; Q off)
DP DN
i i = = ) 0 (
(

= = =
2 2
) (
2
1
) |)( | ( ) (
2
1
O DD O DD tp I DD p DP tn I n DN
v V v V V v V k i V v k i
2 2
|) | (
2
1
) (
2
1
tp I DD p DP tn I n DN
V v V k i V v k i = = =
2 2
|) | (
2
1
2
1
) (
tp I DD p DP O O tn I n DN
V v V k i v v V v k i = =
(

=
) 0 (= = i i
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Region V: (Q
N
tri.; Q
P
off)
) 0 (= =
DP DN
i i
v
O
i
D
v
O
i
D
v
O
i
D
v
O
i
D
v
O
i
D
Region I Region II
Region III Region IV Region V
Static Characteristics of the CMOS Inverter
Ratioless logic: V
OH
and V
OL
are independent of ratio of the transistors
V
OH
=V
DD
V
OL
=0
Static power dissipation is zero for both states
Noise margins can be determined by the VTC
The switching voltage (when v
I
=v
O
) is defined by
where
V
M
increases(VTC shifts) withr
1
) | (
+
+
=
r
V V V r
V
tn tp DD
M
n n
p p
n
p
L W
L W
k
k
r
) / (
) / (

= =
NTUEE Electronics III 14-9
V
M
increases (VTC shifts) with r
NM
L
increases and NM
H
decreases as r increases
NM
L
decreases and NM
H
increases as r decreases
The Matched Inverter
A matched inverter has equivalent pull-up and pull-down device with k
n
=k
p
and V
tn
=|V
tp
| =V
t
The VTC is symmetric
Determine V
IL
from the VTC in Region II:
DetermineV
IH
fromtheVTCinRegionIV:
(

=
2 2
) (
2
1
) )( ( ) (
2
1
O DD O DD t I DD t I
v V v V V v V V v
I
O
O DD
I
O
t I DD O DD t I
dv
dv
v V
dv
dv
V v V v V V v ) ( ) ( ) ( + =
) 2 3 (
8
1
t DD IL
V V V + =
NTUEE Electronics III 14-10
Determine V
IH
from the VTC in Region IV:
Noise margins: NM
H
=NM
L
=(3V
DD
+2V
t
)/8
Switching voltage: V
M
=V
DD
/2
2 2
) (
2
1
2
1
) (
t I DD O o t I
V v V v v V v =
) ( ) (
t I DD
I
O
O
I
O
t I O
V v V
dv
dv
v
dv
dv
V v v = +
) 2 5 (
8
1
t DD IH
V V V =
14.3 DYNAMIC OPERATION OF THE CMOS INVERTER
Determining the Propagation Delay
Evaluated by charging/discharge the output capacitor C through Q
P
and Q
N
Average current method:
t
PHL
:
| | ) ( ) (
2
1
M i E i I
DN DN av
+ =
2
) (
2
1
) (
tn DD n DN
V V k E i =
(
(

|
.
|

\
|

|
.
|

\
|
=
2
2 2
1
2
) ( ) (
DD DD
tn DD n DN
V V
V V k M i
C CV
NTUEE Electronics III 14-11
t
PLH
:
Propagation delay: t
P
=(t
PHL
+t
PLH
)/2
DD n
n
av
DD
PHL
V k
C
I
CV
t
o
= =
2
where
(

+ =
2
2
3
4
7
/ 2
DD
tn
DD
tn
n
V
V
V
V
o
DD p
p
av
DD
PLH
V k
C
I
CV
t
o
= =
2
where
(
(

+ =
2
2
| | 3
4
7
/ 2
DD
tp
DD
tp
n
V
V
V
V
o
An alternative approach:
Modeling the turn-on device as a resistance
Use RC charge/discharge behavior to evaluate the propagation delay
The empirical values of the resistors are given by
t
PHL
=0.69R
N
C
t
PLH
=0.69R
P
C
) (
) / (
5 . 12
O = k
L W
R
n
N
) (
) / (
30
O = k
L W
R
p
P
and
NTUEE Electronics III 14-12
Determining the Equivalent Load Capacitance
Components accountable for the equivalent load capacitance
Transistor parasitic capacitances
Wiring capacitance or interconnect capacitance
Input capacitance of the following stages
NTUEE Electronics III 14-13
w g g db db gd gd
C C C C C C C C + + + + + + =
4 3 2 1 2 1
2 2
Inverter Sizing
Minimum length permitted by the technology is usually used as the length for all channels
Device aspect ratio (W/L)
n
is usually selected in the range 1 to 1.5
The selection of (W/L)
n
is relative to (W/L)
n
Matched inverter by (W/L)
p
: (W/L)
n
=
n
:
p
(W/L)
p
=(W/L)
n
: minimum area, small propagation delay
(W/L)
p
=2(W/L)
n
: a frequently used compromise
Transistor sizing (aspect ratios are increased by a factor of S) versus propagation delay
Load capacitance:
ext ext
C SC C C C + = + =
0 int int
NTUEE Electronics III 14-14
Equivalent resistance:
Propagation delay:
Dynamic Power Dissipation
Dynamic power dissipation:
Peak current:
S
R
S
R
S
R
R
eq
P N
eq
0
) (
2
1
= + =
|
.
|

\
|
+ = +
|
|
.
|

\
|
=
ext eq eq ext
eq
P
C R
S
C R C SC
S
R
t
0 0 int 0 0 int
0
1
69 . 0 ) ( 69 . 0
2
DD D
fCV P =
2
2 2
1
|
.
|

\
|
=
tn
DD
n peak
V
V
k I
14.4 CMOS LOGIC-GATE CIRCUITS
CMOS Logic-Gate Structure
Implementation of PDN
Implementation of PUN
NTUEE Electronics III 14-15
The PDN can be most directly synthesized by expressing .
The PUN can be most directly synthesized by expressing .
The PDN can be obtained from the PUN (and vice versa) using duality property.
However, duality of the PDN and PUN is not a necessary condition.
Y
Y
Transistor Sizing
The (W/L) ratios are chosen for a worst-case gate delay equal to
that of the basic inverter
The derivation of equivalent (W/L) ratio is based on the equivalent
resistance of the transistors
1
2 1
...
) / (
1
) / (
1
) / ( Connection Series

(

+ + =
L W L W
L W
eq
1
) / (

L W r
DS
... ) / ( ) / ( ) / ( Connection Parallel
2 1
+ + = L W L W L W
eq
NTUEE Electronics III 14-16
Effects of Fan-In and Fan-Out
Each additional input to a CMOS gate requires two additional transistors
Increases the chip area and the propagation delay due to excess capacitive loading
The number of NAND gate is typically limited to 4
Redesign the logic design may be required for a higher number of inputs
Advantages of using CMOS logic: static power dissipation, ratioless design, noise margin
Disadvantage of using CMOS logic: area, complexity, capacitive loading, propagation delay
Examples for CMOS Logic Gates
NTUEE Electronics III 14-17
14.5 IMPLICATIONS OF TECHNOLOGY SCALING
Moores Law
A new technology is developed for every 2~3 years due to cost and speed requirement
The trend was predicted more than 40 years ago by Gordon Moore
For every new technology generation:
The minimum length is reduced by a factor of 1.414 and the area is reduced by a factor of 2
The cost is reduced by half or the circuit complexity is doubled
Device scaling generally decreases the parasitics and enhances the operating speed
The operating power is reduced
The current technology node advances into deep-submicron
Issuesindeep-submicrontechnologieshavetobetakenintoaccountfor circuitdesigns
NTUEE Electronics III 14-18
Issues in deep submicron technologies have to be taken into account for circuit designs
Scaling Implications
NTUEE Electronics III 14-19
Velocity Saturation
Long-channel devices:
Drift velocity: v
n
=
n
E
Electric field in the channel: E =v
DS
/L
Short-channel devices:
Velocity saturates at a critical field E
cr
with v
sat
~ 10
7
cm/s
The v
DS
at which velocity saturates is denoted by V
DSsat
V
DSsat
=E
cr
L =v
sat
L/
n
V
DSsat
is a device parameter
The I V Characteristics
NTUEE Electronics III 14-20
The I-V Characteristics
Long-channel devices
Saturation current:
Short-channel devices
For V
GS
-V
t
<V
DSsat
: same as long-channel devices
For V
GS
-V
t
>V
DSsat
:
2
) (
2
1
t GS ox n D
V V
L
W
C i =
(

=
2
2
1
) (
DSsat DSsat t GS ox n Dsat
V V V V
L
W
C I
|
.
|

\
|
=
DSsat t GS sat ox
V V V v WC
2
1
Current Equation for Velocity Saturation
For v
GS
-V
t
> V
DSsat
and v
DS
> V
DSsat
, the drain current is given by
The current is reduced from the predication of a long-channel device
The dependence on v
GS
is more linear rather than quadratic
Four regions of operation: cutoff, triode, saturation and velocity saturation
Short-channel PMOS transistors undergo velocity saturation at the same value of v
sat
The effects on PMOS are less pronounced due to lower mobility and higher V
DSsat
) 1 (
2
1
DS DSsat t GS DSsat ox n D
V V V v V
L
W
C i + |
.
|

\
|
=
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Subthreshold Conduction
The device is not complete off in deep-submicron devices as v
GS
<V
t
The subthreshold current is exponentially proportional to v
GS
: i
D
=I
s
exp(v
GS
/nV
T
)
It is a problem in digital IC design for two reasons:
Such current leads to nonzero static power dissipation for CMOS logics
May cause undesirable discharge of capacitors in dynamic CMOS logics
The Interconnect
The width of the interconnect scales down with the CMOS technology
The metal wire is no longer an ideal short
Seriesparasiticresistancemaycauseundesirablevoltagedropandexcessdelay
NTUEE Electronics III 14-22
Series parasitic resistance may cause undesirable voltage drop and excess delay
Parasitic capacitance to ground may lead to speed degradation and additional dynamic power