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  • Exp 6: Physical Analysis of Nand Gate Objective: EEE610 Custom IC Design Lab (Fall 2012-13)

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    This document summarizes an experiment analyzing the physical properties of a NAND gate. It details: sizing the PMOS and NMOS transistors based on a symmetric inverter, performing DC and transient analyses, designing a layout that passes DRC, extracting RC parasitics, and simulating post-layout. Graphs of the analyses are presented along with the netlists and layout showing it passes LVS.

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    cadence nand

    Original Title

    Exp Mihir 6 Nand

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    This document summarizes an experiment analyzing the physical properties of a NAND gate. It details: sizing the PMOS and NMOS transistors based on a symmetric inverter, performing DC and transient analyses, designing a layout that passes DRC, extracting RC parasitics, and simulating post-layout. Graphs of the analyses are presented along with the netlists and layout showing it passes LVS.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    10 views15 pages

    Exp 6: Physical Analysis of Nand Gate Objective: EEE610 Custom IC Design Lab (Fall 2012-13)

    Uploaded by

    tinku2409
    This document summarizes an experiment analyzing the physical properties of a NAND gate. It details: sizing the PMOS and NMOS transistors based on a symmetric inverter, performing DC and transient analyses, designing a layout that passes DRC, extracting RC parasitics, and simulating post-layout. Graphs of the analyses are presented along with the netlists and layout showing it passes LVS.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 15

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Exp 6: PHYSICAL ANALYSIS OF NAND GATE Objective


    i) To size the pmos and nmos of nand gate taking reference of Symmetric inverter . ii) To perform DC analysis and transient analysis of nand gate. iii) To design layout for the nand gate using Design rules. iv) To perform RCX and post layout simulation for the nand gate.

    Circuit Diagram

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Sizing Sizing of both NMOS and PMOS in NAND gate is done by keeping CMOS Inverter as the reference. Circuit Diagram after Sizing

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Output Waveforms of DC Analysis


    Output waveform with a as input.

    Ouput waveform with b as input.

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Spice Netlist of DC Analysis

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Output Waveforms of Transient Analysis

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Spice Netlist of Transient Analysis

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Layout of NAND Gate and DRC Result

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    LVS Result

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    RCX Extraction of NAND gate

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012 POST LAYOUT SIMULATION

    Register No:12MVD0087

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Symbol View Circuit Diagram

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Output Waveforms of Schematic View

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Spice Netlist

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Output Waveforms of AV-Extracted View

    EEE610 Custom IC Design Lab (Fall 2012-13)

    Experiment No: 6

    Date:07/09/2012

    Register No:12MVD0087

    Spice Netlist

    Analysis and Inference The sizing of PMOS and NMOS of NAND gate taking Reference of Symetric inverter has been performed. The DC and Transient analysis , Design Layout , RCX Extraction and Post-Layout Simulation for NAND gate has been analyzed.

    EEE610 Custom IC Design Lab (Fall 2012-13)

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