Date: November 04, 2013

Ahdl1.tdf

Project: VHDL_EX

entity JKFLIPFLOP1 is Port ( J : in std_logic ; K : in std_logic ; CLK : in std_logic ; Q : inout std_logic ; QN : inout std_logic ); end JKFLIPFLOP1 ; architecture Behavioral of JKFLIPFLOP1 is begin process (CLK,J,K) begin if (CLK='1' and CLK'event) then if(J='0' and K='0') then Q <=Q; QN <=QN; elsif(J='0' and K='1') then Q <= '1'; QN <= '0'; elsif(J='1' and K='0') then Q <= '0'; QN <= '1'; elsif(J='1' and K='1') then Q <= NOT Q; QN <= NOT QN; end if; end if; end process ; end Behavioral ;

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Revision: VHDL_EX