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Lecture12 PDF
Lecture12 PDF
CMOS Layout
Mask Layers
IC design procedure:
Layer
system specifications
Representation
circuit design
layout
n-well
purple
active
green
select (p+)
brown
polysilicon
red
metal
blue
contact
black
Layout considerations:
mask layers
devices
electrical connectivity (interconnect)
layout (design) rules
MOSFET Layout
Electrical Connectivity
select
n-well
contact to bulk
contact to well
Layout Example
polysilicon
4
VDD
VDD
active
metal
2
2
contact
2
10 12
select
14 16
18 20 m
metal
contact-topoly
2
VSS
VSS
active
polysilicon
polysilicon
active
10 12
14 16
18 20 m
n-well
Circuit Extraction
Circuit Extraction
2) Extract wiring
2) Extract wiring
VSS
VSS
VSS
10 12 14 16 18 20 m
VSS
VDD
10 12 14 16 18 20 m
VDD
VDD
10 12 14 16 18 20 m
VDD
10 12 14 16 18 20 m
Extracted Schematic
Circuit Simulation
VDD
CA-DD
(4.5/1)
Objectives:
CB-DD
(4.5/1)
evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips
Cw
(3/1)
CB-SS
Simulators:
SPICE: invented at UC Berkeley circa 1970-1975
commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley
SPICE, but add functionality, improved user interface, ...)
(3/1)
A
CA-SS
other simulators for higher speed, special needs (e.g. SPLICE, RSIM)
C w = -----------W w L w
t
thox
Interconnect capacitances CA-SS and CA-DD are the sum of polysilicon and metal
capacitances to the substrate (connected to VSS ) or the well (connected to VDD)
Limitations:
simulation results provide no insight (e.g. how to increase speed of circuit)
results sometimes wrong (errors in input, effect not modeled in SPICE)
===> always do hand-analysis first and COMPARE RESULTS