Digital Electronics Design with VHDL

Lab 1 Introduction to tools + simple gates

Student: Igor Lima de Paula
1 - Code
The code shown below brings not much more than the minimum necessary to be
synthesizable. That is the entity and the architecture of the component. VHDL is focused on
components and one can understand it as an analogy to the physical world. The entity brings
the port declarations, in other words, it defines the inputs and outputs connecting the
component to its externals; whereas, the architecture describes the internal structure and its
behaviour.

Figure 1 - VHDL code describing an AND, OR, NOT and XOR gate.

For example, given the inputs a and b, the architecture characterized in figure 1
describes five independent behaviours to generate each of its five outputs. It can be noted
from the comments in this piece of code that the outputs are respectively an AND, OR, NOT
and XOR gates and, also, another XOR gate designed from scratch.

The signal declarations before the begin statement of the architecture refer to signals
that exist only inside the component, i.e., are not observable in the outside world.
In addition, the software used here to compile and synthesise VHDL code is Quatus II.

2 Simulation
After the design of a component, a good practice is to simulate it. The simulations
were held by the software ModelSim, which has a link with Quartus II.

Figure 2 - Simulation of component. The inputs are 'a' and 'b'.

By looking at figure 2, one could infer that the output my_not depends only on input
a. Indeed it is the inverted of a signal a. All the other outputs depends on both a and b
inputs. Here it is very simple to check that all the outputs are behaving well according to the
truth table of each Boolean expression. By comparing the my_xor2 and my_xor1 signals, it
is possible to verify that the goal of designing a XOR gate using simple gates has been
accomplished as they look exactly the same.

3 - Additional Comments
This practice differentiates from the others in terms of the level of the designs. Here, it
were used only gate level description, whereas in the rest of the course it tends to come to RTL
level, which is one level higher.