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2) Verify The Behavior of Logic Gates Using Truth Tables (AND, OR, NOT, XOR, NAND, NOR, XNOR)
2) Verify The Behavior of Logic Gates Using Truth Tables (AND, OR, NOT, XOR, NAND, NOR, XNOR)
tables(AND,OR,NOT,XOR,NAND,NOR,XNOR)
AND:
entity and123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end and123;
architecture Behavioral of and123 is
begin
process (x, y)
begin
if (x='1' and y='1') then
Z <= '1';
else
Z <= '0';
end if;
end process;
end Behavioral;
0R:
entity or123 is
Port ( x : in
STD_LOGIC;
y : in
STD_LOGIC;
z : out
STD_LOGIC);
end or123;
architecture Behavioral of or123 is
begin
process (x, y)
begin
if (x='0' and y='0') then -Compare with truth table
Z <= '0';
else
Z<= '1';
end if;
end process;
end Behavioral;
NOT:
entity not123 is
Port ( x : in STD_LOGIC;
z : out STD_LOGIC);
end not123;
architecture Behavioral of not123 is
begin
process (X)
begin
if (x='0') then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;
NAND:
entity nand123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nand123;
architecture Behavioral of nand123 is
begin
Process (x, y) Begin
If (x='1' and y='1') then -- Compare with truth table
Z <= '0';
else
Z <= '1';
end if;
end process;
end Behavioral;
NOR:
entity nor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end nor123;
architecture Behavioral of nor123 is
begin
process (x, y)
begin
If (x='0' and y='0') then -- Compare with truth table
Z <= '1';
else
Z <= '0';
end if;
end process;
end Behavioral;
XOR:
entity xor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xor123;
architecture Behavioral of xor123 is
begin
process (x, y)
begin
If (x/=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;
XNOR:
entity xnor123 is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end xnor123;
architecture Behavioral of xnor123 is
begin
process (x, y)
begin
If (x=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;
end process;
end Behavioral;
HALF ADDER:
entity HA123 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end HA123;
architecture Behavioral of HA123 is
begin
s <=a xor b;
c <=a and b;
end Behavioral;
8x1MUX:
entity mux8x1 is
Port ( I : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
en_1 : in STD_LOGIC;
Y : out STD_LOGIC);
end mux8x1;
architecture Behavioral of mux4x1 is
begin
process (I,S,en_1)
begin
if en_1='0' then case s is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);
when "101" => y <= I(5);
when "110" => y <= I(6);
when "111" => y <= I(7);
when others=>null;
end case;
else y <= '0'; --y=0 when en_l=1
end if;
end process;
end Behavioral;
entity ffd1 is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end ffd1;
architecture Behavioral of ffd1 is
begin
process(clk,d)
begin
if clk='1'then q<=d;
qbar<= not d;
end if;
end process;
end Behavioral;
2)T-FlipFlop:
entity tff123 is
Port ( clk : in STD_LOGIC;
t : in STD_LOGIC;
q : inout STD_LOGIC:='0');
end tff123;
architecture Behavioral of tff123 is
begin
process(clk)
begin
if (clk' event and clk='1') then
if(t='1') then
q<= not q;
else
q<=q;
end if;
end if;
end process;
end Behavioral;