Professional Documents
Culture Documents
BO CO
PROJECT 2
TI:
H THNG GIM ST,TRUYN PHT NHIT S DNG
SNG RF TN S 2.4GHZ
GVHD
Sinh vin
: To Tun Mnh
TTT7-K56
Trn Th Minh Tuyn TTT8-K56
H Ni,12/2014
20111842
20112466
BO CO PROJECT 2
LI NI U
Ngy nay phng thc truyn nhn d liu khng dy ang ngy cng pht trin v c
ng dng rng ri trong khoa hc k thut, trong cuc sng. Cc h thng khng dy
thng nh gn, tit kim chi ph do khng phi s dng dy ni. Cc h thng khng
dy thng s dng sng wifi, sng RF. Nhng ng dng, h thng c nh, trung bnh th
s dng sng wireless truyn nhn d liu l mt la chn hp l.
Mt h thng khng dy khng ch nh gn n cn i hi phi tit kim nng lng
h thng c th s dng trong thi gian di vi cc ngun cp c lp nh pin, nng
lng mt tri. V vy,chng em la chn ti H thng gim st, truyn pht nhit
s dng sng RF tn s 2.4GHz .Do kin thc cn hn ch nn bi bo co khng trnh
khi cn nhiu sai st, chng em mong nhn c s gp ca thy bi bo co hon
thin hn.
Page 1
BO CO PROJECT 2
Li ni u1
Chng 1 M t ti.....................................................................................................5
1.1.
Yu cu chc nng.............................................................................................5
1.2.
1.3.
Chng 2
2.1.
2.2.
2.3.
2.4.
Chng 3
3.1.
S layout Master.........................................................................................17
3.2.
S layout Slave...........................................................................................18
3.3.
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BO CO PROJECT 2
DANH MC HNH NH
Hnh 1.1. S khi chc nng..........4
Hnh 2.1. S khi vi iu khin MSP430x2xx..............................................................5
Hnh 2.2. S chn MSP430G2553................................................................................6
Hnh 2.3. S cc thanh ghi trong CPU MSP430...9
Hnh 2.4. S khi module nRF24L0............................................................10
Hnh 2.5 S chn nRF24L01.....11
Hnh 2.6. S nguyn l module nRF24L0.................................................................12
Hnh 2.7. S khi DS18B20..12
Hnh 2.8. S chn ca DS18B20...................................................................................13
Hnh 2.9. S khi hin th LCD.....................................................................................14
Hnh 2.10. LCD 16x2.15
Hnh 3.1. Layout Master.....................................................................................................16
Hnh 3.2. Layout Slave.......................................................................................................17
Hnh 3.3. Hnh nh sn phm.............................................................................................18
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BO CO PROJECT 2
NI DUNG
Page 4
BO CO PROJECT 2
Chng 1
M t ti
1 Yu cu chc nng
Gim st, truyn pht song song gia mt Master v mt Slave,hin th nhit ln LCD
2 Yu cu phi chc nng
S dng dng vi iu khin MSP430 ca Texas Instrument,c th l
MSP430G2553
Module thu pht sng RF nRF24L01 ca Nordic
Cm bin nhit DS18B20
PCB nh gn
Ngun p thp 3.3V
Khong cch truyn nhn d liu ca cc module t 30m 40m.
3 S khi chc nng
KHI HIN TH
KHI TRUYN
NHN
KHI X L
KHI CM
BIN
Chng 2
2.1.
Khi x l : vi iu khin MSP430G2553
a)Gii thiu v dng VK MSP430 ca TI.
MSP430 l mt h vi iu khin 16 bit c cu trc RISC ca Texas Instrument.y l
dng vi iu khin s dng in p thp 1.8V-3.6V, tiu th dng thp. N kt hp cc
c tnh ca CPU hin i v cc thit b ngoi v. Vi CPU s dng ngun xung dao
ng ni nn kh nng x l CPU nhanh v tin li cho vic thit k mch.
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BO CO PROJECT 2
MSP430 h tr cc chun giao tip : UART, SPI, I2C, IrDA VK MSP430 c th giao
tip vi cc thit b ngoi vi, cc b nh ngoi, cc vi iu khin khc.
Bn trong VK cn tch hp mt cm bin nhit .
Ngoi ra n cn h tr b chuyn i ADC, DAC ni tch hp trong VK.
MSP430 l mt la chn hp l cho cc ng dng nh gn, tit kim nng lng.
b)VK MSP430G2553.
b1)Thng s k thut ca MSP430G2553.
+Ngun in th s dng trong khong t 1.8V n 3.6V.
Ch hot ng: 270 A ti 1MHz v 2.2V.
Ch ng: 0.7 A.
Ch khng hot ng: 0.1 A.
Thi gian thc dy t ch ng t hn 1s.
+Cu trc RISC 16 Bit, mi chu k lnh hot ng mt 62.5ns.
+H tr cc giao din giao tip nh: UART, SPI.
+H tr mt timer A.
+B chuyn i ADC 10-Bit vi tc chuyn i ln n 200ksps.
+B nh flash 16KB.
+B nh RAM 512B.
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BO CO PROJECT 2
BO CO PROJECT 2
Comparator_A+, ng ra.
- P1.4/ SMCLK/ UCB0STE/ UCA0CLK/ A4/VREF+/VEREF+/ CA4/TCK (Pin 6):
Chn chc nng vo/ra s.
SMCLK tn hiu ng ra.
USCI_B0 Cho php Slave truyn.
USCI_A0 clock ng vo/ng ra .
ADC10 ng vo tng t A4 (1).
ADC10 in p tham chiu dng.
Comparator_A+, CA4 ng vo.
JTAG xung nhp kim tra, ng vo ni tip cho thit b np v kim tra
chng trnh.
- P1.5/ TA0.0/ UCB0CLK/ UCA0STE/ A5/CA5/TMS (Pin 7):\
Chn chc nng vo/ra s.
Timer0_A, compare: Out0 ng ra / BSL nhn .
USCI_B0 clock ng vo/ng ra.
USCI_A0 cho php slave truyn.
ADC10 ng vo tng t A5 .
Comparator_A+, CA5 ng vo.
JTAG la chn ch kim tra, ng vo ni tip cho thit b np v kim tra
chng trnh.
- P2.0/TA1.0 (Pin 8):
Chn chc nng vo/ra s.
Timer1_A, capture: CCI0A ng vo, compare: Out0 ng ra.
- P2.1/TA1.1 (Pin 9):
Chn chc nng vo/ra s.
Timer1_A, capture: CCI1A ng vo, compare: Out1 ng ra.
- P2.2/TA1.1( Pin 10):
Chn chc nng vo/ra s.
Timer1_A, capture: CCI1B ng vo, compare: Out1 ng ra.
- P2.3/TA1.0 (Pin 11):
Chn chc nng vo/ra s.
Timer1_A, capture: CCI0B ng vo, compare: Out0 ng ra.
- P2.4/TA1.2( Pin 12):
Chn chc nng vo/ra s .
Timer1_A, capture: CCI2A ng vo, compare: Out2 ng ra.
- P2.5/TA1.2 (Pin 13):
Chn chc nng vo/ra s .
Timer1_A, capture: CCI2B ng vo, compare: Out2 ng ra.
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BO CO PROJECT 2
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BO CO PROJECT 2
CPU ca vi iu khin MSP430g2553 c kin trc RISC 16 Bit (Reduced Intruction Set
Computer) l mt kin trc vi x l theo hng n gin ha tp lnh. Cc lnh c xy
dng c th thc hin vi ch 1 chu k my. Mt khc, bus d liu v bus a ch (c
rng 16 Bit) tch ri nhau iu ny gip cho qu trnh c d liu v m lnh c th
din ra ng thi do nng cao hiu sut lm vic ca vi iu khin.
CPU ca vi iu khin MSP430g2553 gm 16 thanh ghi 16 Bit. Trong R0 n R3 c
cc chc nng c bit nh: thanh ghi m chng trnh, thanh ghi con tr, thanh ghi
trng thi, thanh ghi hng. Cc thanh ghi cn li c s dng vi mc ch chung.
RAM
Ngoi vi:
+ 16 bit.
+ 8 bit.
+ 8 bit FSR.
512 Byte
a ch
0xFFFF to
0xFFC0
0xFFFF to 0xC000
0x03FF to 0x0200
0x01FF to
0x0100
0x0FF to 0x010
0x0Fh to 0x00
Page 10
BO CO PROJECT 2
2.2.
Khi truyn pht : Module nRF24L01
a) Gii thiu
nRF24L01 l mt trong nhng dng sn phm ca nh sn xut Nordic (Nauy), c chc
nng thu pht tn hiu qua sng RF s dng in p thp (3.3V).
Mt vi im chnh ca chip nRF24L01:
Thc hin chc nng thu pht d liu bng sng RF tn s 2.4GHz.
S dng dng sng iu ch GFSK.
Tc truyn ti d liu trong khng kh 1Mbp 2Mbp.
Tiu th nng lng thp, s dng in p thp (3.3V).
S dng giao thc phn cng Shockburst.
+ T ng to gi d liu (Preamble, Address, CRC).
+ T ng pht hin gi d liu v xc nhn.
+ La chn d liu t 1-32 Byte.
+ C kh nng truyn li d liu
+ T ng xc nhn m ACK.
+ C 6 ng dn truyn nhn d liu.
S dng giao thc SPI trao i d liu vi Vi iu khin, tc truyn nhn d
liu ln ti 10Mbp.
Mt s ng dng c bn ca nRF24L01:
Thit b ngoi vi my tnh khng dy.
ng dng trong chut, bn phm v iu khin t xa.
iu khin t xa bng sng RF cho cc thit b in t tiu dng.
Mng cm bin vi in nng cc thp.
T ng ha trong thng mi v gia dng
ng dng trong chi.
b) S khi
Page 11
BO CO PROJECT 2
Thng s
Notes Min.
VDD in p cung cp
VDD in p tn hiu ng vo >3.6V
TEMP Nhit lm vic
Typ.
Max. Units
1.9
3.0
3.6
2.7
3.0
3.3
-40
+27
+85
e) Hot ng ca nRF24L01.
nRF24L01 c nm ch hot ng c bn c iu khin bi cc bit PWR_UP,
PRIM_RX trong thanh ghi CONFIG v chn CE.
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BO CO PROJECT 2
PWR_UP
Bit
1
1
1
PRIM_RX Bit
1
1
0
0
-
1
0
0
CE
1
1
Xung cao ti thiu
10s
1
0
-
g) S nguyn l
BO CO PROJECT 2
b) S khi
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BO CO PROJECT 2
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BO CO PROJECT 2
BO CO PROJECT 2
Chn chn thanh ghi RS (Register Select): C hai thanh ghi trong LCD, chn
RS(Register Select) c dng chn thanh ghi, nhsau: Nu RS = 0 th
thanh ghi m lnh c chn cho php ngi dng gi mt lnh chng hn nh
xo mn hnh, a con trv u dng v.v Nu RS = 1 th thanh ghi d
liu c chn cho php ngi dng gi dliu cn hin thtrn LCD.
Chn c/ ghi (R/W): u vo c/ ghi cho php ngi dng ghi thng tin ln
LCD khi R/W = 0 hoc c thng tin tn khi R/W = 1.
Chn cho php E (Enable): Chn cho php E c sdng bi LCD cht d
liu ca n. Khi dliu c cp n chn dliu th mt xung mc cao xung
thp phi c p n chn ny LCD cht dliu trn cc chn d liu.
Xung ny phi rng ti thiu l 450ns.
Chn D0 - D7: y l 8 chn dliu 8 bt, c dng gi thng tin ln LCD
hoc c ni dung ca cc thanh ghi trong LCD. Tuy nhin trong mch s
dng LCD 4 bit nn 4 chn D0-D3 s khng s dng. hin thcc chci v cc
con s, chng ta gi cc m ASCII ca cc chci tA n Z, a n f v cc con s
t 0 - 9 n cc chn ny khi bt RS = 1.
Cng c cc m lnh m c th c gi n LCD xo mn hnh hoc a con
trv u dng hoc nhp nhy con tr.
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BO CO PROJECT 2
Chng 3
3.1.
S layout Master
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BO CO PROJECT 2
3.2.
S layout Slave
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BO CO PROJECT 2
3.3.
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BO CO PROJECT 2
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