ECE 8053 – Project Fall’02

Design of 64-bit Low Power Spanning Tree

Carry Lookahead Adder

Presented by
Suderson Soundararajan
 Overview
• Introduction
• Design
• Optimization for Power
• Optimization for Performance
• Optimization for Area
• Usage of CAD tools
• Presentation of Results and Comparison
• Summary and Conclusion
• References
Design
 Optimization for Power
• Low Power and High Performance Full
Adder Cell

Full Adder Cell – A Novel High Performance CMOS 1-bit Full Adder cell,
Ahmed M.Shams, Bayoumi, M.A
 Optimization for Speed
• Domino!
• Two-Phase Clock – Generated using
Chopper Circuit
 Optimization for Speed Contd..

MCC – Group Propagate MCC – Group Generate

Signal Generation Signal Generation
 Optimization for Area

4-bit Carry Select Adder - Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry
Select adder with Reduced Area”

Less Number of Transistors => Less Area

Delay and Power Dissipation

MCC MCC3 MCC2

Blocks

Delay 420 ps 300 ps

Power 15 uW 11 uW
 Usage of CAD tools
• Functionality Verification -
Gate Level Verilog – ModelSim
• Synthesis -
Flattened Netlist – Synopsys
• Transistor Level Simulation and Testing -
Netlist - Cadence Spectre
Results
Delay 2.4 ns 3.2 ns
Power 5.7 mW 3.6 mW

Comparison
Parameters Delay Transistor
Count
Spanning Tree Carry 3.2 ns 6390
Lookahead Adder
Variable Spanning Tree Carry 2.8 ns 5671
Lookahead Adder
Hybrid Spanning Tree Carry 2.4 ns 2475
Lookahead Adder
 Conclusion
• Achieved Low Power and High Performance
compared to the conventional one
• Can still optimize for Power – Carry Lookahead
Scheme
• Can still optimize for Speed – Sizing!
 References
• Thomas Lynch, Earl E.Swartzlander, “A Spanning Tree Carry
Lookahead Adder,” IEEE transactions, Vol 41, No.8, August 1992.
• Jeffrey Blackburn, Lisa Amdt, Earl E.Swartzlander, “Optimization of
Carry Lookahead Adders”, 1997, IEEE transactions.
• Ahmed M.Shams, Bayoumi, M.A, “A Novel High Performance
CMOS 1-bit Full Adder Cell”, IEEE transactions, Vol.47, No.5,
May’2000.
• Youngjoon Kim; Lee-Sup Kim. “A Low Power Carry Select adder
with Reduced Area, Circuits and Systems,” ISCAS 2001. The 2001
IEEE International Symposium on, Volume: 4, 2001 Page(s): 218 –
221