Application of FinFET Technology to Analog/RF Circuits

Matthew Muh, Professor Ali M. Niknejad

Research plans
Evaluating the suitability of FinFET technology for analog/RF circuits involves the following:
Developing a working model for SPICE simulation based on measurements and/or 3-D device simulation Finding optimal device layouts for high-frequency performance Designing, fabricating test circuits (e.g., frequency divider, LNA, oscillator) and verifying speed, power gain, noise, linearity Refining device models based on circuit-level measurements Comparing utility of FinFET for different applications

RF CMOS performance trends

Effect of technology scaling on RF performance: fT: improves with scaling (proportional to 1/L in velocity saturation); assuming fT ~ 75 GHz for a 0.13 m MOSFET, then fT ~ 150 GHz for a 60-nm FinFET fMAX: improves with scaling, but exhibits strong dependence on layout, gate resistance, and parasitics FMIN: decreases with scaling for a given frequency due to increase in fT A sub-100nm advanced transistor structure (FinFET) should be able to take advantage of these RF scaling trends. Can it confer additional benefits to analog/RF circuits, such as improved gmro or linearity?

High-frequency modeling
Impact of gate resistance on RF performance
if ignored, potential error in impedance matching (e.g., to a 50 increased minimum noise figure reduced power gain, degraded overall transconductance fMAX
}

source)

2 Rg (g mCgd

ft Cgg )  (Rg  rch  Rs ) g ds

Gate resistance modeling

Rgate consists of two components:
distributed gate electrode resistance channel-induced gate resistance

Minimize gate resistance by using

proper layout (multi-finger design) silicided polysilicon gate/metal gate technologies

Source: Jin, IEDM98

Problem is alleviated in FinFETs utilizing metal gate to adjust Vt

FinFET structure and layout

The double-gate FinFETa promising candidate to continue CMOS scaling deep into the nanometer regime Gate straddles thin silicon fin, forming two conducting channels on sidewalls
e G te Length = Lg Source G te Gate 2
Source Dr in G te

G te 1 Dr in Drain Current Flow

Fin Heigh = Hfin = W Height Fin Width Wfin = TSi

3D view of FinFET

Layout similar to bulk-Si MOSFET

Source G te Dr in

Pfin
Source G te Dr in

Source

Bulk-Si MOSFET

Source (all images): T-J King, et al, FinFET Technology Optimization presentation slides, Oct. 2003

Source
Multi-fin layout

Simulated n-FinFET high-frequency behavior

Initial simulation results using BSIMSOI3.1 model, adapted from preliminary SPAWAR FinFET model (extrapolated DC, estimated AC parameters), ignoring gate resistance Device exhibits high source/drain parasitic resistance Need an improved high-frequency device model

GTU,max

W/L = 1um/0.06um I s = 80uA Vgs = V s = 1V

MSG

MAG

fT = 34 GHz fMAX = 8 GHz fT much lower than expected

FinFET modeling approach

Need a suitable SPICE model for initial design based on transistor IV and high-frequency AC characteristics Modeling approaches
Small-signal equivalent model
Uses simple lumped circuit elements Suitable for only selected bias points Avoids need for complete device model Valid only for small-signal operation
Lg Gat Rs Cgsext Csb Cgdext Ld ain Cdb

Rd Rg

Rdb Rbb Bulk

Subcircuit model (adapt 60-GHz CMOS approach)

Begin with core BSIMSOI model Extend core subcircuit with extrinsic parasitics (BSIMSOI3.1 already includes gate resistance model) DC I-V curve fitting to extract core BSIM parameters Small-signal Y-parameter fitting to extract parasitic component values Also suitable for large-signal simulation

Rsb

Ls

Sou

Generic subcircuit model (core MOSFET shown in color)

(Adapted from S. Enami, C. Doan, V-Band CMOS Mixers)

Small-signal lumped-element model

Performed 3-D device simulation to generate I-V and y-parameter curves Performed initial high-frequency curve fitting to obtain circuit parameters for basic small-signal model. Need to refine 3D device structure to obtain better accuracy.
rg Gate Cgs ri + vgs gm*vgs Cgd Cd ds rd rain
RE(Y11) (ss model) RE(Y11) (ISE) 6.0E 04 5.0E 04 4.0E 04 (1/ ) (1/ ) 3.0E 04 2.0E 04 1.0E 04

rd ds

rs

Source

0 0E+00 Frequency (H )

1.6E 04 1.0E+09 1.0E+10 1.0E+11 1.0E+12 Frequency (H )

1.0E+09

1.0E+10

1.0E+11

1.0E+12

rg rd rs ri rds

80 210 160 1000 140 k

Cgs Cgd Cds gm

104 aF 22 aF 2 aF 160 S
(1/ )

RE(Y21) (ss model) RE(Y21) (ISE) 2.0E-04 1.5E-04 1.0E-04 5.0E-05 0.0E+00 -5.0E-05 -1.0E-04 -1.5E-04 -2.0E-04 -2.5E-04 -3.0E-04 1.0E+09 1.0E+10

IM(Y21) (ss model) IM(Y21) (ISE)

RE(Y22) (ss model) RE(Y22) (ISE) 1.6E-04 1.4E-04 1.2E-04 (1/ ) 1.0E-04 8.0E-05 6.0E-05 4.0E-05 2.0E-05 0.0E+00

IM(Y22) (ss model) IM(Y22) (ISE)

W/L = 0.1 m/0.065 m Vgs = 1.5 V, Vds = 1 V

1.0E+11

1.0E+12

1.0E+09

1.0E+10

1.0E+11

Frequency (H )

Frequency (H )

M(Y11) (ss model) IM(Y11) (ISE)

RE(Y12) (ss model) RE(Y12) (ISE) 0.0E+00 -2.0E-05 -4.0E-05 -6.0E-05 -8.0E-05 -1.0E-04 -1.2E-04 -1.4E-04

IM(Y12) (ss model) IM(Y12) (ISE)

1.0E+12

Test structures

VDD

SCL static frequency dividera good benchmark for high-speed technologies UCB Microlab FinFET process, target gate length ~ 35 nm, fin thickness = 20 nm, metal gate technology (polySi + Mo) Circuit-level simulation using simple AHDL behavioral model based on device simulation results with lumped capacitances One-metal and two-metal versions, some rotated by 45 to enhance NMOS mobility Individual transistors included for DC and S-parameter characterization

BIAS2

BIAS1 CLK

VOUT

GND

frequency divider schematic Estimated maximum operating frequency near 40 GHz for single metal version. Core divider power consumption ~ 6.6 mW

single metal layout

(probe pads also utilize second metal)

Future work
Investigate additional circuits, e.g., VCO, LNA Characterize individual transistors by measuring DC/AC behavior of fabricated devices Refine 3-D device simulations to improve accuracy, especially with respect to parasitic resistances and output resistance Build large-signal subcircuit BSIM model based on simulation results and/or measured data With an improved model, design additional analog/RF circuits for system-level verification of power gain, noise, etc.