Buckconverters For Portable Application

Magnetic Buck Converters for Portable Applications
Frank De Stasi Mathew Jacob
Outline
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Why use Switching Regulators? Common Device/Converter Specifications Buck Converter Analysis CCM/DCM modes Selection of L and C Synchronous Buck Converters Conduction and Switching Losses Efficiency improvement using PWM/PFM/LDO modes Control Approaches Current Mode Models and Compensation Guidelines Transient Measurement Techniques Layout Guidelines
2
2003 National Semiconductor Corporation
Efficiency
Ig Io
Power supply
Vg +
+ Vo _
P/DSP core
output DC power Po Vo I o = = = input DC power Pg Vg I g
3
Linear voltage regulator as power supply

Series pass transistor
Q Iload + Vg + C Vo
Load
Vref
Bandgap reference
Simple, low noise, small footprint area Output voltage lower than the battery voltage High efficiency only if Vo is close to Vg
4
Linear regulator power model

Ig Rs Io + Vg + IQ Vo
Bias current
I g = Io + IQ
Efficiency:
Vo ?< Linear regulator efficiency cannot be greater Vg than the ratio of the output and the input voltage
5
Vo I o Vo I o ?= = Vg I g Vg ( I o + I Q )
SMPS efficiency as a function of load

100 90 80 70 Efficiency [%] 60 50 40 . 30 20 10 0 0.1 1 10 Io [mA] 100 1000
Buck regulator
Example: Vg = 3.6 V Vo = 1.5 V 0 < Io < 300 mA
Linear regulator
6
Buck (step-down) switching power converter

Ig
1
Low-pass LC filter
+
2
L + C
Io
Vg
vs (t)
v(t)
Load
vs(t)
Vg DTs 0 DTs 1 2 D' Ts 0 Ts
fs = 1/Ts = switching frequency

t
1
Switch position:
D = switch duty cycle

7
Buck converter ideal static characteristic

vs(t)
Vg area = DTsVg
vs = DVg
0 DTs
V Vg
t Conversion ratio:
Ts
Vo =D Vg
0 1 D
8
switch duty cycle
Switch-Mode Power Supplies

Step-up, step-down and inverting configurations available Switching converters are ideally 100% efficient Real efficiency can be close to 100%; depends on operating conditions and implementation
Losses and efficiency will be discussed
Converters generate switching noise Discrete filter components (L, C) are required Higher switching frequency => smaller L, C
Component selection will be discussed
Duty cycle is the control variable Closed-loop output voltage control is usually applied
Dynamic models and control will be discussed
9
Impact of efficiency: a system example

uP/DSP core mode % of time in this mode Load current Io [mA] Linear regulator Efficiency [%] Battery current Ig [mA] Average Ig in this mode [mA] 4.45 Efficiency [%] Battery current Ig [mA] Average Ig in this mode [mA] 2.12 29.1 0.14 0.13 78.4 0.53 0.02 93.7 4.45 0.13 93.0 44.82 1.12 87.7 142.60 0.71 Stand-by 90.0 0.1 34.7 0.12 0.11 Wait 4.0 1.0 40.9 1.02 0.04 Run1 3.0 10.0 41.6 10.02 0.30 Run2 2.5 100.0 41.7 100.02 2.50 FullRun 0.5 300.0 41.7 300.02 1.50
Total linear reg average Ig [mA] SMPS
Total SMPS average Ig [mA]
Example: Vg = 3.6 V Vo = 1.5 V 0 < Io < 300 mA

10
Advantages of using SMPS over Linear regulators

SMPS results in significantly lower average battery current High efficiency over a wide range of loads and output voltages is achieved with a SMPS SMPS with low quiescent current modes provide longer battery life for mobile systems that spend most of their time in stand-by
11
Buck regulators in the system

Power distribution: Vg = 2.8-5.5 V
PS 3.6 V PS 2.5 V 1.5 V PS
Battery
Charger
Buck SMPS regulators

1-3.6 V
PS
Antenna
Display
PS 2.7-5.5 V
Audio Interface
P/DSP core I/O

Baseband digital 2.5 V PS
D/A
LO
PA
LNA
A/D
Analog/RF 2.5 V PS
2.5 V PS
Buck regulators are often used as switch-mode power supplies for baseband digital core and the RF power amplifier (PA)
12
Device/Converter Specifications
Static voltage regulation
DC output voltage precision, i.e., % variation with respect to the nominal value over: input voltage range (line regulation) output load range (load regulation) temperature
Dynamic voltage regulation

Load transient response, including peak output voltage variation and settling time for a step load transient Line transient response, including output voltage variation and settling time for a step input voltage transient
13
Overvoltage protection
prevents the output voltage from rising above a specified limit
Undervoltage shutdown
turns the device off if the input (battery) voltage drops below a specified threshold
Current limiting (overload protection)

limits the load current
Thermal shutdown
turns the device off if the temperature exceeds a specified threshold
14
Frequency synchronization
allows synchronization of the switching frequency to an external system clock
Soft start
controlled output voltage increase during startup
Shut-down and operating-mode control

enables a system controller to shut-down the device, or to select an operating mode(PWM,PFM,LDO)
Adjustment of the output voltage using

a resistive voltage divider, external analog control voltage, or digital (pin-select) control
15
Buck converter analysis

1
iL (t)
L + vL (t) + iC(t) R v(t)
Vg
iL(t)
L + vL(t) iC(t) R + v(t)

Vg +
L + v L(t) iL(t) C iC(t) R v(t) +
Vg
Switch in position 1
16
iL (t)
Inductor voltage:
L + vL(t) iC(t) R + v(t)
vL = Vg v(t )
Small-ripple approximation:
Vg
vL Vg V
Knowing the voltage, we can solve for the current from: Solve for the slope:
diL vL Vg V = dt L L
diL vL = L dt
Therefore, the inductor current increases in time with an essentially constant slope.
17
L
Inductor voltage:
+ vL (t) Vg + iL (t) C
vL = v (t )
Small-ripple approximation:
iC(t) R
+ v(t)
vL V
Knowing the voltage, we can solve for the current from: Solve for the slope:
diL vL = L dt
diL vL V = dt L L
Therefore, the inductor current decreases in time with an essentially constant slope.
18
Inductor voltage and current waveforms

vL(t)
Vg V DTs D'Ts V Switch position: iL(t) 1 2 1
iL(DTs)
I iL(0)
iL
DTs
Ts
t
19
Average voltage across the inductor equals zero

vL(t) Vg V Total area t V
DTs
Ts
vL =
1 vL dt = D (Vg V ) + (1 D )(V ) = 0 Ts 0 V = DVg
The DC output voltage is directly proportional to the input voltage and the switch duty cycle
20
Average inductor current equals the output current

1
iL (t)
L + vL(t)
IO
i C(t) R
+ v(t)
Vg
v (t ) V iC (t ) = iL (t ) iL (t ) = iL (t ) I o R R
We know that the average capacitor current equals zero
iC
1 = iC dt = iL I o = 0 Ts 0
Ts
iL = I o
In steady state, the average inductor current equals the load current
21
Light-load operation: CCM and DCM

iL (t )
without zero cross detect
high I o low I o
Inductor current reverses polarity at light loads
iL (t )
with zero cross detect
high I o low I o
t
Inductor current drops to zero before the end of the cycle: Discontinuous conduction mode (DCM)
22
Implementing Zero-cross detect

S1
iL(t)
L + vL(t) iC(t)
Io + v(t)
Vg +
C
S2
S2 is turned OFF
S2 control logic
S2
With the zero-crossing comparator the switch S2 operates as a diode, resulting in DCM and improved efficiency at light loads All switchers in the LM26XX family have this feature
23
CCM vs. DCM

In DCM, the inductor current is always positive At light loads, in DCM, the duty cycle is significantly lower than in CCM CCM operation at light loads is undesirable because the reversal of the inductor current polarity contributes to conduction losses, while it does not contribute to the output load current With a diode rectifier, DCM operation occurs automatically because of the diode characteristic With a synchronous rectifier, DCM operation at light loads can be accomplished by turning off the NMOS switch at the zero-crossing of the inductor current
24
DCM/CCM boundary
Boundary between constant-frequency CCM and constant-frequency DCM depends on the circuit parameters and the load At the CCM/DCM boundary the inductor current ripple equals the output load current:
Vg V V I o = iL = = ICCM / DCM 2 Lf s Vg
If Io > ICCM/DCM, the buck converter operates in CCM If Io < ICCM/DCM, the buck converter operates in DCM
25
Static characteristic in DCM

V D2 = Vg D 2 + 2 Lf s I o Vg
2 VL fs I o D= Vg (Vg V )
As the load Io in DCM decreases, the duty cycle D must decrease to keep the output V in regulation Minimum possible on-time tp,min of the PMOS limits the minimum load current Io,min in constantfrequency PWM mode for which the output stays in regulation: If the output load current is reduced beyond Io,min the output voltage will start to rise and over voltage protection will activate.
I o ,min =
Vg V Vg V 2L
t 2 ,min f s p
26
Determination of the inductor current ripple magnitude

iL(t) I iL(0) iL(DTs)
iL
DTs
Ts
(change in iL) = (slope)x(length of subinterval) Current ripple magnitude
2iL =
Vg V L
DTs
Basic inductance selection eq.
iL =
Vg V 2 Lf s
L=
Vg V 2iL f s
D
27
iC(t) Total charge q
0
DTs
vC(t) V
Output capacitor voltage ripple 1 Ts q = C ( 2v ) q = iL 2 2 i t iL T /2 (neglecting esr) ( 2 v ) D'T 4Cf s iL ( 2 v ) [2D 1 + 8ResrCf s ] 4Cf s v
L s s
(including esr)
The peak to peak output voltage ripple is the larger of the two values in the equations above.The equations can be used as capacitance selection equations if a target peak to peak output voltage ripple is known.
28
Practice problem: selection of L and C

LM2612 is used to generate the output voltage of V = 1.5V at the max. DC output current of Io = 300 mA The input voltage is between Vg = 2.8V and Vg = 5.5V Select L and C so that: the worst-case peak current ripple is iL = 120 mA, and the worst-case peak-to-peak output voltage ripple is 2v = 5 mV
29
Inductor selection
Vg V V V 1 V 1 L= D= = 2iL f s 2iL f s Vg 2iL f s Vg Vg V
LM2612 datasheet: Switching frequency is between fsmin = 468 kHz and fsmax = 732 kHz
V 1 L 2iL f s min
1 V V g max
= 9.7 H
A 10H inductor is chosen in the datasheet

30
Output filter capacitor selection
1 iL C= 4 f s ( 2 v )
1 iL max C = 12.8F 4 f s min (2v)
A 22F ceramic capacitor is chosen in the datasheet. A 10F capacitor can also be used with slightly higher output ripple, in case the load transient requirements are not demanding.
31
Input current waveform

1
iL (t)
L + vL (t) iC(t) R + v(t)
ig (t )
Vg +
2
Cg
ig (t)
Input current is pulsating, with large switching-noise component Input filter (decoupling) capacitor is mandatory to reduce the input voltage noise and ensure proper operation of the device to prevent propagation of the switching noise to other system components
32
Capacitor ripple currents

2iL Ripple Current Ratio = =r IO
Irms Input Capacitor = IO
r2 D(1 D + ) 12 r 12
(Vg Vo) D r= L fs min IO
Irms Output Capacitor = IO
L = 10 H
r = 0.962
Vg = 3.6 V
Vo = 1.8 V
fs min = 468 kHz

Io = 400 mA
r = 0.481
Io = 200 mA
Irms Input Capacitor = 107 mA Irms Output Capacitor = 56 mA
Irms Input Capacitor = 204 mA
Irms Output Capacitor = 56 mA

33
Capacitors : How small can I go ?

Output Capacitor Input Capacitor
When reducing the value of output capacitors ensure proper gain and phase margins and evaluate line/load transient performance and whether it meets requirements.
34
Switch realization with a synchronous rectifier
Synchronous Buck
PMOS: main switch
PMOS
NMOS: synchronous rectifier

ip(t) in(t)
NMOS
iL(t)
L iC(t)
Io + v(t)
+ + v (t) L vsw(t) C
Vg
vp
vn
drivers
n p
Switch control signals
p n td1 td2 dead times
Dead times are used to prevent short-circuit current through PMOS/NMOS
35
Switch currents
Average and RMS values
i p (t )
I p = i p (t ) DI o
I p ,rms =
t
in (t )
i 2 (t ) D I o p
I n = in (t ) (1 D) I o
t
I n,rms =
in2 (t ) 1 D I o
Switch on-resistance and forward voltage drops result in switch conduction losses
36
Conduction-loss models
_
vON body diode
_
Ron,p + vON i p(t) _ vn
ON
+ vON body diode i n(t) _

OFF
Ron,n _ vON
i p(t) + vSG _ vp
ON OFF
i n(t) +
vGS +
PMOS: On-resistance Ron,p

_ vON + in(t)
NMOS: On-resistance Ron,n

L iL(t)
RD _ vON
VD
in(t) +
RL winding + resistance
ideal L vL _
i L(t)
Diode: Forward voltage drop VD in series with on-resistance RD
Winding resistance RL
37
Buck circuit when the PMOS is ON

Ron,p + + Vg vON ip (t) _ RL winding + resistance ideal L vL _ iL(t) Io + V _
v L = Vg ( Ron , p + RL )iL v Vg ( Ron , p + RL ) I o V
iL I o
38
Buck circuit when the NMOS is ON

RL winding + resistance ideal L vL _ + V _ iL (t) Io
R on,n
Vg
v L = ( Ron, n + RL )iL v ( Ron , n + RL ) I o V
ig = 0
39
Steady-state model with conduction losses

Inductor volt-second balance: Input current: I g = i g = DI o
vL = 0
V = DVg ( DRon , p + (1 D )Ron , n + RL ) I o

V + Io ( Ron , n + RL ) Duty cycle considering losses D = Vg + Io ( Ron , n Ron , p ) Equivalent steady-state circuit model with conduction losses:
Ig DRon,p + (1-D)Ron,n + RL Io + Vg + DIo + DV g R V
40
Switching losses
Switching losses are proportional to the switching frequency Switching loss mechanisms:
Charging/discharging of capacitance at MOSFET gates and switch node Inductive switching transitions Body-diode reverse recovery Oscillator and other misc. controller losses Inductor eddy-current and core losses
41
Improving light-load efficiency

In PWM mode, light-load efficiency is reduced because a significant portion of switching losses does not scale with load In PWM mode, the oscillator and the power switches are always switching at high switching frequency Low-power modes are based on the idea of reducing the switching frequency in proportion to the load If the switching frequency is proportional to load, high efficiency can be maintained over a very wide range of loads
42
Switching frequency in PFM mode

tp =
Ipeak iL
I o = iL
LI peak Vg Vo
LI peak Vo
tn =
tp
tn
Ts
1 I o = I peak (t p + t n ) f s 2
2Vo I o Vo f s = 2 1 LI peak Vg
In PFM, the switching frequency is directly proportional to the load current

43
Output voltage ripple in PFM

Ipeak iL
I o = iL
tp
tn
Ts
2 LI peak
( 2v )
I peak 2C
(t p + t n ) =
Vg
2C Vo (Vg Vo )
The output voltage ripple is typically higher in PFM than in constant-frequency PWM mode
44
PWM/PFM Combination
100% 90% 80% 70%
Efficiency
60% 50% 40% 30% 20%
Vin = 3.6V
10% 0% 0.1 1 10 100 1000
Iout in mA
LM2618 PFM
LM2618 PWM
High efficiency over very wide range of loads Low IQ
45
Discussion of Operating Modes

Best efficiency at moderate to heavy load Constant-frequency, low switching noise Synchronization to external clock possible Relatively high IQ and poor lightload efficiency
PWM
LDO
LDO: linear regulator Low-noise Very low IQ Simple controller
PFM
High efficiency over very wide load range Very low IQ Simple controller Increased output voltage ripple
46
PWM/LDO Combination
Example: LM2608
PWM
LDO
PFM
High efficiency (moderate-to-heavy load) Low noise: Constant-frequency operation No switching noise at very light loads (LDO) Very low IQ 47
PWM/PFM Combination
PWM
Examples: LM2612/LM2614
LDO
PFM
High efficiency over very wide range of loads Low IQ

48
Selection Guide
49
Control approaches in constant-frequency PWM mode
Voltage-mode control
The switch duty cycle is controlled based on output voltage sensing
Current-mode control
The switch duty cycle is controlled based on output voltage and switch current sensing
50
Voltage-Mode Control Architecture

Power input iL(t) + vg (t) + vsw(t) Gate drivers p n Compensator Pulse-width modulator
p(t) vc(t)
L + vL(t) C iC(t)
Io Load + v(t) Feedback connection
Dead-time
vc
G c (s) Voltage reference Vref

t
dTs Ts
Controller chip
51
Current-Mode Control Architecture

Power input ip(t) L + vL(t) + C vsw(t) Gate drivers p n Rsip (t) Compensator vc Gc(s) Voltage reference Vref
t
iL(t) iC(t)
Io Load + v(t) Feedback connection
vg(t) +
Dead-time
Current-mode modulator
p(t) v c(t)
dTs Ts
Controller chip
52
Current-mode summary
Advantages of current-mode control
Simpler, approximately single-pole responses Inherent rejection of line disturbances Built-in over-current protection
LM26XX family is based on current-mode architecture LM2608/12/18 feature internal compensation LM2614/19 require external compensation
53
Important definitions
Cross-over frequency fc is the frequency where the magnitude response of the loop gain drops to 1, i.e. 0 dB T ( jwc ) = 1 0 dB Phase margin PM is the difference between the phase of the loop gain at the cross-over frequency and -180o
PM = phase [T ( jwc )] + 180o

Gain margin GM (in dB) is the negative of the loop-gain magnitude response (in dB) at the frequency fm where the phase of the loop gain equals -180o
GM = 20 log T ( jwm ) , phase [T ( jwm )] = 180o

54
Example of finding phase and gain margins

1 100 50 0 -50 -100 -150 10. 100. 1000. 10000.
GM
PM
10.
100.
1000.
10000.
100000.
f c 10 KHz
PM = 71o
GM = 24 dB
55
Current Mode Power Stage Model

L
Vo Ro gm ESR
C
Vc
Vo gm ( Ro // R ) (1 + s ESR C ) Vc (1 + s ( Ro // R ) C ) (1 + s L ) Ro
56
Closed Loop Regulator Model

L
Vo
ESR C
IF:
R3 C 4 ( Ro // R) C
1 Fc 2 ESR C 1 Fc
Ro
gm
Vc
Ao
+ -
Vref Rp
L 2 Ro Fc
R3
Loop Gain
C4
gm R o // R 2 Rp C 4
( g m Ro // R Ao) (1 + s ESR C ) (1 + s R 3 C 4 ) L (1 + s Ro // R C ) (1 + s ) (1 + s Rp C 4 Ao) Ro

57
Compensation Example
Objective: To compensate a LM2614 to get a stable system
R = 10 Load resistance C = 10 F Output capacitor ESR = 10 m ESR of output capacitor L = 10 H Inductor
The load pole = 1 = 4.8 kHz 2 ( R // Ro) C Ro = 80 kHz 2 L
The high frequency pole = The ESR zero =
Ro = 5 Small signal output resistance gm = 1 mho Transconductance of power stage Rp = ( R1 // R2) + 5 k R1,R2 are external feedback resistor dividers,5 kO is internal
1 = 1.6 MHz (high enough to ignore ) 2 ESR C
Rp = 33 k
Ao = 10000
Open loop gain of error amplifier
58
Compensation Example
We now need to choose the values of R3 and C4 to give a stable regulator response. If we set the zero frequency of R3 and C4 equal to the load pole frequency, and we choose a loop gain crossover frequency, Fc, much lower than the high frequency pole, then we can assume that the loop gain has a first order response. By choosing Fc = 30 kHz, the 80 kHz pole will contribute only 20 degrees of phase lag at Fc. This should give us a phase margin of about 90-tan-1(30/80) = 90-20 = 70 degrees.
C4 = gm ( Ro // R ) = 536 pF 680 pF 2 Fc Rp ( Ro // R ) C = 49 k 47 k C4
R3 =
This should give a stable regulator. Of course the real circuit should be checked under all conditions to ensure a stable system. This is only one of the methods to stabilize a regulator. Any other small signal methods that apply to feedback systems, will work here as well.
59
Compensation guidelines
Typically we like to choose a crossover frequency as high as possible. This gives a regulator with a fast transient response. However, if Fc is too close to the high frequency pole, of the power stage, the phase margin will be degraded. If we chose a Fc in the previous example of 75 kHz, then the phase margin would only be 47 degrees. Given the fact that these equations are only approximate, the phase margin of the real circuit will probably be smaller. This will give a ringy transient response. Lower crossover frequencies give a slower regulator, but tend to be more stable, and more on-the-safeside. The size of the output capacitor is also a compromise. Smaller gives more under/overshoot during a load transient and slightly higher output voltage ripple. However, with regulators that are internally compensated, smaller values of output capacitor will tend to increase Fc and therefore decrease phase margin. Large values of output capacitor will give small under/over-shoot and ripple, but are physically larger. Parts such as the LM2614, with external compensation, are much more flexible with regards to output capacitor value. In any case, it is always best to stay within the range given in the datasheet.
60
Line Transient Measurements

+15V
220pF(C) 10 F 50K 50K
1000 F
0.5 H (L)
Pulse Generator Output
LM12CL 30 10F
DUT
50
-15V
1000 F
Adjust L and C to minimise overshoots

600mV
30 s
61
Load Transient Measurements
Pulse Load
Constant Load
Function Generator Output 50
IRF 510
DUT
62
Layout guidelines
Electrical guidelines
component placement and length of traces width of traces curling of critical current loops routing of sensitive traces ground pins and ground plane voltage regulator placement on the system board
Mechanical guidelines
63
Critical current loops in a buck regulator

Ig
1
L + + C
Io
Vg
vs (t)
v(t)
Load
The critical current loops carry large currents with significant switching ripples
64
Component placement and length of traces
Loop 1 Loop 2
The two critical loops carry large switching currents and act as antennas that radiate switching noise Place C1, chip, L, and C2 as close as possible, to minimize the area of the two critical current loops
65
Routing of sensitive traces
Route noise sensitive traces, such as the voltage feedback path, away from the critical current loops with noisy traces between power components
66
Ground pins and ground plane

Connect the chip ground pins and the filter capacitor ground pins using a large component-side fill Connect this area to the ground plane using several vias This approach prevents large switching currents from circulating through the ground plane, and reduces ground bounce to the chip
67
Voltage regulator placement
sensitive analog/RF
Place switching regulator away from sensitive analog/RF subsystems
68
References and Acknowledgements
R.W.Erickson, D.Maksimovic, Fundamentals of Power Electronics, 2nd Edition, Kluwer Academic Publishers, 2000, ISBN 0-7923-7270-0 LM26XX Data Sheets, National Semiconductor Corporation
LM2608,LM2612,LM2614,LM2618,LM2619
Dragan Maksimovic, Associate Professor, ECE Dept, University of Colorado, Boulder, CO
69
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Buckconverters For Portable Application

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Buckconverters For Portable Application

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Magnetic Buck Converters for Portable Applications

Frank De Stasi Mathew Jacob

output DC power Po Vo I o = = = input DC power Pg Vg I g

Linear voltage regulator as power supply

Linear regulator power model

SMPS efficiency as a function of load

Example: Vg = 3.6 V Vo = 1.5 V 0 < Io < 300 mA

Buck (step-down) switching power converter

Vg DTs 0 DTs 1 2 D' Ts 0 Ts

fs = 1/Ts = switching frequency

D = switch duty cycle

Buck converter ideal static characteristic

switch duty cycle

Switch-Mode Power Supplies

Impact of efficiency: a system example

Total linear reg average Ig [mA] SMPS

Total SMPS average Ig [mA]

Example: Vg = 3.6 V Vo = 1.5 V 0 < Io < 300 mA

Advantages of using SMPS over Linear regulators

Buck regulators in the system

Buck SMPS regulators

P/DSP core I/O

Dynamic voltage regulation

Current limiting (overload protection)

Shut-down and operating-mode control

Adjustment of the output voltage using

Buck converter analysis

L + vL (t) + iC(t) R v(t)

L + vL(t) iC(t) R + v(t)

L + v L(t) iL(t) C iC(t) R v(t) +

L + vL(t) iC(t) R + v(t)

Inductor voltage and current waveforms

2003 National Semiconductor Corporation

Average voltage across the inductor equals zero

1 vL dt = D (Vg V ) + (1 D )(V ) = 0 Ts 0 V = DVg

Average inductor current equals the output current

Light-load operation: CCM and DCM

Inductor current reverses polarity at light loads

Implementing Zero-cross detect

CCM vs. DCM

Static characteristic in DCM

Determination of the inductor current ripple magnitude

(change in iL) = (slope)x(length of subinterval) Current ripple magnitude

Basic inductance selection eq.

2003 National Semiconductor Corporation

iC(t) Total charge q

Practice problem: selection of L and C

A 10H inductor is chosen in the datasheet

Output filter capacitor selection

Input current waveform

L + vL (t) iC(t) R + v(t)

Capacitor ripple currents

Irms Input Capacitor = IO

(Vg Vo) D r= L fs min IO

Irms Output Capacitor = IO

fs min = 468 kHz

Irms Input Capacitor = 204 mA

Irms Output Capacitor = 56 mA

Capacitors : How small can I go ?

Switch realization with a synchronous rectifier

NMOS: synchronous rectifier

Switch control signals

p n td1 td2 dead times