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Complementary MOS fabrication

CMOS Technology depends on using both N-Type and P-Type devices on the same chip. The two main technologies to do this task are: P-Well (Will discuss the process steps involved with this technology)
The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate.

N-Well
The substrate is P-Type. The N-channel device is built directly on the substrate, while the Pchannel device is built into a N-type well within the parent P-Type substrate.

Two more advanced technologies to do this task are:

Becoming more popular for sub-micron geometries where device performance and density must be pushed beyond the limits of the conventional p & n-well CMOS processes.

Twin Tub
Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.

Silicon-on-Insulator (SOI) CMOS Process

SOI allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate.
CMOS fabrication process overview

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P-well on N-substrate
Steps : N-type substrate Oxidation, and mask (MASK 1) to create P-well (4-5m deep) P-well doping
P-well acts as substrate for nMOS devices. The two areas are electrically isolated using thick field oxide (and often isolation implants [not shown here])
SiO2

P-well N-type substrate

CMOS fabrication process overview

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Polysilicon Gate Formation

Steps : Remove p-well definition oxide Grow thick field oxide Pattern (MASK 2) to expose nMOS and pMOS active regions Grow thin layer of SiO2 (~0.1m) gate oxide, over the entire chip surface Deposit polysilicon on top of gate oxide to form gate structure Pattern poly on gate oxide (MASK 3)

Thin gate oxide (SiO2)

Gate (patterned polysilicon on thin oxide)

Thick field oxide pMOS active region N-type substrate

nMOS active region

CMOS fabrication process overview

nMOS P+ Source/Drain difusion self-aligned to Poly gate

Implant P+ nMOS S/D regions (MASK 4)

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P+ implant/diffusion

P+ mask

Thick field oxide N-type substrate

CMOS fabrication process overview

pMOS N+ Source/Drain difusion self-aligned to Poly gate

Implant N+ pMOS S/D regions (MASK 5 often the inverse of MASK 4)

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N+ implant/diffusion N+ mask

P+ N-type substrate

N+

CMOS fabrication process overview

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pMOS N+ Source/Drain difusion, contact holes & metallisation

Oxide and pattern for contact holes (MASK 6) Deposit metal and pattern (MASK 7) Passivation oxide and pattern bonding pads (MASK 8) P-well acts as substrate for nMOS devices. Two separate substrates : requires two separate substrate connections Definition of substrate connection areas can be included in MASK 4/MASK5
Vin N+ for N-substrate contact) Vdd Vout Vss P+ (for P-substrate contact)

P P+
P channel Device

N+

N channel Device

N-type substrate
CMOS fabrication process overview

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CMOS N-well process

An N-well process is also widely used

Vin P+ for P-substrate Vss contact) Vout Vdd N+ (for Nsubstrate contact)

N+

N channel Device

P+

N-well
P channel Device

P-type substrate

CMOS fabrication process overview

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Composite layout and cross-section view of n-well CMOS device

(excludes passivation and patterning of wire-bonding pads)

CMOS fabrication process overview

Twin-Tub (Twin-Well) CMOS Process

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This technology provides the basis for separate optimization of the nMOS and pMOS transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. The Twin-Tub process is shown below.

In the conventional p & n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics. The twin-tub process avoids this problem.
CMOS fabrication process overview

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Silicon-on-Insulator (SOI) CMOS Process

Rather than using silicon as the substrate material, technologists have sought to use an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional p & n-well or twin-tub CMOS processes. A crosssection of nMOS and pMOS devices using SOI process is shown below.

The SOI CMOS process is considerably more costly than the standard p & n-well CMOS process. Yet the improvements of device performance and the absence of latch-up problems can justify its use, especially for deep-sub-micron devices.
CMOS fabrication process overview