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6.002 ELECTRONICS
R1
+ vOUT
v IN +
– –
v + R2 vOUT
R1
v IN +
– v − +
– A(v + − v − )
vOUT = A(v + − v − )
= Av +
v − vIN
= A OUT ⋅ R1 + vIN
R1 + R2
AR1 AR1vIN
= vOUT − + AvIN
R1 + R2 R1 + R2
AR1 R1
vOUT 1 − = v A 1 −
IN R + R
R1 + R2 1 2
1 − R1
R +R R2
vOUT = 1 2
⋅ Av IN = − vIN
− AR 1 R1
R1 + R2
6.002 Fall 2000 Lecture 21 3
Representing dynamics of op amp…
v+ +
vo
+ R v* +
– C – Av*
(v + − v − )
v− –
+
vo
–
R3 R4
vo
Circuit model R2 A
R1 +
v+ +
+ R v* +
– C – vo
v− (v + − v − ) –
–
R3 R4
A
dv* *
RC + v = v+ − v_
dt vo R1 +
v+ = = γ vo
RC dvo vo R1 + R2
+ = v+ − v_
vo R3
=−
A dt A −
v = γ vo
+ R3 + R4
= ( γ − −γ ) vo
neglect
dvo 1 A − +
or +
+ ( γ − γ ) vo = 0
dt RC RC
dvo A − +
+ ( γ − γ ) vo = 0
dt RC
time −1
dvo vo RC
or + = 0 where T = − +
dt T A( γ − γ )
vo ( 0 ) = 0
vo
unstable
K neutral
stable
t
disturbance
v+ + vo
v− –
− VS
vo
+ VS
v+ − v−
0
− VS
vo
+
−
v →0 v
t
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
e.g. R1 = R2
+
v = 7.5 vo = 15
vi VS = 15
vo = −15 v − = −7.5
vi –
vo
+ R2
+ vo R1
v = R1
R1 + R2
+ VS R1 e.g. R1 = R2
v = vo = +VS 15
R1 + R2 vi VS = 15
( vi = v − ) > v + v− < v+
v − > 7.5 v − < −7.5
− VS R1
vo = −VS − 15 v − =
R1 + R2
hysteresis
vi
− 7 .5 0 7 .5
Demo − VS
− 15
Demo
6.002 Fall 2000 Lecture 21 11
Without hysteresis
vi analog
vo to digital
vi
7.5
t
− 7.5
vC
–
vo
C + R1
vo
R1
2
vo
VS
VS v+
2 v−
vC
−
t
v
VS
−
2 v+
− VS
Assume vo = VS at t = 0
Demo vC = 0
6.002 Fall 2000 Lecture 21 13
Clocks in Digital Systems
We built an oscillator using an op amp.
t
can use as a clock
clock
a 1,1,0?
b When is the signal valid?
common timebase -- when to “look” at a signal
(e.g. whenever the clock is high)
Æ Discretization of time
one bit of information associated with
an interval of time (cycle)
6.002 Fall 2000 Lecture 21 14