3 Sept 15 Webcast Slides

How to Design Power Electronics
The HF in Power Semiconductor Modeling and Design
Innovations in EDA Webcast Series

September 3, 2015
Ingmar Kallfass
Institute of Robust Power Semiconductor Systems
University of Stuttgart
Outline
Semiconductor-Based Power Electronics
An Introduction
Challenges in Power Module Design
Power Module Design Flow
Modeling and Characterization
Electro-Thermal Co-Simulation
GaN Integration: Power Electronic
Circuits

03/09/15
2
SEMICONDUCTOR-BASED POWER ELECTRONICS

AN INTRODUCTION

03/09/15
3
Where Power Electronics meet Microwaves

Semiconductor Technologies
Scaling & Device Engineering
Compounds
Silicon
Power
IGBT
MOSFET
vs.
Performance
Maturity & Reliability
Cost
Compounds
SiC
MOSFET/IGBT
GaN HEMT
Share of Markets and Applications
GaAs/InP
HEMT/HBT
GaN HEMT
vs.
Silicon
MOSFET
SiGe HBT
Frequency
4
03/09/15
Power Electronics A Definition
Power Electronics is the extension of solid-state electronics away from

handling communications and data and into the business of efficiently
handling power, from milliwatts to gigawatts.
It makes the mobile phone battery last longer, it makes hybrid cars
practicable, and it helps make electrical generation and distribution
possible from sources ranging from a solar cell on your roof to a nuclear
reactor in mainland Europe.
[BIS]

03/09/15
5
Power Electronics A Definition
Power Electronics is (...) an enabling technology that often determines the

performance of, and provides the competitive advantage for, much more
expensive devices or systems. For example, choosing a mobile phone or
lap-top computer for its battery life is actually a Power Electronics decision,
with the battery performance itself just one part of that.
The importance of Power Electronics to the economy is consequently very
much greater than its direct market value.
Power Electronics is rarely seen as an end product by the general public,

but it does play a critical role in almost all aspects of our daily lives.
[BIS]

03/09/15
6
Applications and Technologies
Source: GaN-on-Si power transistors from French lab Leti, CEA-Leti

http://www.electronicsweekly.com/news/design/power/gan-on-si-power-transistors-french-lab-leti-2015-07/
03/09/15
7
Power Semiconductor Figures of Merit

Johnson FOM
describes the capability of power handling at
high frequencies
Baliga FOM
describes the capability of minimizing on-state
power loss in a transistor switch, i.e. loss due to
current flow through on-resistance

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8
Power Semiconductor Figures of Merit

Switching loss power as function of transistor area (simplified)
Minimum switching loss
Semiconductor-related loss term (= FOM)

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9
FOM Power Semiconductors
[Catrene]
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10
SEMICONDUCTOR-BASED POWER ELECTRONICS

CHALLENGES IN POWER MODULE DESIGN

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11
efficiency [%]
Power Conversion:
Small and Light, but also Efficient, Robust and EM Compatible
power density [W/cm3]

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12
ECPE* Technology Roadmap

Requirement
Key Performance
Indicator
Goal: Improvement by
2020 by a factor of
size
power density
[kW/l]
2-3
weight
power-to-mass ratio
[kW/kg]
efficiency
efficiency
[%]
cost
relative cost
[kW/]
2-3
robustness
failure rate
[1/h]
60 W
DC-DC PSiP
24 W/cm3
65 W
[golem.de]
*European Center for Power Electronics
03/09/15
13
Design Measures in Switched-Mode Converters

Control
Reduction of
Filters (Passives)
Related entities
Transistor Power Switches
Measures
Size, weight of passives
high fsw
Transistor switching loss
small FOM = RonQsw

high d/dt slopes
Parasitic LC resonance
(gate and power loops)
compact layout & high

integration density
Cooling effort
high temp. operation

of wide-bandgap SC
EMC shielding/filtering
EMC-oriented design

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14
Tradeoffs
fsw
d/dt
high T operation
integration
density
size
weight
efficiency
cost
robustness
EMC
Optimum design requires an RF-refined design flow

from device characterization and modeling
to multi-domain circuit analysis
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15
Multi-Domain Modeling & Design

Characterization
IV
CV
QV
vs Temperature
LF dispersion
Thermal impedance
Design
Modeling
Transistor
Package
DBC, PCB
time and
frequency domain
analysis
static
dynamic
thermal
electro-magnetic
simulation
B1506A
Cth,J
Cth,HS
Rth,HS Rth,JC
Modeling
electro-thermal
co-simulation

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16
POWER MODULE DESIGN FLOW

MODELING AND CHARACTERIZATION
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17
Refining a (Transistor-)Switch Model
NQS
2 dim. f(V) LF dispersion
1 dim. f(V)
Ron
Caps
Ids/gm
gate IV (HEMT)
bulk IV (MOSFET)
electrothermal
overtly simplistic
RF
parasitics
(package)
high fidelity

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18
Dynamic IV for Switching of Inductive Loads

VDS
Id
3
ID
IdMAX
Vin
VG
Vds
PLOSS
VG
VPlateau
tcross ON
tON
tcross OFF
Gate charge is required for the

calculation of switching loss
and efficiency
03/09/15
19
Dynamic IV for Switching of Inductive Loads
Dynamic IV in a FET transistor switch transits from sub-threshold to saturation to linear regime
03/09/15
20
Conventional Capacitance Measurement

100000
DUT: SiC MOSFET

600V, 100m, 35A
Capacitance (pF)
10000
B1506A
Ciss
Coss
Crss
1000
measurement conditions
as defined in datasheets
100
10
Vgs = 0 V
Vds = 0 to 500 V
f = 100 kHz
1
0
50 100 150 200 250 300 350 400 450 500

Vds (V)
Q derived from capacitance:

03/09/15
21
Capacitance Trace for Inductive Load Switching

datasheet
application
Cgs [fF/0.1mm]
Cgd [fF/0.1mm]
GaAs 0.15m RF power pHEMT

03/09/15
22
Qg Measurement
B1506A
18
Qg HC
16
Qg HV
14
DUT: Si MOSFET
100V, 11m, 200A
Vgs (V)
12
10
8
6
4
2
JESD24-2 standard
0
0
200
400
Qg (nC)
600
Measurement setup:
Ig = 5mA
HC meas:
Vdsoff=60V
Idson=10A
HV meas:
Vdsoff = 100V
800
Capacitance derived from Q:

03/09/15
23
Traps in GaN Devices

well known from RF devices
drain-lag/gate-lag
LF dispersion
dynamic Ron
after OFF-to-ON switching,
Ron remains high for a period
of time
trapping time constants from
ns to ms or even longer
(continuous exposure)
[Catrene]
03/09/15
24
Dynamic Ron Measurement
Vds, Id
3
1
Vstress
Id
3
Meas
Meas
2
2
Vds
Quiescent
Vstress
Vlow
Von
t
tstress
tdelay1
total delay
Vds_Pulse
Vgs_Pulse
Vds pulse width
Vgs pulse width
T_delay1 for safety. Minimun value depends

on slew rate of drain SMU
Very short total_delay necessary for
measuring dynamic effects
t
Vds pulse delay
Vgs pulse delay

03/09/15
25
Trapping Effects in GaN devices

Effect of Vstress in Output Characteristics
25
DUT: 600V GaN-on-Si

20
trapping states in
the off-state affect
Ron in the on-state
Id (A)
15
Measurement Setup
10
V_Stress = 50V
VdsPulse_Delay = 1us
VdsPulse_width = 10us
VgsPulse_Delay = 1.6us
VgsPulse_Width = 8us
Period = 2ms
NOS = 1
V_Stress = 100V
5
V_Stress = 150V
V_Stress = 200V
0
10
15
Vds (V)
03/09/15
26
Ron vs. Time

0.9
Vstress = 200V
0.8
Measurement Setup
0.7
Ron ()
DUT: 600V GaN-on-Si

0.6
0.5
0.4
0.3
0.2
0.E+00
SMU slew rate

delay
stable voltages
1.E-06
Vstress = 20V
2.E-06
3.E-06
Time (seconds)
4.E-06
VdsPulse_Width = 10us
Period = 2ms
NOS = 1
Resolution=200ns
5.E-06

03/09/15
27
Benchmarking Different GaN Devices

35
30
Measurement setup
Id (A)
25
20
15
Device A
10
Device B
5
Device C
Same voltage conditions

VdsPulse_Width = 10us
Period = 2ms
NOS = 1
comparable
devices from
different
manufacturers
4
Vds (V)
8
03/09/15
28
Ron Temperature Dependence

B1506A w/ heat plate
0.3
T=23C
0.25
T=100C
T=150C
Ron ()
0.2
0.15
Measurement Setup
0.1
DUT:
SiC MOSFET
600V / 100m / 35A
0.05
Vgs=10V
Vgs=10V
GatePulse_Delay=100us
GatePulse_Width=100us
DrainPulse_Delay=0us
DrainPUlse_Width=200us
PulsePeriod=50ms
0
0
20
40
Ids (A)
60
80

03/09/15
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Model Requirements
2D Capacitance Model
LF Dispersion Model
Thermal Model

03/09/15
30

ELECTRO-THERMAL CO-SIMULATION
03/09/15
31
SiC MOSFET Multi-Chip

Power Module
AlN DBC with half- and full-bridge
bare-die SiC MOSFETs
driver ICs
bootstrap supply
buffer caps
fsw > 100 kHz

power up to 10 kW
Reliability: 10C simulated T from Tj to Theatsink

03/09/15
32
Electro-Thermal Co-Simulation
Operating the Full-Bridge Module as a DC-AC Inverter
03/09/15
Alternating output voltage

VP = 340 V
fsw = 100 kHz
Alternating output current

IP = 11 A
Alternating output power
HB1
HB2
Temperature transients
Rth heatsink: 0.917 K/W

33
Fullbridge Module Transient Simulation

03/09/15
Observations
The temperature in the SiC MOSFETs pulsates with 60 Hz
Temperature difference about 5 C
Temperature peaking is only visible in the junction layer
Time constants of the materials are high enough

34
Electro-thermal Co-Simulation
03/09/15
Mold mass 1 mm
Bond-hor.
Bond-vert. 0.5 mm
Al-Top 0.04 mm
SiC 0.4 mm
Solder 0.1 mm
Cu (DBC) 0.3 mm
Ceramic (DBC) 0.63 mm
M2
M1
Cu (DBC) 0.3 mm
Heatsink 2mm
New degrees of freedom

Thermal equivalent circuit extraction (thermal impedance)
Optimized compact layout of modules (hybrid, multi-chip, on-chip)
Reduction of safety margins (de-rating)
Robustness-oriented design
Lifetime prediction (coupling to thermo-mechanical co-simulation)
35

GAN INTEGRATION
03/09/15
36
AlGaN/GaN HEMTs...
600V E-(GI)HEMT
can be tailored for power (Baliga FOM, RonQg,

Vbd) and microwave applications (Johnson FOM,
fmax, Vbd)
show best RonQg compared to Si and SiC
600V E-mode
Si/GaN cascode
can be cost-efficient when on Si-substrate
650V E-HEMT
are today less mature (traps -> reliability, dynamic

Ron, ...)
600V E-HEMT
as lateral devices are amenable to monolithic

functional integration
are intrinsic depletion-mode / normally-on

devices, normally-off are more complex (pdoping, Si-GaN cascode, ...)
have limited input dynamic range due to Schottky
gate (except MISFET)
600V D-HEMT
03/09/15
37
GaN Driver Integration: Motivation

VGS
conventional hybrid assembly

shoot-through
currents
over-shoot
& oscillations
t
Robustness:
normally-off
default
behaviour
Quasi normally-off
GaN driver
Switching
Speed:
reduction of gate
loop inductance
(Monolithic) Integration of
Gate driver & power transistor
03/09/15
38
Normally-On
GaN-on-Si HFET
Quasi-Normally-Off
GaN-on-Si HFET
Mnch et.al.
ISPSD 2015
VGS = 0V
ID
VDS
ID
2.9
0 1.1 V
VGS

03/09/15
39
Boost Converter
switching
node
VIN
GaN gate
driver
Mnch et.al.
ISPSD 2015
VOUT
GaN 600 V
HFET
No shoot-through currents
VG++
robust
Default: pull-down
VG-
Monolithic integration
power transistor off
Hybrid integration

03/09/15
40
Hybrid GaN Power Module
Mnch et.al.
ISPSD 2015
Q1: GaN Power HEMT

100 mm, 24 A, 600 V
D: GaN Schottky diode
50 mm, 12 A, 600 V
QPD: GaN HEMT
10 mm, 2.4 A, 600 V
QPU: GaN HEMT

10 mm, 2.4 A, 600 V
4x GaN diode, <100V, 10 mm

03/09/15
41
Turn-On and Turn-Off Transitions

Turn-on
Mnch et.al.
ISPSD 2015
tf,DS > 1.6 ns

dV/dtMAX 91 V /ns
tr,GS 5.4 ns
no overshoot
no oscillation
fast switching
Turn-off
tr,DS > 1.2 ns
dV/dtMAX 177 V /ns
tf,GS 3.8 ns
fast switching
03/09/15
42
Monolithic Integration: Gate Driver & Power

Transistor
Monolithic combination of
transistors with different
voltage ratings
Power transistor 600 V / 24 A
Pull-up driver <100 V / 2.4 A
Pull-down driver <100V / -1.2 A
3 x 2 mm2
Parasitic gate loop

inductance almost eliminated

03/09/15
43
CONCLUSION

03/09/15
44

03/09/15
45
Thank you for your attention

Ingmar Kallfass
University of Stuttgart
Institute of Robust Power Semiconductor Systems
Pfaffenwaldring 47
D 70569 Stuttgart
Tel.: +49 (0)711-685-68747
Fax: +49 (0)711-685-58747
E-Mail: ingmar.kallfass@ilh.uni-stuttgart.de
ILH is a member of
ILH was founded in the frame of

03/09/15
46
References
[Catrene] Integrated power & energy efficiency, Power device
technologies, simulations, assembly and circuit topographies enabling high
energy efficiency applications, Catrene Scientific Committee Working
Group Integrated power & energy efficiency,
http://www.catrene.org/web/downloads/IPEE_Report_by_Catrene%20Sci._
Comm.pdf
[BIS] UK Department for Business Innovation and Skills, Power electronics: A
strategy for success, 2011.
[ECPE] [Online] http://www.ecpe.org/

03/09/15
47
Question and Answer Session
Resources
Power Electronics Applications Page

keysight.com/find/power-electronics
includes our Quick Start guide:
Video clip: How to design DC-DC convertors

keysight.com/find/eesof-how-to-dc-dc

03/09/15
48

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3 Sept 15 Webcast Slides

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How to Design Power Electronics

The HF in Power Semiconductor Modeling and Design

Innovations in EDA Webcast Series

Innovations in EDA Webcast Series

SEMICONDUCTOR-BASED POWER ELECTRONICS

Innovations in EDA Webcast Series

Where Power Electronics meet Microwaves

Share of Markets and Applications

Power Electronics A Definition

Power Electronics is the extension of solid-state electronics away from

Innovations in EDA Webcast Series

Power Electronics A Definition

Power Electronics is (...) an enabling technology that often determines the

Power Electronics is rarely seen as an end product by the general public,

Innovations in EDA Webcast Series

Applications and Technologies

Source: GaN-on-Si power transistors from French lab Leti, CEA-Leti

Power Semiconductor Figures of Merit

Innovations in EDA Webcast Series

Power Semiconductor Figures of Merit

Minimum switching loss

Semiconductor-related loss term (= FOM)

Innovations in EDA Webcast Series

FOM Power Semiconductors

SEMICONDUCTOR-BASED POWER ELECTRONICS

Innovations in EDA Webcast Series

power density [W/cm3]

Innovations in EDA Webcast Series

ECPE* Technology Roadmap

Design Measures in Switched-Mode Converters

Transistor Power Switches

Size, weight of passives

Transistor switching loss

small FOM = RonQsw

compact layout & high

high temp. operation

Innovations in EDA Webcast Series

Optimum design requires an RF-refined design flow

Multi-Domain Modeling & Design

Innovations in EDA Webcast Series

POWER MODULE DESIGN FLOW

Refining a (Transistor-)Switch Model

Innovations in EDA Webcast Series

Dynamic IV for Switching of Inductive Loads

Gate charge is required for the

Dynamic IV for Switching of Inductive Loads

Conventional Capacitance Measurement

DUT: SiC MOSFET

50 100 150 200 250 300 350 400 450 500

Q derived from capacitance:

Capacitance Trace for Inductive Load Switching

GaAs 0.15m RF power pHEMT

Innovations in EDA Webcast Series

Capacitance derived from Q:

Traps in GaN Devices

Dynamic Ron Measurement

Vds pulse width

Vgs pulse width

T_delay1 for safety. Minimun value depends

Innovations in EDA Webcast Series

Trapping Effects in GaN devices

DUT: 600V GaN-on-Si

Ron vs. Time

DUT: 600V GaN-on-Si