Lecture 3:

CMOS
Transistor
Theory

Outline
q
q
q
q
q

Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

Introduction
q So far, we have treated transistors as ideal switches
q An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
q Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

MOS Capacitor
q Gate and body form MOS
capacitor
V <0
q Operating modes
+
Accumulation
Depletion
(a)
Inversion
0<V <V
g

polysilicon gate
silicon dioxide insulator
p-type body

+
-

depletion region

(b)

Vg > Vt
+
-

inversion region
depletion region

(c)

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

Terminal Voltages
Vg
q Mode of operation depends on Vg, Vd, Vs
+
+
Vgs = Vg Vs
Vgs
Vgd
Vgd = Vg Vd
Vs
Vd
Vds = Vd Vs = Vgs - Vgd
+
Vds
q Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
q nMOS body is grounded. First assume source is 0 too.
q Three regions of operation
Cutoff
Linear
Saturation
3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

nMOS Cutoff
q No channel
q Ids 0
Vgs = 0

+
-

+
-

Vgd

n+

n+
p-type body
b

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

nMOS Linear
q Channel forms
q Current flows from d to s
V
e from s to d
q Ids increases with Vds
q Similar to linear resistor

gs

> Vt

+
-

+
-

Vgd = Vgs

n+

Vds = 0

n+
p-type body
b

Vgs > Vt

+
-

+
d

n+

n+

Vgs > Vgd > Vt

Ids
0 < Vds < Vgs-Vt

p-type body
b

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

nMOS Saturation
q
q
q
q

Channel pinches off

Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt

+
-

+
-

Vgd < Vt

d Ids

n+

n+

Vds > Vgs-Vt

p-type body
b

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

I-V Characteristics
q In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversions
Gate oxide channel
q Qchannel = CV
q C = Cg = oxWL/tox = CoxWL
Cox = ox / tox
q V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

10

Carrier velocity
q Charge is carried by eq Electrons are propelled by the lateral electric field
between source and drain
E = Vds/L
q Carrier velocity v proportional to lateral E-field
v = E
called mobility
q Time for carrier to cross channel:
t = L / v

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

11

nMOS Linear I-V

q Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

Qchannel
I ds =
t
W
= Cox
L

V V Vds
gs t
2

V
= Vgs Vt ds Vds
2

3: CMOS Transistor Theory

V
ds

CMOS VLSI Design 4th Ed.

W
= Cox
L
12

nMOS Saturation I-V

q If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
q Now drain voltage no longer increases current

V
I ds = Vgs Vt dsat
2

V
(
2

gs

Vt )

3: CMOS Transistor Theory

V
dsat

CMOS VLSI Design 4th Ed.

13

nMOS I-V Summary

q Shockley 1st order transistor models

Vds
I ds = Vgs Vt
2

Vgs Vt )
(

2
3: CMOS Transistor Theory

Vgs < Vt
V V < V
ds
ds
dsat

Vds > Vdsat

CMOS VLSI Design 4th Ed.

cutoff
linear
saturation

14

Example
q We will be using a 0.6 m process for your project
From AMI Semiconductor
tox = 100
2.5
V =5
2
= 350 cm /V*s
2
Vt = 0.7 V
1.5
V =4
q Plot Ids vs. Vds
1
V =3
Vgs = 0, 1, 2, 3, 4, 5
0.5
V =2
Use W/L = 4/2

V =1
Ids (mA)

gs

gs

gs

gs

3.9 8.85 1014 W

W
= Cox = (350 )

8
L
100 10
L
3: CMOS Transistor Theory

gs

=
120
A/V 2

CMOS VLSI Design 4th Ed.

Vds

15

pMOS I-V
q All dopings and voltages are inverted for pMOS
Source is the more positive terminal
q Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/Vs in AMI 0.6 m process
q Thus pMOS must be wider to
provide same current
In this class, assume

n / p = 2
0

Vgs = -1

Vgs = -2

Ids (mA)

-0.2

Vgs = -3

-0.4

Vgs = -4

-0.6

-0.8
-5

Vgs = -5

-4

-3

-2

-1

Vds

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

16

Capacitance
q Any two conductors separated by an insulator have
capacitance
q Gate to channel capacitor is very important
Creates channel charge necessary for operation
q Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

17

Gate Capacitance
q Approximate channel as connected to source
q Cgs = oxWL/tox = CoxWL = CpermicronW
q Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.90)

p-type body
3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

18

Diffusion Capacitance
q Csb, Cdb
q Undesirable, called parasitic capacitance
q Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process

3: CMOS Transistor Theory

CMOS VLSI Design 4th Ed.

19