Development and Supply of COTS Module based Ku band RF seeker

Portable test Simulator

1.Objective:

Ku band RF seeker development work is going on in DRSS Directorate of RCI and the same seeker
will be utilized in QRSAM missile for homing guidance. Portable Test Simulator will be used for
test and evaluation of RF seeker at RF frequencies at different test centers i.e. During
Environmental Test, EMI /EMC Test and Bench Test of seeker. This simulator will generate target
echo signal in RF frequency with closing range and target relative velocity. This will also facilitate
target angle simulation to validate angle tracking of target.

2. Scope of Work:

Based on RCI design vendor has to realize the test simulator system and supply to RCI.

 The primary Scope of work for the vendor is Test Simulator H/W development based on System
block diagram & proven schematic of RCI.
 Mechanical housing design and fabrication as per RCI requirements.
 Integration and Packaging.

User Responsibility:

(a) Should Provide Block Level and Schematic level design to Vendor
(b) Mechanical Dimension and packaging requirements
Vendor Responsibility:

(a) Realization of the system based on RCI design

 Procurement of components and development boards
 PCB design
 Electrical Integration
(b) Mechanical housing design and Packaging of the system
(c) Board Support Software package design
(d) Minor design modification (up to 10%) as per user requirements
(e) PDR document
(f) Acceptance document
3. Technical Description and Specifications:

COTS based Seeker test simulator will able to generate target echo in RF frequency for Closing
range, variable target velocity , angle channel simulation along with closing range simulation.
Figure 1 showing the test system configuration.
A Xilinx Virtex7 based high end board will act as main processing block where a high speed 04
channel DAC card (4DSP make 1.2 Gsps ) will be interfaced with a high density edge connector
to the FPGA card.
A rugged laptop computer will act as system controller which will establish Ethernet and RS232
communication with the FPGA board. A DDC make real time 1553B card will be interfaced
with system controller. Through this 1553B communication real time seeker data will be logged
in system controller.
Seeker reference clock (60MHz) will be taken as system clock and FPGA and DAC card clock
will be derived from this. IF signal of 75MHz will be generated inside FPGA using Direct
Digital Synthesis technique after adding necessary Doppler and Phase shift will be made analog
using 4 channel DAC. Sum, Delta Azimuth and Delta Elevation return echo will be generated in
IF frequency using the DAC. Further IF signal will be up converted to Ku band with a LO signal
available from seeker . Ku band signal will be further pulse modulated and followed by
attenuation based on radar range equation.
These echo signal for Sum, Azimuth and Elevation will be fed to the seeker either injection
mode or radiated mode. Based on this signal the seeker detection, tracking performance will be
evaluated.
 Figure 1: Block diagram of Test simulator system

Sum channel will be processed for Doppler detection and tracking . Difference channel (azimuth
and Elevation) will be process for the angular information of the target.
A graphic user interface will be generated for real time display of measured data.

Specifications:

1. Number of RF channel : 3 Ku Band

2. IF frequency Range : 30 to 125MHz
3. Attenuation per channel(Digital Control): 90dB with a step size of 0.5 dB
4. 1553B Communication with Seeker: Dual redundant with real time operation
5. System controller to FPGA card communication via RS232 and 10/100 Ethernet
6. Dynamic range of Signal : > 60dB
7. Mechanical Dimension: To be decided jointly with Vendor
8. Operating Voltage : 230V AC , 02 Amp
 Major Bill of Materials:

As per serial number listed in block diagram:

1. Xilinx Virtex7 Evaluation Board (Part No: XC7VX485T2FFG1761CFP4) ,Qty:1 no
2. 4DSP DAC Card ( Part no. FMC204) , Qty 1 no
3. System Controller (Rugged Laptop with high configuration), Qty 1 no.
4. DDC Real Time 1553 Card(Part no: BU-67119W200R-JL0), Qty 1 no.
5. Ku Band UP converter : Specs will be provided , Qty 3no.
6. Pulse Modulator : Specs will be provided Qty 03 nos
7. Digital Variable Attenuator (single or dual) : Specs will be provided ,Qty 03 nos.
8. LO amplifier : Specs will be provided, Qty 1no
9. Power Divider 3 way: specs will be provided, Qty. 01 no
10. Assorted Connectors and Cables
11. 230VAC to DC power module
12. Mechanical Housing

Delivery Time:
20 weeks from the date of supply order:

Deliverables:

1. Portable Test Simulator System: Qty 02 nos with mechanical housing and necessary
interface connectors
 SMA Cable (Male to Male) up to 18 GHz.(Length 0.5mtr.) – 6Nos.
 SMA Cable (Male to Male) up to 18 GHz.(Length 1.0mtr.) – 6Nos.
 SMA(Male) to BNC(F) Adaptors – 6Nos.
2. Board Support package S/W in a CD
3. PCB Design File in a CD
4. Unit Test Report

Terms and Conditions

The following terms and conditions are applicable to all vendors.

1. Vendor should demonstrate Bench Level H/W functionality to RCI Rep.
2. Should provide post delivery technical support to RCI for a period of 1 year to sort out the
board level problem found during integration.

3. Vendor should have working experience with Xilinx Virtex-5 and above devices in digital
system design. Necessary documentary evidence should furnish with technical bid in support
of above experiences else the vendor will not be considered for technical evaluation and will
be rejected.
4. Vendors should have necessary infrastructure and test equipments at their place. RCI/user
will not provide any equipments.
5. Stage wise progress monitoring will be done at vendors place by user representative.
6. Vendor should provide COC certificate for all BOM materials from the OEM

Mile Stone:

T0 - Supply Order
T1 = (T0 + 2 weeks) - Completion of PDR and Schematic design
T2 = (T1 + 10 Weeks) – PCB Design, Fabrication, Procurement of components and
Mechanical Housing Design
T3 = (T2 + 6Weeks) – Integration of 1st and 2nd Unit, S/W development and GUI
Development
Delivery = (T3 + 4 Weeks) – Acceptance Test, Packaging and delivery of store.
Testing:

 The block diagram of test set up is given below for testing the Test Simulator.
 Clock and PRF are fed from Function generator and LO signal is fed from RF
Synthesizer
 through RF cables (SMA to SMA).
 Doppler (Velocity) is generated digitally and added with transmitting frequency.
 Pulse Modulated out puts i.e. Sum, Az., El. Ports are monitored in Spectrum Analyzer.
 0-90 db digitally controlled attenuators are used in the simulator to simulate target return as per
1/R4 law.
 The attenuated output readings are monitored in 20 steps over the full range of attenuation (0 –
90dB).
 All the test parameters for 3 channels are noted down in the test slip.

Note:” Vendor is required to produce COC at the time of delivery”