ECE 658 VLSI Design - I Homework-1 Due Date: Sept.

15, 16

Dr. D. Misra
No collaboration is permitted on this assignment. Your work must be your own. Submit a
PDF file in moodle.

Question 1.
Sketch the transistor-level schematics for a CMOS 4-input NOR gate and a CMOS 4-input NAND
gate. Also, provide a stick diagram for each gate. Be sure your stick diagram differentiates between
layers (metal, active, and poly) and indicates the different active regions (N+ and P-). See the
lecture notes for an example. Computer generated figures are preferred but hand-drawn figures
will be acceptable.

Question 2.

For each of the output functions below design a CMOS gate to implement the logic. Provide both
a schematic and stick diagram for each. Draw the transistor- level schematic. Be sure your stick
diagram differentiates between layers (metal, active, and poly) and indicates the different active
regions (N+ and P-). See the lecture notes for an example. Computer generated figures are
preferred but hand-drawn figures will be acceptable. Also, provide a gate-level design.

F = (A+B) . C

F = (A+B) . (C+D)

Question 3.
Figure below shows the stick diagram of a 2-input NAND gate. Sketch the side view (cross-
section) of the gate from X to X’ and Z to Z’

Z’