Computer Science and Engineering

Department

Digital IC and VLSI Design (ACOE419)

Assignment

Question 1: Design one of the following 6-input NAND implementations in a

transistor-level schematic according to your last name initial as shown:
(a) A-E
(b) F-I
(c) J-M
(d) N-Z

The transistor size ratio k, should be for the nMOS transistors equal to the last digit of
your registration number and for the pMOS equal to the first digit of your registration
number. If either is zero, pick the digit next to it.

Deadline: 07/01/2021
Insert schematic here…

Question 2: Simulate your circuit and measure the circuit delay using ALS

Delay =

Insert ALS simulation waveform here…

Question 3: Simulate your circuit and measure the circuit delay using Spice

Delay =
Insert SPICE simulation waveform here…