Department of

Computer Science and Engineering

Digital Integrated Circuits and VLSI Design (ACOE419)

Experiment #2

Compound Gates

Student’s Name:
Semester: Date:

Assessment:
Assessment Point Weight Grade
Methodology
Presentation and discussion of results
Participation
Assessment Points’ Grade

Comments:
 Digital Integrated Circuits and VLSI Design Lab1- ACOE419

Experiment #2: Compound Gates

Objectives:
The objective of this experiment is to show students how to use the Electric VLSI system to
design more complex circuits such as compound gates.

Procedure: Use the Electric VLSI system available at

http://www.
Exercise 1:
a) Launch the Electric environment and create a new cell, by using the Cell menu => new
cell. Select “schematic” in the components view.
b) Enter the schematic of a CMOS compound gate implementing the logic function
.

Figure 1.

c) Select “Tools => DRC => Check Hierarchically”. If there are error messages, find the
errors in the schematic.

d) Verify the schematic using the ALS simulator

1
 Digital Integrated Circuits and VLSI Design Lab1- ACOE419

Questions
1. How many transistors were used for implementing the circuit?

2. How much was the delay of the compound gate? Was it equal for all inputs?

If A, B, C is 1 and D is 0 then the delay is 40ns

If A, B, C is 1 and D is 1 then the delay is 10ns