Computer Science and Engineering

Department

Konstantinos Christofi 12688

Digital IC and VLSI Design (ACOE419)

Assignment

Question 1: Design one of the following 6-input NAND implementations in a

transistor-level schematic according to your last name initial as shown:
(a) A-E
(b) F-I
(c) J-M
(d) N-Z

The transistor size ratio k, should be for the nMOS transistors equal to the last digit of
your registration number and for the pMOS equal to the first digit of your registration
number. If either is zero, pick the digit next to it.

Deadline: 07/01/2021
Question 2: Simulate your circuit and measure the circuit delay using ALS

Delay = 80ns-20ns=60ns

Question 3: Simulate your circuit and measure the circuit delay using Spice

Delay = 10.5ns-10ns=0.5ns
*** SPICE deck for cell final{sch} from library noname
*** Created on Tue Jan 12, 2021 15:37:37
*** Last revised on Tue Jan 12, 2021 15:49:14
*** Written on Tue Jan 12, 2021 15:51:57 by Electric VLSI Design System, version
9.07
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
*CMOS/BULK-NWELL (PRELIMINARY PARAMETERS)

.MODEL N NMOS LEVEL=1

+KP=60E-6 VTO=0.7 GAMMA=0.3 LAMBDA=0.05 PHI=0.6
+LD=0.04E-6 TOX=40E-9 CGSO=2.0E-10 CGDO=2.0E-10 CJ=.2e-6
.MODEL P PMOS LEVEL=1
+KP=20E-6 VTO=0.7 GAMMA=0.4 LAMBDA=0.05 PHI=0.6
+LD=0.06E-6 TOX=40E-9 CGSO=3.0E-10 CGDO=3.0E-10 CJ=.2e-6
.MODEL DIFFCAP D CJO=.2e-6

.global gnd vdd

Vdd Vdd Gnd 5
Vin A gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin1 B gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin2 C gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin3 D gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin4 E gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin5 F gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0
Vin6 Y gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0

*** TOP LEVEL CELL: final{sch}

Mnmos@0 net@48 B net@47 gnd N L=0.4U W=3.2U
Mnmos@1 net@47 C net@46 gnd N L=0.4U W=3.2U
Mnmos@2 net@49 F net@50 gnd N L=0.4U W=3.2U
Mnmos@3 net@50 E gnd gnd N L=0.4U W=3.2U
Mnmos@4 Y A net@48 gnd N L=0.4U W=3.2U
Mnmos@5 net@46 D net@49 gnd N L=0.4U W=3.2U
Mpmos@0 vdd A Y vdd P L=0.4U W=0.4U
Mpmos@1 vdd B Y vdd P L=0.4U W=0.4U
Mpmos@3 vdd C Y vdd P L=0.4U W=0.4U
Mpmos@4 vdd D Y vdd P L=0.4U W=0.4U
Mpmos@5 vdd F Y vdd P L=0.4U W=0.4U
Mpmos@6 vdd E Y vdd P L=0.4U W=0.4U
***********************************************************************
* Stimulus
***********************************************************************
.tran 1ps 80ns
.PLOT DC V(A) V(y)
.measure tpdr
* rising prop delay
+ TRIG v(a) VAL=5/2 FALL=1
+ TARG v(y) VAL=5/2 RISE=1
.measure tpdf
* falling prop delay
+ TRIG v(a) VAL=5/2 RISE=1
+ TARG v(y) VAL=5/2 FALL=1
.measure tpd param= (tpdr+tpdf)/2
* average prop delay
.measure trise
* rise time
+ TRIG v(y) VAL=0.2*5 RISE=1
+ TARG v(y) VAL=0.8*5 RISE=1
.measure tfall
* fall time
+ TRIG v(y) VAL=0.8*5 FALL=1
+ TARG v(y) VAL=0.2*5 FALL=1

.END