LABORATORY EXERCISE 3

CMOS NOR and NAND Gates

Objectives
• To construct the circuit-level implementation of NOR and NAND gates
• To simulate the dynamic behavior of NOR and NAND gates
• To describe the dynamic characteristics of NOR and NAND gates using delay-time
parameters
• To understand how the NOR and NAND gates delay-time parameters changes as the
transistor sizes are varied

Introduction
Combinational logic circuits or gates are the basic building blocks of all digital systems.
These gates perform Boolean operations on multiple variables and determine the outputs as
Boolean functions of the inputs. In this exercise, the basic principles used in the analysis of
the transient response of inverters will be applied to more complex logic circuits such as
NOR and NAND gates.

Procedure
1. Load Electric.

2. Open the library Exercise.

3. Create new facet NOR_sch in library Exercise with schematic as the facet view. Draw
the NOR schematic in Figure 3-a.
Note: Lp, Ln = 0.35µm; Wp = 3.2µm; Wn = 0.8µm

Figure 3-a. Schematic diagram of a NOR gate.

4. Save the NOR schematic.

5. Create an icon for the NOR_sch{sch}. Save the icon facet. Close the NOR_sch{ic}
and the NOR_sch{sch} design windows.

6. Create new facet NOR_sch_tst with schematic as the facet view.

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7. Click on Edit → New Facet Instance. Choose library Exercise. Select NOR_sch{ic}
from this library. Click on the design window.
Note: Lp, Ln = 0.35µm; Wp = 3.2µm; Wn = 0.8µm

8. Click on Export → Re-Export Everything. Add other necessary components for

simulation. Please refer to Figure 3-b. Save the schematic.

Figure 3-b. Schematic diagram for the transient analysis of a NOR gate.

Note: loadcap = 100fF

SPICE card for DC → DC 3.3
SPICE card for Input A → PULSE(0 3.3 0 1n 1n 100n 200n)
SPICE card for Input B → PULSE(0 3.3 50n 1n 1n 100n 200n)
SPICE card for Transient Analysis→ 5p 500n 0 5p

9. Create a SPICE netlist of your circuit. Simulate the circuit using WinSpice. Verify if
the circuit is working properly by referring to the truth table of a NOR gate (Table 3-a).

Va Vb Vout (NOR) Vout (NAND)

0 0 1 1
0 1 0 1
1 0 0 1
1 1 0 0

Table 3-a. NOR and NAND gate truth table.

10. Fill-up the table below. Round off your answers to two decimal places.

WN WP τPHL τPLH
0.80µm 3.20µm
0.80µm 1.60µm
0.80µm 0.80µm
Note: Refer to Exercise 2 for the determination of τPHL and τPLH.

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11. Repeat procedures 3 - 9 for a NAND gate (Figure 3-c and 3-d). Verify if the circuit is
working properly by referring to the truth table of a NAND gate (Table 3-a).
Note: Lp, Ln = 0.35µm; Wp = 3.2µm; Wn = 1.6µm

12. Fill-up the table below. Round off your answers to two decimal places.

WN WP τPHL τPLH
1.60µ 3.20µ
1.60µ 1.60µ
1.60µ 0.80µ
Note: Refer to Exercise 2 for the determination of the τPHL and τPLH.

Figure 3-c. Schematic diagram of a NAND gate.

Figure 3-d. Schematic diagram for the transient analysis of a NAND gate.

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