12

CMOS Layout Mask Layers

■ IC design procedure:
Layer Representation Color Convention (EECS 105)
• system specifications
• circuit design
• layout n-well purple

• post-layout extraction and simulation

• IC fabrication active green
• testing

select (p+) brown

■ Layout considerations:
• mask layers polysilicon red

• devices
• electrical connectivity (interconnect) metal blue
• layout (design) rules

contact black

EE 105 Fall 1998 EE 105 Fall 1998

Lecture 12 Lecture 12
 MOSFET Layout Electrical Connectivity

■ active, polysilicon, and metal can be used for interconnects (wires)

■ polysilicon crossing active results in an NMOS device:

L ■ metal has much lower resistivity than either active or polysilicon

gate

■ metal is separated from active or polysilicon by an (insulating) oxide; a contact

W
is needed for electrical connections between these layers

source / drain (symmetric)

■ PMOS devices are placed in n-wells:

■ active and polysilicon cannot be connected directly (without metal)

■ use p-doped active (select mask) as contact to the bulk

use n-doped active (no select mask) as a contact to n-wells

select

n-well contact to bulk contact to well

EE 105 Fall 1998 EE 105 Fall 1998

Lecture 12 Lecture 12
 Layout Rules (EECS 105 Technology) Layout Example

minimum dimensions and separations (in mm, not to scale):

n-well polysilicon
VDD VDD
4 1

5 1

18 20 µm
active metal

2 2

14 16
2 2
A F

select contact

10 12
2 1 B

2 1

8
6
active contact-to-
polysilicon

metal
poly
2

4
1

2
2 VSS VSS
polysilicon

0
active

3 1
1
0 2 4 6 8 10 12 14 16 18 20 µm
n-well

EE 105 Fall 1998 EE 105 Fall 1998

Lecture 12 Lecture 12
 Circuit Extraction Circuit Extraction
1) Find all transistors and sizes 1) Find all transistors and sizes

2) Extract wiring 2) Extract wiring

3) Calculate (parasitic) capacitance and resistance 3) Calculate (parasitic) capacitance and resistance

VDD VDD VDD VDD

10 12 14 16 18 20 µm

10 12 14 16 18 20 µm
A F A F

B B
8

8
6

6
4

4
2

2
VSS VSS VSS VSS
0

0
0 2 4 6 8 10 12 14 16 18 20 µm 0 2 4 6 8 10 12 14 16 18 20 µm

EE 105 Fall 1998 EE 105 Fall 1998

Lecture 12 Lecture 12
 Extracted Schematic Circuit Simulation

■ Objectives:
• fabricating an IC costs $1000 ... $100,000 per run
VDD
CA-DD CB-DD ---> nice to get it “right” the first time
(4.5/1)
A (4.5/1) • check results from hand-analysis
(e.g. validity of assumptions)
F
• evaluate functionality, speed, accuracy, ... of large circuit blocks or entire chips
Cw
B (3/1)
■ Simulators:
CB-SS
• SPICE: invented at UC Berkeley circa 1970-1975

A (3/1) commercial versions: HSPICE, PSPICE, I-SPICE, ... (same core as Berkeley
SPICE, but add functionality, improved user interface, ...)
CA-SS
EECS 105: student version of PSPICE on PC, limited to 10 transistors
VSS
• other simulators for higher speed, special needs (e.g. SPLICE, RSIM)

■ Wire capacitance Cw is found from its capacitance per unit length --

 ε ox  ■ Limitations:
C w =  -----------W w L w
 thox
t  • simulation results provide no insight (e.g. how to increase speed of circuit)
• results sometimes wrong (errors in input, effect not modeled in SPICE)
■ Interconnect capacitances CA-SS and CA-DD are the sum of polysilicon and metal ===> always do hand-analysis first and COMPARE RESULTS
capacitances to the substrate (connected to VSS ) or the well (connected to VDD)
■ Could add resistances of polysilicon and metal interconnects

EE 105 Fall 1998 EE 105 Fall 1998

Lecture 12 Lecture 12