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Acer Aspire One AO532H - D260 COMPAL LA-5651P NAV70 - REV 2.0 PDF
Acer Aspire One AO532H - D260 COMPAL LA-5651P NAV70 - REV 2.0 PDF
1 1
Compal Confidential
2 2
3
2010-04-29 3
REV: 2.0
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 1 of 32
A B C D E
A B C D E
Clock Generator
Compal Confidential CK505 page 8
RGB
Memory BUS(DDRII) DDRII-SO-DIMM
PCB
Pineview page 7
DA60000E420
LCD Conn. LVDS FCBGA 559 1.8V DDRII 667
page 9 22x22mm
Thermal Sensor page 4,5,6
EMC1402
page 5
DMI
X2 mode
GEN1
PCBGA360 BlueTooth
page 15
17x17mm SATA
page 11,12,13,14
CMOS CAM
MINI Card x1 To I/O Board To I/O Board page 9
LPC BUS
Transfermer USB Port x1
To I/O Board Conn.
3 3
page 20
Conn. to I/O Board
Aralia Codec
ALC272 page 20
To I/O board
Power ON/OFF RJ45 Card Reader
DC/DC Interface
page 25
I/O Board ENE6252
page 18
3VALW/5VALW
page 26
ENE KBC SPI page 20
DC IN
page 23
KB926page 17
0.89VP/1.5VP
AMP & INT INT MIC HeadPhone & SD/MMC/MS
BATT IN 0.9VSP/2.5VSP MIC Jack
page 24 page 28 Speaker CONN
Int.KBD SPI ROM
page 19 page 17
CHARGER 1.8V/VCCP Touch Pad I/O Board
page 25
4
page 27 page19 4
CPU_CORE
page 29
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 2 of 32
A B C D E
A B C D E
1 1
2
+5VS 5V switched power rail ON OFF OFF 2
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 3 of 32
A B C D E
5 4 3 2 1
(7) DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M (7) DDR_A_D[0..63]
U71A U71B
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 DDR_A_DQS0
AH19 DDR_A_MA_0 DDR_A_DQS_0 AD3
DMI_RX0_R (7) DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 (13) AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DMI_RX#0_R F2 G1 DMI_TX#0 (13) DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RX1_R DMI_RXN_0 DMI_TXN_0 (7) DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
H4 DMI_RXP_1 DMI_TXP_1 H3 DMI_TX1 (13) AK16 DDR_A_MA_3
DMI_RX#1_R G3 J2 DMI_TX#1 (13) DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN_1 DMI_TXN_1 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
(8) CLK_CPU_EXP# N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
EXP_CLKINN EXP_RCOMPO R162 DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
(8) CLK_CPU_EXP N6 EXP_CLKINP EXP_ICOMPI L9 AH12 DDR_A_MA_11 DDR_A_DQ_7 AE3
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 EXP_TCLKINN AJ24 DDR_A_MA_13 DDR_A_DQS_1 AB8
R9 N11 DDR_A_MA14 AJ10 AD7 DDR_A_DQS#1
EXP_TCLKINP RSVD_TP T38 DDR_A_MA_14 DDR_A_DQS#_1
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
(7) DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
(7) DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
DDR_A_RAS# AK21 AE5 DDR_A_D10
(7) DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 (7) DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD (7) DDR_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
L3 N2 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD (7) DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 DDR_A_DQS_2 AD8
DDR_CS#0 AH22 AD10 DDR_A_DQS#2
(7) DDR_CS#0 DDR_A_CS#_0 DDR_A_DQS#_2
DDR_CS#1 AK25 AE8 DDR_A_DM2
(7) DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
JP16 AJ21
XDP_PREQ# CONN@ DDR_A_CS#_2 DDR_A_D16
(5) XDP_PREQ# 1 1 AJ25 DDR_A_CS#_3 DDR_A_DQ_16 AG8
(5) XDP_PRDY# XDP_PRDY# 2 AG7 DDR_A_D17
2 DDR_CKE0 DDR_A_DQ_17 DDR_A_D18
3 3 (7) DDR_CKE0 AH10 DDR_A_CKE_0 DDR_A_DQ_18 AF10
(5) XDP_BPM#3 XDP_BPM#3 4 DDR_CKE1 AH9 AG11 DDR_A_D19
4 (7) DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
(5) XDP_BPM#2 XDP_BPM#2 5 AK10 AF7 DDR_A_D20
5 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
6 6 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
C435 DMI_RX0_R XDP_BPM#1 DDR_A_D22
(13) DMI_RX0 1 2 (5) XDP_BPM#1 7 7 DDR_A_DQ_22 AD11
0.1U_0402_10V7K (5) XDP_BPM#0 XDP_BPM#0 8 M_ODT0 AK24 AE10 DDR_A_D23
8 (7) M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
9 M_ODT1 AH26
C436 9 (7) M_ODT1 DDR_A_ODT_1
1 2 DMI_RX#0_R (5,13) H_PWRGD R354 1 @ 2 1K_0402_5% 10 AH24 AK5 DDR_A_DQS3
(13) DMI_RX#0 10 DDR_A_ODT_2 DDR_A_DQS_3
0.1U_0402_10V7K R347 1 @ 2 1K_0402_5% 11 AK27 AK3 DDR_A_DQS#3
C (13) SLPIOVR# 11 DDR_A_ODT_3 DDR_A_DQS#_3 C
(8) CPU_ITP 12 AJ3 DDR_A_DM3
C437 12 DDR_A_DM_3
(13) DMI_RX1 1 2 DMI_RX1_R (8) CPU_ITP# 13 13 DDR_A_D24
0.1U_0402_10V7K +VCCP 14 14 DDR_A_DQ_24 AH1
PLTRST# 1 R348 2 1K_0402_1% 15 M_CLK_DDR0 AG15 AJ2 DDR_A_D25
C438 DMI_RX#1_R (5,13,15,17,20) PLTRST# 15 (7) M_CLK_DDR0 DDR_A_CK_0 DDR_A_DQ_25
(13) DMI_RX#1 1 2 @ 16 M_CLK_DDR#0 AF15 AK6 DDR_A_D26
16 (7) M_CLK_DDR#0 DDR_A_CK_0# DDR_A_DQ_26
0.1U_0402_10V7K 17 M_CLK_DDR1 AD13 AJ7 DDR_A_D27
17 (7) M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
(5) XDP_TDO XDP_TDO 18 M_CLK_DDR#1 AC13 AF3 DDR_A_D28
18 (7) M_CLK_DDR#1 DDR_A_CK_1# DDR_A_DQ_28
(5) XDP_TRST# XDP_TRST# 19 AH2 DDR_A_D29
19 DDR_A_DQ_29
Close to CPU (5)
(5)
XDP_TDI
XDP_TMS
XDP_TDI
XDP_TMS
20
21
20
AC15
DDR_A_DQ_30 AL5
AJ6
DDR_A_D30
DDR_A_D31
21 DDR_A_CK_3 DDR_A_DQ_31
22 22 AD15 DDR_A_CK_3#
23 AF13 AG22 DDR_A_DQS4
XDP_TCK 23 DDR_A_CK_4 DDR_A_DQS_4 DDR_A_DQS#4
(5) XDP_TCK 24 24 AG13 DDR_A_CK_4# DDR_A_DQS#_4 AG21
25 AD19 DDR_A_DM4
G1 DDR_A_DM_4
26 G2
AE19 DDR_A_D32
ACES_87151-24051 DDR_A_DQ_32 DDR_A_D33
+1.8V AD17 RSVD DDR_A_DQ_33 AG19
AC17 AF22 DDR_A_D34
RSVD DDR_A_DQ_34 DDR_A_D35
AB15 RSVD DDR_A_DQ_35 AD22
AB17 AG17 DDR_A_D36
RSVD DDR_A_DQ_36 DDR_A_D37
AF19
XDP Reserve +VCCP R369
10K_0402_5%
DDR_A_DQ_37
DDR_A_DQ_38 AE21
AD21
DDR_A_D38
DDR_A_D39
DDR_A_DQ_39
XDP_TDI R341 1 2 51 +-1% 0402 +1.8V +1.8V AE26 DDR_A_DQS5
DDR_A_DQS_5 DDR_A_DQS#5
AB4 RSVD DDR_A_DQS#_5 AG27
XDP_TMS R342 1 2 51 +-1% 0402 AK8 AJ27 DDR_A_DM5
RSVD DDR_A_DM_5
1
R370
XDP_TDO R343 1 2 51 +-1% 0402 AE24 DDR_A_D40
R50 10K_0402_5% DDR_A_DQ_40 DDR_A_D41
DDR_A_DQ_41 AG25
XDP_PREQ# R344 1 2 51 +-1% 0402 @ T40 AB11 AD25 DDR_A_D42
1K_0402_1% RSVD_TP DDR_A_DQ_42 DDR_A_D43
T41 AB13 RSVD_TP DDR_A_DQ_43 AD24
B DDR_A_D44 B
2
DDR_A_DQ_44 AC22
AL28 AG24 DDR_A_D45
R243 DDR_VREF DDR_A_DQ_45 DDR_A_D46
AK28 AD27
1
XDP_TRST# R345 1 51 +-1% 0402 R242 80.6_0402_1% DDR_RPD DDR_A_DQ_46 DDR_A_D47
2 R142 AJ26 DDR_RPU DDR_A_DQ_47 AE27
+5VS
FAN1 Conn XDP_TCK R346 1 2 51 +-1% 0402
1K_0402_1%
80.6_0402_1%
AK29 RSVD DDR_A_DQS_6 AE30 DDR_A_DQS6
AF29 DDR_A_DQS#6
Modify follow KAV60 schematic 06/12 DDR_A_DQS#_6 DDR_A_DM6
2
DDR_A_DM_6 AF30
U12
XDP_PREQ# 2
XDP_TDO D38 AB27 DDR_A_DQS7
1 8 DDR_A_DQS_7 DDR_A_DQS#7
EN GND AA27
1
DDR_A_DQS#_7
3
2 7
+VCC_FAN1 VIN GND 1 2 C314 DDR_A_DM_7 AB26 DDR_A_DM7
3 VOUT GND 6 D39
1 2 4 5
PJDLC05C_SOT23-3
(17) EN_FAN1 VSET GND 4.7U_0603_6.3V6K DDR_A_D56
PJDLC05C_SOT23-3
1 2
1
A R256 A
2 OF 6
10K_0402_5% PINEVIEW-M_FCBGA8559
40mil JP12 Add 2009-6-17
2
+VCC_FAN1 1 1
(17) FAN_SPEED1 2 2 G1 4
3 3 G2 5
1
ACES_85204-03001 Security Classification Compal Secret Data Compal Electronics, Inc.
C311 CONN@ 2006/08/18 2007/8/18 Title
Issued Date Deciphered Date
100P_0402_50V8J
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 4 of 32
5 4 3 2 1
5 4 3 2 1
PINEVIEW_M
U71C
C1171
VGA
1 2 D9 LA_DATAP_0 LINT0 H_NMI
XDP_RSVD_09 (9) LVDS_A1# N26 F11 H_NMI (12)
T8 C8 LA_DATAN_1 LINT1 H_IGNNE#
1K_0402_5% T15 XDP_RSVD_10 (9) LVDS_A1 N27 E5 H_IGNNE# (12)
B8 LA_DATAP_1 IGNNE# H_STPCLK#
XDP_RSVD_11 (9) LVDS_A2# R26 F8 H_STPCLK# (12)
T9 C10 L31 GMCH_CRT_DATA (10) LA_DATAN_2 STPCLK#
XDP_RSVD_12 CRT_DDC_DATA
ICH
(9) LVDS_A2 R27 LA_DATAP_2
T16 D10 XDP_RSVD_13 CRT_DDC_CLK L30 GMCH_CRT_CLK (10)
T10 B11 XDP_RSVD_14 H_DPRSTP#
R201 665_0402_1% DPRSTP# G6 H_DPRSTP# (13)
T17 B10 XDP_RSVD_15 DAC_IREF P28 R151 H_DPSLP#
R22 LIBG DPSLP# G10 H_DPSLP# (13)
T11 B12 XDP_RSVD_16 2.37K_0402_1% H_INIT#
CPU_DREFCLK J28 LVBG INIT# G8 H_INIT# (12)
T28 C11 XDP_RSVD_17 REFCLKINP Y30 CPU_DREFCLK (8) XDP_PRDY#
CPU_DREFCLK# N22 LVREFH PRDY# E11 XDP_PRDY# (4)
REFCLKINN Y29 CPU_DREFCLK# (8) XDP_PREQ#
CPU_SSCDREFCLK N23 LVREFL PREQ# F15 XDP_PREQ# (4)
REFSSCLKINP AA30 CPU_SSCDREFCLK (8) GMCH_ENBKL
CPU_SSCDREFCLK# (17) GMCH_ENBKL L27 LBKLT_EN
AA31
LVDS
REFSSCLKINN CPU_SSCDREFCLK# (8) (9,17) INVT_PWM L26
0_0402_5% LBKLT_CTL H_THERMTRIP#
L23 LCTLA_CLK THERMTRIP# E13 H_THERMTRIP# (12)
T37 L11 RSVD R213 @ K25 LCTLB_DATA
Add INVT_PWM
(9)
05/11
LVDS_SCL K23 LDDC_CLK
0_0402_5% (9) LVDS_SDA K24
R200 LDDC_DATA
PM_EXTTS#1 (9) GMCH_ENVDD H26 LVDD_EN
PM_EXTTS#_1/DPRSLPVR K29 PM_DPRSLPVR (13) H_PROCHOT#
PM_EXTTS#0 PROCHOT# C18
PM_EXTTS#_0 J30 PM_EXTTS#0 (7) H_PWRGD
H_PWROK CPUPWRGOOD W1 H_PWRGD (4,13)
PWROK L5
AA3 PLTRST#
RSTIN# PLTRST# (4,13,15,17,20)
A13 H_GTLREF
W8 CLK_CPU_HPLCLK# GTLREF
HPL_CLKINN CLK_CPU_HPLCLK# (8) H27
CLK_CPU_HPLCLK VSS
C
HPL_CLKINP W9 CLK_CPU_HPLCLK (8) Del R323 05/11 C
AA7 Modify 08/04
MISC
T18 RSVD_TP
T19 AA6 RSVD_TP
RSVD L6
T20 R5 RSVD_TP
RSVD E17
T21 R6 RSVD_TP (4) XDP_BPM#0 G11 BPM_1_0#
E15 H10 CLK_CPU_BCLK#
T22 AA21 @ (4) XDP_BPM#1 BPM_1_1# BCLKN CLK_CPU_BCLK# (8)
RSVD_TP R305 G13 J10 CLK_CPU_BCLK
T23 W21 H_PWROK 1 2 (4) XDP_BPM#2 BPM_1_2# BCLKP CLK_CPU_BCLK (8)
RSVD_TP VGATE (8,13,17,29) F13
T24 T21 (4) XDP_BPM#3 BPM_1_3#
RSVD_TP 0_0402_5% K5 CPU_BSEL0
T25 V21 BSEL_0 CPU_BSEL0 (8)
RSVD_TP R306 T48 B18 H5 CPU_BSEL1
1 2 BPM_2_0#/RSVD BSEL_1 CPU_BSEL1 (8)
PCH_POK (13,17) T49 B20 K6 CPU_BSEL2
BPM_2_1#/RSVD BSEL_2 CPU_BSEL2 (8)
0_0402_5%
CPU
T50 C20 BPM_2_2#/RSVD
T51 B21 H30 CPU_VID0
BPM_2_3#/RSVD VID_0 CPU_VID0 (29)
H29 CPU_VID1
VID_1 CPU_VID1 (29)
H28 CPU_VID2
VID_2 CPU_VID2 (29)
G30 CPU_VID3
VID_3 CPU_VID3 (29)
T55 G5 G29 CPU_VID4
RSVD VID_4 CPU_VID4 (29)
XDP_TDI D14 F29 CPU_VID5
(4) XDP_TDI TDI VID_5 CPU_VID5 (29)
XDP_TDO D13 E29 CPU_VID6
(4) XDP_TDO TDO VID_6 CPU_VID6 (29)
XDP_TCK B14
(4) XDP_TCK TCK
XDP_TMS C14 L7
(4) XDP_TMS TMS RSVD
XDP_TRST# C16 D20
(4) XDP_TRST# TRST# RSVD
RSVD H13
RSVD D18
H_THERMDA D30
H_THERMDC THRMDA_1
E30 THRMDC_1 RSVD_TP K9 T26
RSVD_TP D19 T27
K7 H_EXTBGREF
EXTBGREF
B XDP_TCK B
Place closed to chipset T58
T59 XDP_TDI
3 OF 6 R307
GMCH_CRT_R 1 2
PINEVIEW-M_FCBGA8559 150_0402_1% T60 XDP_TDO
GMCH_CRT_G C30
1 R308 2 THRMDA_2/RSVD
150_0402_1% XDP_TMS D31 THRMDC_2/RSVD
T61
GMCH_CRT_B 1 R309 2
150_0402_1% XDP_TRST# 4 OF 6
T62 PINEVIEW-M_FCBGA8559
GMCH_ENBKL R34
100K_0402_5% T63 H_PWRGD
+VCCP
+VCCP
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
R244
R144
+VCCP 976_0402_1%
1K_0402_1%
+3VS
+3VS H_EXTBGREF
CPU THERMAL SENSOR H_GTLREF
1
1U_0603_10V6K
1U_0603_10V6K
R202
R143 68_0402_5% 1 1 R156
@ C939
@ C940
R155
0.1U_0402_16V4Z
1 10K_0402_5% 3.3K_0402_1%
2K_0402_1%
C80 H_PROCHOT#
2
U2 PM_EXTTS#0 2 2
2
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A
1 8 EC_SMB_CK2
Close to Processor Close to Processor placed within 0.5" A
l.c
VDD SMCLK EC_SMB_CK2 (17)
pin pin placed within 0.5"
of processor pin.
ai
H_THERMDA 2 7 EC_SMB_DA2
C79 DP SMDATA EC_SMB_DA2 (17) of processor pin.
tm
1 2 H_THERMDC 3 6 2 R58 1 +3VS
2200P_0402_50V7K DN ALERT# 10K_0402_5%
ho
4 THERM# GND 5
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EMC1402-1-ACZL-TR MSOP 8P SENSOR Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Address:100_1100 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 5 of 32
5 4 3 2 1
5 4 3 2 1
U71F PINEVIEW_M
GFX/MCH
VCCGFX VCC VSS VSS
W19 VCCGFX VCC E22 AA8 VSS VSS J15
VCC E24 AB19 VSS VSS J4
E27 AB21 K11
CPU
VCC VSS VSS
VCC F21 AB28 VSS VSS K13
VCC F22 AB29 VSS VSS K19
VCC F25 AB30 VSS VSS K26
VCC G19 +VCCP AC10 VSS VSS K27
VCC G21 AC11 VSS VSS K28
VCC G24 AC19 VSS VSS K30
H17 AC2 K4
DDR supply current 2.27A
GND
VCC VSS VSS
VCC H19 AC21 VSS VSS K8
VCC H22 1 1 AC28 VSS VSS L1
+1.8V H24 C1160 C1161 AC30 L13
VCC VSS VSS
2.2U_0603_10V6K2.2U_0603_10V6K VCC J17 AD26 VSS VSS L18
AK13 J19 0.1U_0402_10V6K 0.1U_0402_10V6K AD5 L22
VCCSM VCC 2 2 VSS VSS
AK19 VCCSM VCC J21 AE1 VSS VSS L24
2 2 2 2 AK9 VCCSM VCC J22 AE11 VSS VSS L25
AL11 K15 Close U71.D4 AE13 L29
C188 C187 C186 C85 VCCSM VCC VSS VSS
AL16 VCCSM VCC K17 R20 AE15 VSS VSS M28
AL21 K21 1 2 +RING_EAST AE17 M3
1 1 1 1 VCCSM VCC VSS VSS
2.2U_0603_10V6K 2.2U_0603_10V6K AL25 VCCSM VCC L14 0_0603_5% 1 AE22 VSS VSS N1
+1.8V L16 AE31 N13
C VCC C242 VSS VSS C
VCC L19 AF11 VSS VSS N18
L21 1U_0603_10V6K AF17 N24
VCC 2 VSS VSS
VCC N14 AF21 VSS VSS N25
VCC N16 AF24 VSS VSS N28
22UF 6.3V M X5R 0805
1U_0603_10V6K
B9 VSS VSS W5
2 1 AC31 +1.8VS C1 W6
VCCSFR_AB_DPL +VCC_ALVD RSVD_NCTF VSS
1 1 VCCALVDS V30 C12 VSS VSS W7
0_0603_5% W31 +VCC_DLVD C21 Y28
VCCDLVDS VSS VSS
C192
C189
VCCACRTDAC RSVD_NCTF
D22 VSS
+3VS C239 E1
1U_0603_10V6K RSVD_NCTF
E10 VSS
GIO supply current: 0.006A T31 T1 +VCC_DMI 2
E19
+RING_EAST VCC_GIO VCCA_DMI VSS
J31 T2 DMI analog supply current: 0.48A +DMI_HMPLL E21
+RING_WEST VCCRING_EAST VCCA_DMI 1 R18 2 VSS
C3 T3 E25 T29
DMI
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0603_10V6K
+CPU_CORE C235
C74
C81
C70
C76
C75
C78
C77
C71
2 1 1 1 1 1 1 1 1U_0603_10V6K
2
R32
VCCSENSE 1 2
1 2 2 2 2 2 2 2 100_0402_1%
R31
VSSSENSE 1 2
100_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
Modify to 2.2U
Close Chipset pin
05/11 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 6 of 32
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
09/03 CONN@
JDIM1
Change to SP07F001720 04/30
20mils
(4) DDR_A_DQS#[0..7] +DIMM_VREF 1 VREF VSS 2
3 4 DDR_A_D4
+1.8V DDR_A_D0 VSS DQ4 DDR_A_D5
(4) DDR_A_D[0..63] 1 1 5 DQ0 DQ5 6
C111 C112 DDR_A_D1 7 8
DQ1 VSS DDR_A_DM0
(4) DDR_A_DM[0..7] 9 VSS DM0 10
1
0.1U_0402_16V4Z 2.2U 6.3V M X5R 0402 DDR_A_DQS#0 11 12
R61 2 2 DDR_A_DQS0 DQS0# VSS DDR_A_D6
(4) DDR_A_DQS[0..7] Layout Note: 13 DQS0 DQ6 14
15 16 DDR_A_D7
(4) DDR_A_MA[0..14]
Place near JDIM1 1K_0402_1% DDR_A_D2 17
VSS DQ7
18
DDR_A_D3 DQ2 VSS DDR_A_D12
19 20
2
DQ3 DQ12 DDR_A_D13
+DIMM_VREF 21 VSS DQ13 22
DDR_A_D8 23 24
DQ8 VSS
1
D DDR_A_D9 DDR_A_DM1 D
25 DQ9 DM1 26
R62 Share +DIMM_VREF for 27 28
DDR_A_DQS#1 VSS VSS M_CLK_DDR0
29 30 M_CLK_DDR0 (4)
1K_0402_1% 1.DDRII VREF DDR_A_DQS1 31
DQS1# CK0
32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 (4)
+1.8V 2.GMCH SM_VREF_0 33 34
2
DDR_A_D10 VSS VSS DDR_A_D14
35 36
SM_VREF_1 DDR_A_D11 37
DQ10 DQ14
38 DDR_A_D15
DQ11 DQ15
39 VSS VSS 40
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2 2 2 2 2
41 VSS VSS 42
C128
C129
C110
C109
C130
DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
1 1 1 1 1
47 VSS VSS 48
DDR_A_DQS#2 49 50 R64 1 2
DQS2# NC PM_EXTTS#0 (5)
DDR_A_DQS2 51 52 DDR_A_DM2 0_0402_5%
DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D22
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
59 VSS VSS 60
220U_B2_2.5VM_R35
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR_A_D24 61 62 DDR_A_D28
DDR_A_D25 DQ24 DQ28 DDR_A_D29
1 1 1 1 63 DQ25 DQ29 64
+ 65 66
VSS VSS
C94
C106
C105
C108
C107
@ DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
2 2 2 2 2
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
(4) DDR_CKE0 DDR_CKE0 79 80 DDR_CKE1 DDR_CKE1 (4)
CKE0 NC/CKE1
81 VDD VDD 82
83 NC NC/A15 84
C DDR_A_BS2 DDR_A_MA14 C
(4) DDR_A_BS2 85 BA2 NC/A14 86
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
Layout Note: 99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
Place one cap close to every 2 pullup 103
A1 A0
104
DDR_A_MA10 VDD VDD DDR_A_BS1
resistors terminated to +0.9VS 105 A10/AP BA1 106 DDR_A_BS1 (4)
(4) DDR_A_BS0 DDR_A_BS0 107 108 DDR_A_RAS# DDR_A_RAS# (4)
DDR_A_WE# BA0 RAS# DDR_CS#0
(4) DDR_A_WE# 109 WE# S0# 110 DDR_CS#0 (4)
111 VDD VDD 112
(4) DDR_A_CAS# DDR_A_CAS# 113 114 M_ODT0 M_ODT0 (4)
DDR_CS#1 CAS# ODT0 DDR_A_MA13
(4) DDR_CS#1 115 NC/S1# NC/A13 116
117 VDD VDD 118
(4) M_ODT1 M_ODT1 119 120
NC/ODT1 NC
121 VSS VSS 122
+0.9VS DDR_A_D32 123 124 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 136
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DQ34 DQ39
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C445
C446
C439
C440
C441
C442
C443
C117
C86
C121
C87
C88
C122
C115
C91
C90
C120
C118
C89
47_0804_8P4R_5% 47_0804_8P4R_5%
0.1U_0402_16V4Z
om
6 6 2
DDR_A_WE# 4 5 5 4 DDR_A_MA12 2
A
DIMMA A
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ai
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DDR_CKE1 1 R163
ho
2
47_0402_5% Layout Note:
DDR_A_BS2 1 R60 2
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Place these resistor
47_0402_5%
closely DIMMA,all Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
DDR_CKE0 1 R59 2
SCHEMATICS, MB A5651
in
47_0402_5% trace length
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Max=1.3" Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 7 of 32
5 4 3 2 1
5 4 3 2 1
Change C174 C175 to 10U_0603 05/14
+3VM_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB +3VS
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz +3VS 1
R1370_0603_5%
2
1 1 1 1 1
C174 C172 C138 C148 R72 R91
0 0 0 266 100 33.3 14.318 96.0 48.0 C1145
47P_0402_50V8J
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2.2K_0402_5% 2.2K_0402_5%
2 2 2 2 0.1U_0402_16V4Z 2 2N7002DW-T/R7_SOT363-6
0 0 1 133 100 33.3 14.318 96.0 48.0 Q10A
+1.05VM_CK505 CLK_SMBDATA
(13) ICH_SMBDATA 6 1
0 1 0 200 100 33.3 14.318 96.0 48.0 R138
+VCCP 1 2
0_0603_5% 1 1 1 1 1 1
2
0 1 1 166 100 33.3 14.318 96.0 48.0 1 C139 C167 C137 C146 C165 +3VS
D C1146 C175 D
5
47P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 10U_0603_6.3V6M 2 2 2 2 2
1 0 0 333 100 33.3 14.318 96.0 48.0 2
(13) ICH_SMBCLK 3 4 CLK_SMBCLK
9 CLK_SMBDATA
R435 +1.5VM_CK505 SDA CLK_SMBDATA (7,15)
+1.5VS 1
R1349
2
0_0603_5%
55 VDD_SRC
SCL 10 CLK_SMBCLK
CLK_SMBCLK (7,15)
SRC PORT LIST
10K_0402_5% LOWPW@ 0.1U_0402_16V4Z 6 VDD_REF
1 1 1 1 1
1
C386 10P_0402_50V8J 2
R68 @ 1 2 38 32
SRC9 CLK_CPU_EXP
VDD_SRC_IO SRC_2
R76 470_0402_5%
09/03 Modify T64
CLK_48M_CR 1 R74 2 33
SRC10 PCIE_LAN
2.2K_0402_5% 22_0402_5% SRC_2#
SRC11 PCIE_WWAN
2
@ FSA 1 8 SS_VDD 1 2@ 54
Add 1K follow R113 XIN/CLKIN VCC 0.1U_0402_16V7K (13) H_STP_PCI# PCI_STOP# CLK_PCIE_PCH#
SRC_7# 60 CLK_PCIE_PCH# (13)
Intel check list 05/11 2 7 1 2
470_0402_5% XOUT SSEXTR R1382 @ 1M +-5% 0402 CLK_XTAL_IN 5 XTAL_IN
B R52 1K_0402_1% 3 6 T57 64 CPU_ITP (4) B
2
FS MR CLK_XTAL_OUT SRC_8/CPU_ITP
FSB 1 2 4 XTAL_OUT
4 5 1 2 CLK_PCH_48M 63
GND MODOUT SRC_8#/CPU_ITP# CPU_ITP# (4) +3VS
1 2 R1384 22_0402_5%
(5) CPU_BSEL1
R119 PCS3P73Z21BWG-08-CR TDFN 8P @
0_0402_5% 13 44 CLK_CPU_EXP
PCI_1 SRC_9 CLK_CPU_EXP (4)
1
33_0402_5%
15P 50V J NPO 0402
CLK_PCIE_WWAN
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# C389
1 1
C388 SRC_11 48 CLK_PCIE_WWAN (15)
REQ PORT LIST
1
18 47 CLK_PCIE_WWAN#
VSS_PCI SRC_11# CLK_PCIE_WWAN# (15)
R92 @ For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# 60-3G@2 60-3G@
2
R98 470_0402_5% Pin28/29 : LCDCLK / LCDCLK# 3 VSS_REF PORT DEVICE
10K_0402_5% 1 = Pin24/25 : SRC_0 / SRC_0# 22 37
2
VSS_48 CLKREQ_3#
FSC 2 1
Pin28/29 : 27M/27M_SS 26 41 WLAN_CLKREQ#
Add WWAN_CLKREQ# 05/04
REQ_3#
VSS_IO CLKREQ_4# WLAN_CLKREQ# (20)
(5) CPU_BSEL2 1
R84
2
For PCI2_TME:0=Overclocking of CPU and SRC allowed 69 58
REQ_4# PCIE_WLAN
0_0402_5% VSS_CPU CLKREQ_6#
(ICS only) 1=Overclocking of CPU and SRC NOT allowed REQ_6#
1
30 VSS_PLL3 CLKREQ_7# 65
R87
@ 34 43
REQ_7#
0_0402_5% VSS_SRC CLKREQ_9#
+3VS +3VS +3VS 59 49
REQ_9#
2
VSS_SRC SLKREQ_10#
42 46 WWAN_CLKREQ#
WWAN_CLKREQ# (15)
REQ_10#
VSS_SRC CLKREQ_11#
2
A
R85 R95 R71 73 21
REQ_11# PCIE_WWAN A
VSS USB_1/CLKREQ_A#
Follow Intel check list change to 27P 06/05 REQ_A#
10K_0402_5% 10K_0402_5% 10K_0402_5%
Follow Vendor check change to 22P 10/16 @ @ ICS9LPRS387BKLFT_QFN72_10X10
1
Y1
2
@
14.318MHZ_16PF_7A14300083 R89 R90 R77 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Routing the trace at least 10mil DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401793 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 8 of 32
5 4 3 2 1
5 4 3 2 1
+3VS 1 2 +CAM_VCC
+LCDVDD +3VS 1 2
NTR4101PT1G 1P SOT-23-3
+LCDVDD
Q3
JUMP_43X39
W=20mils W=20mils
1
@
S
1 3
R577 +3VS
D D
@
470_0402_5% 1
G
2
C1105 1 C1106 1 1
2
0.1U_0402_16V4Z C1107 C1113
2
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
1+LCDVDD_R
2
4.7U_0603_6.3V6K
R578 1 2 2 2
C1108
100K_0402_5%
0.047U_0402_16V4Z
1
Q4 2
D
2 2 1
2N7002W-T/R7_SOT323-3 G PJUSB208_SOT23-6
S3 R579 4.7K_0402_5%
USB20_N3_1 6 3
CH3 CH2
+CAM_VCC 5 Vp Vn 2
4 1 USB20_P3_1
CH4 CH1
1
Q5 D6
DTC115EUA_SC70-3
@
(5) GMCH_ENVDD 2
Add D6 05/14
2
R174
3
C 100K_0402_5% C
1
2 1
0_0402_5% R1182
@ L3
USB20_N3_1 2 1 USB20_N3 USB20_N3 (13)
2 1
C1167 C1168
10P_0402_50V8J
10P_0402_50V8J
2 1
CMOS & LCD/PANEL BD. Conn. 2 2
@
0_0402_5% R1183
+3VS
2.2K_0402_5%
2
2
R1180
R1181
Add for RF 07/02
JLVDS1
1
1 1
USB20_P3_1
2 USB20_N3_1
camera LVDS_SCL
B 3 LVDS_SCL (5) B
4 +CAM_VCC
LVDS_SDA LVDS_SDA (5)
5
6
7 LVDS_ACLK
8 LVDS_ACLK (5)
LVDS_ACLK#
9 LVDS_ACLK# (5)
10 LVDS_A2
11 LVDS_A2 (5)
LVDS_A2# LVDS_A2# (5)
12 INVT_PWM
13 LVDS_A1
14 LVDS_A1 (5)
LVDS_A1# LVDS_A1# (5)
15 BKOFF#
16 LVDS_A0
17 LVDS_A0 (5)
LVDS_A0# LVDS_A0# (5)
18
19
1
22 INVT_PWM
23 INVT_PWM (5,17)
24 +LCDVDD_L
+3VS For RF
25 1 2 +LCDVDD
L2
26 FBMA-L11-201209-221LMA30T_0805
27 (20 MIL)
+LEDVDD L1 2 1 B+
28
29 FBMA-L11-201209-221LMA30T_0805
30 2 1
ACES_88341-3000B001 C1111 C1112
330P_0402_50V7K 100P_0402_50V8J
CONN@ 1 2
om
A A
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 B
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 9 of 32
5 4 3 2 1
A B C D E
2
D18
D17
PJDLC05C_SOT23-3
1 1
PJDLC05C_SOT23-3
Modify C31- C308 C303 C307 C306 C304 BOM Structure 0615
1
L15
BK1608LL121-T_2P
1 2 RED
(5) GMCH_CRT_R
L14
BK1608LL121-T_2P
1 2 GREEN
(5) GMCH_CRT_G
L12
BK1608LL121-T_2P
1 2 BLUE
(5) GMCH_CRT_B
150_0402_1%
150_0402_1%
150_0402_1%
1
1
1 1 1
R255 R253 R250 C310 1 1 1
10P_0402_50V8J
C308 C303
10P_0402_50V8J
10P_0402_50V8J
C307 C306 C304
2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
2
2
2 2 2
+5VS JVGA_HS
1 2
C301 0.1U_0402_16V4Z JVGA_VS
1
2 U11 2
R249
OE#
1 2 2 4 CRT_HSYNC_1
(5) GMCH_CRT_HSYNC A Y
G
10_0402_5% SN74AHCT1G125DCKR_SC70-5
3
+5VS
Change CRT_DET# From Page 13 to Page 10 06/12
Place closed to chipset
1 2
C298 0.1U_0402_16V4Z
1
U10 +3VS
R247
OE#
1 2 2 4 CRT_VSYNC_1
(5) GMCH_CRT_VSYNC A Y
2
G R149
10_0402_5% SN74AHCT1G125DCKR_SC70-5 10K_0402_5%
3
1
CRT_DET
(13) CRT_DET
1
D
Add R1283 R1284 CRT_DET# 2 Q11
Change R247 R249 to 10 ohm G 2N7002W-T/R7_SOT323-3
S
CRT PORT
3
Add @ on U10 U11 C301 C298 06/08
+3VS
+CRT_VCC
+CRT_VCC
+5VS
1
0.1U_0402_16V4Z
3 R248 2.2K_0402_5% 3
+3VS C142
D3 W=40mils
2.2K_0402_5% R245 2 1 1 2 Change JCRT1 P/N to SP010906182 06/22
1
1
2
2
5
7
VGA_DDC_DAT 12
4 3 VGA_DDC_DAT GREEN 2
(5) GMCH_CRT_DATA
8
JVGA_HS 13
Q24B
2
BLUE 3
2N7002DW-T/R7_SOT363-6 9
1 6 VGA_DDC_CLK JVGA_VS 14 16
(5) GMCH_CRT_CLK
4 17
Q24A 10
VGA_DDC_CLK 15
2N7002DW-T/R7_SOT363-6 5
SUYIN_070546FR015M21RZR
CRT_DET#
2
R1103
100K_0402_5%
4 4
1
+CRT_VCC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 10 of 32
A B C D E
5 4 3 2 1
D D
0 1 SPI
1 0 PCI
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A A
1 1 LPC
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 11 of 32
5 4 3 2 1
5 4 3 2 1
D D
U72C TGP
SATA
W10 RSVD13
V12 RSVD14
AE21 RSVD15
AE18 RSVD16
AD19 RSVD17
U12 RSVD18
SATA_CLKN AD4 CLK_PCIE_SATA# (8) Placed within 500 mils of Tiger point chipset pin.
AC17 RSVD19 SATA_CLKP AC4 CLK_PCIE_SATA (8) +3VS
AB13 RSVD20
AC13 RSVD21 SATARBIAS# AD11 R45
AB15 AC11 SATARBIAS R154 24.9_0402_1%
RSVD22 SATARBIAS SATA_LED# SATA_LED#
Y14 RSVD23 SATALED# AD25 SATA_LED# (16)
10K_0402_5%
AB16 RSVD24
AE24 R293
RSVD25 GATEA20
AE23 RSVD26 10K_0402_5%
R312
AA14 U16 GATEA20 GATEA20 (17) SERIRQ
RSVD27 A20GATE H_A20M#
V14 RSVD28 A20M# Y20 H_A20M# (5) 10K_0402_5%
CPUSLP# Y21
Y18 H_IGNNE#
IGNNE# H_IGNNE# (5) +VCCP
AD16 RSVD29 INIT3_3V# AD21
AB11 AC25 H_INIT#
RSVD30 INIT# H_INIT# (5)
+3VS AB10 AB24 H_INTR
RSVD31 INTR H_INTR (5) 56 ohm±5% pull-up resistor has
HOST
1
Y22 H_FERR#
B FERR# H_FERR# (5) B
R294 8.2K_0402_5% AD23 GPIO36 NMI T17 H_NMI
H_NMI (5)
R164 to be within 1" from the Tiger
AC21 KB_RST#
RCIN#
AA16 SERIRQ
KB_RST# (17)
56_0402_5%
Point chipset.
SERIRQ SERIRQ (17)
AA21 H_SMI#
H_SMI# (5)
2
SMI# H_STPCLK#
STPCLK# V18 H_STPCLK# (5)
THRMTRIP# AA20 H_THERMTRIP# (5)
3
ESD request
TIGERPOINT_ES1_BGA360
H_A20M# C450 @
1 2 100P_0402_50V8J
H_IGNNE# C451 @
1 2 100P_0402_50V8J
H_INIT# C452 @
1 2 100P_0402_50V8J
+VCCP
H_INTR C453 @
1 2 100P_0402_50V8J
H_FERR# C454 @
1 2 100P_0402_50V8J
R198
56_0402_5% H_NMI C455 @
1 2 100P_0402_50V8J
H_SMI# C456 @
1 2 100P_0402_50V8J
H_FERR#
H_STPCLK# C457 @
1 2 100P_0402_50V8J
Close to TigerPoint
A
pin A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793
Date: Friday, May 21, 2010 Sheet 12 of 32
5 4 3 2 1
5 4 3 2 1
U72B TGP
U72D TGP
R23 H7 USB20_N0
+3VS (4) DMI_TX#0 DMI0RXN USBP0N USB20_N0 (20)
AA5 T15 GPIO0 R24 H6 USB20_P0
LDRQ1#/GPIO23 BMBUSY#/GPIO0 (4) DMI_TX0 DMI0RXP USBP0P USB20_P0 (20)
V6 W16 CRT_DET P21 H3 USB20_N1
(17) LPC_AD0 LAD0/FWH0 GPIO6 CRT_DET (10) (4) DMI_RX#0 DMI0TXN USBP1N USB20_N1 (20)
LPC
AA6 W14 GPIO7 P20 H2 USB20_P1
(17) LPC_AD1 LAD1/FWH1 GPIO7 SLPIOVR# (4) (4) DMI_RX0 DMI0TXP USBP1P USB20_P1 (20)
Y5 K18 EC_SMI# T21 J2 USB20_N2
(17) LPC_AD2 LAD2/FWH2 GPIO8 EC_SMI# (17) (4) DMI_TX#1 DMI1RXN USBP2N USB20_N2 (20)
W8 H19 EC_SCI# T20 J3 USB20_P2
(17) LPC_AD3 LAD3/FWH3 GPIO9 EC_SCI# (17) @ (4) DMI_TX1 DMI1RXP USBP2P USB20_P2 (20)
1
Y8 M17 ACIN_C T24 K6 USB20_N3
LDRQ0# GPIO10 (4) DMI_RX#1 DMI1TXN USBP3N USB20_N3 (9)
Y4 A24 GPIO12 T25 K5 USB20_P3
(17) LPC_FRAME# LFRAME#/FWH4 GPIO12 R1390 (4) DMI_RX1 DMI1TXP USBP3P USB20_P3 (9)
DMI
C23 EC_LID_OUT# T19 K1 USB20_N4
R160 GPIO13 EC_LID_OUT# (17) DMI2RXN USBP4N USB20_N4 (20)
33_0402_5% 1 2 P6 P5 GPIO14 T18 K2 USB20_P4
(20) HDA_BITCLK_AUDIO R158 HDA_BIT_CLK GPIO14 10K_0402_5% DMI2RXP USBP4P USB20_P4 (20)
33_0402_5% 1 2 U2 E24 GPIO15 U23 L2 USB20_N5
(20) HDA_RST_AUDIO#
2
HDA_RST# GPIO15 DMI2TXN USBP5N USB20_N5 (15)
1 0_0402_5%
AUDIO
W2 AB20 2 R17 U24 L3 USB20_P5
(20) HDA_SDIN0 HDA_SDIN0 DPRSLPVR PM_DPRSLPVR (5) DMI2TXP USBP5P USB20_P5 (15)
V2 Y16 1 2 V21 M6 USB20_N6
HDA_SDIN1 STP_PCI# H_STP_PCI# (8) DMI3RXN USBP6N USB20_N6 (15)
P8 AB19 R1391 V20 M5 USB20_P6
33_0402_5% R159 2 HDA_SDIN2 STP_CPU# H_STP_CPU# (8) DMI3RXP USBP6P USB20_P6 (15)
1 AA1 R3 0_0402_5% V24 N1 USB20_N7
(20) HDA_SDOUT_AUDIO HDA_SDOUT GPIO24 DMI3TXN USBP7N USB20_N7 (20)
33_0402_5% 1 R157 2 Y1 C24 1 R367 2 V23 N2 USB20_P7
(20) HDA_SYNC_AUDIO HDA_SYNC GPIO25 DMI3TXP USBP7P USB20_P7 (20)
AA3 D19 1K_0402_5%
(8) CLK_PCH_14M CLK14 GPIO26
1
GPIO27 D20
U3 F22 D4 USB_OC#0_1
R337 EE_CS GPIO28 OC0# USB_OC#0_1 (20)
PM_CLKRUN# USB_OC#0_1
USB
@ 33_0402_5% AE2 EE_DIN CLKRUN# AC19 (20) PCIE_DTX_C_IRX_N1 K21 PERN1 OC1# C5
T6 U14 K22 D3 USB_OC#2
V3
EE_DOUT EPROM GPIO33
AC1
(20) PCIE_DTX_C_IRX_P1 C565 0.1U_0402_10V7K PCIE_ITX_C_DRX_N1_RJ23 PERP1 OC2#
D2 USB_OC#3 USB_OC#2 (20)
C EE_SHCLK GPIO34 GPIO38 (20) PCIE_ITX_C_DRX_N1 C566 0.1U_0402_10V7K PCIE_ITX_C_DRX_P1_R J24 PETN1 OC3# USB_OC#4 C
2
MISC
For EMI, Close to TigerPoint LAN_RXD0 EC_THERM# (20) PCIE_ITX_C_DRX_P2 PETP2
AD1 LAN_RXD1 THRM# AB17 EC_THERM# (17) (15) PCIE_DTX_C_IRX_N3 L23 PERN3
PCI-E
AC2 V16 VGATE L24
LAN_RXD2 VRMPWRGD (15) PCIE_DTX_C_IRX_P3 C52 0.1U_0402_10V7K PCIE_ITX_C_DRX_N3_RL22 PERP3
W3 AC18 MCH_SYNC# G2
LAN_TXD0 MCH_SYNC# PBTN_OUT# (15) PCIE_ITX_C_DRX_N3 C54 0.1U_0402_10V7K PCIE_ITX_C_DRX_P3_RM21 PETN3 USBRBIAS USBRBIAS R152
T7 LAN_TXD1 PWRBTN# E21 PBTN_OUT# (17) (15) PCIE_ITX_C_DRX_P3 PETP3 USBRBIAS# G3
U4 H23 ICH_RI# P17 20 +-1% 0402
LAN_TXD2 RI# PERN4
SUS_STAT#/LPCPD# G22 P18 PERP4
RTCX1 W4 D22 N25
RTC
1
C25 ICH_PCIE_WAKE#
WAKE# ICH_PCIE_WAKE# (15,20) R338
SMBALERT# E20 T8 INTRUDER#
SMBALERT#/GPIO11 INTRUDER#
1
(8) ICH_SMBCLK ICH_SMBCLK H18 U10 T_PWROK C1158 33_0402_5%
SMBCLK PWROK
SMB
2
SMLINK0 LINKALERT# INTVRMEN SB_SPKR
F25 SMLINK0 SPKR J16 SB_SPKR (20)
SMLINK1 F24 +1.5VS R434
SMLINK1 R153 24.9_0402_1% @ 22P_0402_50V8J
SLP_S3# H20 PM_SLP_S3# (17) 2
R2 SPI_MISO SLP_S4# E25 PM_SLP_S4# (17) 1 2 H24 DMI_ZCOMP
T1 F21 J22 For EMI, Close to TigerPoint
SPI_MOSI SLP_S5# PM_SLP_S5# (17) DMI_IRCOMP
SPI
M8 SPI_CS#
P9 B25 PM_BATT_LOW# W23
SPI_CLK BATLOW# (8) CLK_PCIE_PCH# DMI_CLKN
R4 AB23 H_DPRSTP# W24
SPI_ARB DPRSTP# H_DPRSTP# (5) (8) CLK_PCIE_PCH DMI_CLKP
AA18 H_DPSLP#
DPSLP# H_DPSLP# (5) 0_0402_5% 2
+3VALW RSVD31 F20
T_PWROK 1 R310 2 VGATE
VGATE (5,8,17,29) TIGERPOINT_ES1_BGA360
@
B
2.2K_0402_5% 1 R147 2 ICH_SMBCLK R311 +3VALW B
TIGERPOINT_ES1_BGA360 1 2 PCH_POK (5,17)
2.2K_0402_5% 1 R148 2 ICH_SMBDATA 0_0402_5%
10K_0402_5% 2 R40 1 LINKALERT# +3VS USB_OC#0_1 R46 10K_0402_5%
10K_0402_5% 2 R44 1 SMLINK0 D25 RB751V_SOD323 USB_OC#2 R49 10K_0402_5%
10K_0402_5% 2 10K_0402_5% 2 R37 1 T_PWROK ACIN_C 2 1 ACIN USB_OC#3 R48 10K_0402_5%
R43 SMLINK1 ACIN (17,23)
2
1 USB_OC#4
8.2K_0402_5% 10K_0402_5% 2 R38 1 EC_RSMRST#R
R239 PM_BATT_LOW# R1376 2 R223 1 2 1 USB_OC#5
+3VALW
1K_0402_5% 1 R145 10K_0402_5% @ R222 USB_OC#6 modify 05/14
2ICH_PCIE_WAKE# USB_OC#7
50@ 100K_0402_5% 0_0402_5%
10K_0402_5% 2 R39 1 SYS_RST#
1
8.2K_0402_5% GPIO38
R240 ICH_RI#
2
2
8.2K_0402_5% R315 GPIO14 10K_0402_5% 2 R42 MCH_SYNC#
1 60@
R295 R1370 R372
8.2K_0402_5% R316 GPIO15 8.2K_0402_5% GPIO7
1
0_0402_5%
8.2K_0402_5% R300 GPIO39 1K_0402_5%
8.2K_0402_5% R301 SMBALERT# 1 2
8.2K_0402_5% R368 EC_THERM#
1 1
Q30
8.2K_0402_5% R302 GPIO0 EC_RSMRST#R
+RTCVCC
C
D37 (17) EC_RSMRST# 3 1
1M_0402_5%
E
R146 BAV99DW-7_SOT363 @ MMBT3906_SOT23-3
1 2 INTRUDER# 8.2K_0402_5% R241 PM_CLKRUN#
B
1 2 +3VALW
1 2
R373 @ 4.7K_0402_5%
1 R197 2 INTVRMEN +RTCVCC
2
332K_0402_1% R374
3
2
D28B
@ 2.2K_0402_5% @
BAS40-04_SOT23-3 @ D28A
1 R196 RTCRST#
om
+RTCVCC 2 +CHGRTC
20K_0402_5% BAV99DW-7_SOT363
1
C368 1
A C1148 R375 A
l.c
1 2
12P 50V J NPO 0402 Routing the trace at least 10mil
2 R1184 @1 0_0402_5% RTCX1
0.1U_0402_16V4Z
ai
2 1 2 @ 2.2K_0402_5%
tm
10M_0402_5%
Y3
1
32.768K_1TJS125BJ4A421P
C230
ho
R288
1U_0603_10V4Z~D 2 NC IN 1
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
1 2
3 4
NC OUT Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
2
in
12P 50V J NPO 0402 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 1 RTCX2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom D
401793
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 13 of 32
5 4 3 2 1
5 4 3 2 1
TGP
U72E
D D
F12 +V5REF_RUN 6mA
VCC5REF
U72F TGP
F5 +V5REF_SUS 10mA
+5VS +3VS VCC5REF_SUS
VSS01 A1
Y6 +SATAPLL 50mA A25
VCCSATAPLL VSS02
VSS03 B6
1
0.01U_0402_16V7K
R33 D12
0.1U_0402_16V4Z
VSS05 B16
RB751V-40_SOD323-2 Y25 +DMIPLL B20
VCCDMIPLL VSS06
C42
C47
100_0402_5% 1 1 B24
+VCCP VSS07
F6 10mA E18
2
VCCUSBPLL VSS08
VSS09 F16
+V5REF_RUN G4
2 2 VSS10
VSS11 G8
1 V_CPU_IO W18 14mA 1 VSS12 H1
C59 H4
C41 0.1U_0402_16V4Z VSS13
VSS14 H5
1U_0603_10V6K K4
2 2 VSS15
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCC1_5_1 AA8 1.3A VSS16 K8
1U_0603_10V6K
1U_0603_10V6K
VCC1_5_2 M9 +1.5VS VSS17 K11
VCC1_5_3 M20 VSS18 K19
POWER
C48
C45
C61
C62
C459
VCC1_5_4 N22 1 1 1 1 1 VSS19 K20
VSS20 L4
VSS21 M7
+5VALW +3VALW M11
2 2 2 2 2 VSS22
VSS23 N3
2
VSS24 N12
1
C D10 C
0.1U_0402_16V4Z
J10 0.98A +VCCP N13
10U_0805_10V4Z
VCC1_05_1 VSS25
1U_0603_10V6K
1U_0603_10V6K
R35 RB751V-40_SOD323-2 K17 N14
VCC1_05_2 VSS26
C46
C60
C63
C460
VCC1_05_3 P15 1 1 1 1 VSS27 N23
10_0402_5% V10 P11
1
VCC1_05_4 VSS28
P13
2
+V5REF_SUS VSS29
VSS30 P19
2 2 2 2
VSS31 R14
VSS32 R22
1 VCC3_3_1 H25 0.29A +3VS VSS33 T2
1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
C40
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCC3_3_2 AD13 VSS34 T22
C43
C37
C38
C461
C462
0.1U_0402_16V4Z F10 1 1 1 1 1 V1
VCC3_3_3 VSS35
VCC3_3_4 G10 VSS36 V7
2
VCC3_3_5 R10 VSS37 V8
VCC3_3_6 T9 VSS38 V19
2 2 2 2 2
VSS39 V22
VSS40 V25
VCCSUS3_3_1 F18 0.13A VSS41 W12
VCCSUS3_3_2 N4 VSS42 W22
VCCSUS3_3_3 K7 VSS43 Y2
VCCSUS3_3_4 F1 +3VALW VSS44 Y24
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V4Z
VSS45 AB4
VSS46 AB6
C39
C44
C463
1 1 1 VSS47 AB7
VSS48 AB8
VSS49 AC8
VSS50 AD2
2 2 2
5 VSS51 AD10
VSS52 AD20
TIGERPOINT_ES1_BGA360 VSS53 AD24
VSS54 AE1
B AE10 B
VSS55
VSS56 AE25
4.7U_0603_6.3V6K
TIGERPOINT_ES1_BGA360
+1.5VS
R29
+SATAPLL
0_0805_5%
1 1
C57 C27
10U_0805_10V4Z 0.1U_0402_16V4Z
A A
2 2
1
C1163 1 1 1
C1164 C1165
0.01U_0402_25V7K
4.7U_0603_6.3V6K
C1166
+3VS
47P_0402_50V8J
0.1U_0402_16V4Z
2
2 2 2
+3VS_WWAN
C411 BT@
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
1 1 1 1
1
Mini-Express Card for WWAN C505
0.1U_0402_16V4Z
C506
C507
C508
C850
47P_0402_50V8J (17) BT_ON# 2
R501
1
BT MODULE CONN
2 2 2 0.01U_0402_25V7K 2
2 10K_0402_5%
10U_0805_10V4Z
R4020_0402_5% BT@
EC_TX_P80_DATA 1 2 EC_TX_P80_DATA_R +3VS BT@ +3VS_BT
(17) EC_TX_P80_DATA
EC_RX_P80_CLK 1 2 EC_TX_P80_CLK_R Q35
(17) EC_RX_P80_CLK
R403 0_0402_5% AO3413_SOT23-3 BT@
+3VS_WWAN C502
+3VS_WWAN +3VALW
D
+3VS 3 1 2 1
1
@ 0.1U_0402_16V4Z
Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T 06/29 @ C403 +
G
1 2 1 2
2
R405 0_1206_5% R504 0_1206_5%
150U_B_6.3VM_R40M
+3VS_BT
2
Close to WWAN CONN
JMINI1
(13,20) ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2
1 2
3 3 4 4 JBT1
5 5 6 6 +1.5VS
(8) WWAN_CLKREQ# WWAN_CLKREQ# 7 8 +UIM_PWR 1
7 8 UIM_DATA 1
9 9 10 10 2 2
11 12 UIM_CLK (13) USB20_P6 USB20_P6 3 5
(8) CLK_PCIE_WWAN# 11 12 3 GND
13 14 UIM_RST (13) USB20_N6 USB20_N6 4 6
2 (8) CLK_PCIE_WWAN 13 14 4 GND 2
15 16 UIM_VPP
15 16
ACES 88266-04001
17 18 CONN@
17 18 WXMIT_OFF#
19 19 20 20 WXMIT_OFF# (17)
21 22 R506 1 2 0_0402_5%
21 22 PLTRST# (4,5,13,17,20)
(13) PCIE_DTX_C_IRX_N3 23 23 24 24
(13) PCIE_DTX_C_IRX_P3 25 25 26 26
27 28 R507 0_0402_5%
Change to PCIE_P3 05/13 27 28
29 29 30 30 1 2 NON3G@ CLK_SMBCLK (7,8)
(13) PCIE_ITX_C_DRX_N3 31 31 32 32 1 2 NON3G@ CLK_SMBDATA (7,8)
33 34 R508 0_0402_5%
(13) PCIE_ITX_C_DRX_P3 33 34
35 35 36 36 USB20_N5 (13)
37 37 38 38 USB20_P5 (13)
+3VS_WWAN 10U_0805_10V4Z 39 40
39 40
1
C504
2 41 41 42 42 WWAN_LED# (16,20) (9~16mA)
43 43 44 44 1 2 WLAN_LED# (16,20)
D15 WWAN_WAKEUP_R# 45 46 R511 0_0402_5%
@ CM1293-04SO_SOT23-6 45 46
47 47 48 48 NON3G@
UIM_VPP 1 CH1 UIM_DATA EC_TX_P80_DATA_R
CH4 4 EC_TX_P80_CLK_R
49 49 50 50
51 51 52 52
53 GND1 GND2 54
2 Vn Vp 5 +UIM_PWR 55 NC NC 56
+3VALW
BELLW_80052-1021
UIM_RST 3 6 UIM_CLK CONN@
1
CH2 CH3
R509
JP3 10K_0402_5%
4 1 +UIM_PWR
3 UIM_VPP GND VCC UIM_RST 3
5 2
2
UIM_DATA VPP RST UIM_CLK @
6 I/O CLK 3
(17) WWAN_WAKEUP# 1 2 WWAN_WAKEUP_R#
7 DET R510 0_0402_5%
22P_0402_50V8J
C1116
0.1U_0402_16V4Z
1 1
22P_0402_50V8J
22P_0402_50V8J
1 1 1 1 1 1 1
3G@ C1118
56P_0402_50V8
1
10K_0402_5%
C509
1 C512
C510
R12
C511
C513
C1115
56P_0402_50V8
56P_0402_50V8
2 8
C1117
2 GND
56P_0402_50V8
@ 9
1U_0402_6.3V6K
GND
C1114
2 2 2 2 2 2
56P_0402_50V8
@ @ @ 2
2
2
3G@
3G@
3G@
3G@
3G@
3G@
+UIM_PWR
TAITW_PMPAT6-06GLBS7N14N0 CONN@
om
4 4
l.c
ai
tm
ho
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/05 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 15 of 32
A B C D E
A B C D E F G H
1 1
+3VALW 1 1
(17) PWR_LED# 2 2
(17) PWR_SUSP_LED# 3 3
(17) BATT_GRN_LED# 4 4
(17) BATT_AMB_LED# 5 5
MEDIA_LED# 6
NUM_LED# 6
(17) NUM_LED# 7 7
(17) CAPS_LED# CAPS_LED# 8
BT_LED# 8
(17,20) BT_LED# 9 9
+3VS 10 10
11 11 GND 17
(15,20) WWAN_LED# 12 12 GND 18
(15,20) WLAN_LED# 13 13
14 14
15 15
16 16
ACES_85201-1605N
CONN@
+3VS
5
U29
2 B
P
(20) CARD_LED#
2 4 MEDIA_LED# 2
SATA_LED# Y
(12) SATA_LED# 1 A
G
NC7SZ08P5X_NL_SC70-5
3
3 3
CONN@
0.1U_0402_16V4Z
C514
0.1U_0402_16V4Z
C515
0.1U_0402_16V4Z
C516
0.1U_0402_16V4Z
C517
1000P_0402_50V7K
C521
1000P_0402_50V7K
C519
+3VALW 1 2 +EC_AVCC
MBK1608121YZF_0603 2 1
C518 R1292 +3VALW
C520 2 2 2 2 2 2
@
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U6 Ra
22
33
96
67
9
2
1 ECAGND 2
2 1
R1288 R1291
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
0_0402_5% 100K_0402_5%
10K_0402_5%
Change to R_0402 05/14 +3VS 2 R41 1 60@
1
1 21 PWR_PWM_LED#
(12) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F PWR_PWM_LED# (18)
2 23 BEEP# BRD_ID
(12) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (20)
(12) SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
2
4 27 ACOFF
(13) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (25)
LPC_AD3 5 R1292
(13) LPC_AD3 LAD3
LPC_AD2 7 PWM Output 50@ 33K +-5% 0402
(13) LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
(13) LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (24)
C522 LPC_AD0 BATT_OVP
(13) LPC_AD0 10 LAD0 LPC & MISC 64 BATT_OVP (25) Rb
1
BATT_OVP/AD1/GPIO39
2 1 2 1 ADP_I/AD2/GPIO3A 65 ADP_I (25)
R1289 @ 10_0402_5% 12 AD Input 66 BRD_ID
@ 22P_0402_50V8J
(8) CLK_PCI_LPC
(4,5,13,15,20) PLTRST#
EC_RST#
13
PCICLK
PCIRST#/GPIO05
AD3/GPIO3B
AD4/GPIO42 75 1
0_0402_5%
2
R1389
+0.89V_PG (28) BOARD ID Table
+3VALW 1 2 37 ECRST# SELIO2#/AD5/GPIO43 76
R1290 47K_0402_5% EC_SCI# 20
(13) EC_SCI# SCI#/GPIO0E
2 38 CLKRUN#/GPIO1D VCC 3.3V
C523 68
DAC_BRIG/DA0/GPIO3C EN_FAN1
EN_DFAN1/DA1/GPIO3D 70 EN_FAN1 (4) Ra 100K
0.1U_0402_16V4Z DA Output 71 IREF
1 IREF/DA2/GPIO3E IREF (25)
PLTRST# KSI0 55 72
KSI1 56
KSI0/GPIO30
KSI1/GPIO31
DA3/GPIO3F CALIBRATE# (25) ID BRD ID Rb Vab-Min Vab-Typ Vab-Max
KSI2 57 KSI2/GPIO32
1
470P_0402_50V7K
1 2 EC_SMB_CK1 @
2 2
4.7U_0603_6.3V6K
R1297 2.2K_0402_5% KB926QFD3_LQFP128_14X14 MX25L512AMC-12G_SO8
11
24
35
94
113
69
1 2 EC_SMB_DA1 @
R1298 2.2K_0402_5%
ECAGND
1 2 KSO1
R1299 47K_0402_5%
1 2 KSO2 +3VALW
R1300 47K_0402_5%
8M SPI ROM
1
C525 C526 20mils U76
C527 8 4
VCC VSS
1
OUT
W
+5VS
7 HOLD
JP25
TP_CLK FSEL#SPICS# 2 SPI_CS#
NC
NC
1 2 +3VALW 1 1 1 1 S
R1301 4.7K_0402_5% EC_TX_P80_DATA 2 R1302 22_0402_5%
TP_DATA EC_RX_P80_CLK 2 SPI_CLK SPI_CLK_R
1 2 3 2 1 6
2
om
CONN@ EN25F80-75HCP SOIC 8P
+3VS
l.c
C528
1 2 EC_SMB_CK2 BATT_OVP C529 1 2
ai
R1307 2.2K_0402_5% 100P_0402_50V8J 2 1 SPI_CLK_R
tm
1 2 EC_SMB_DA2 BATT_TEMP C530 1 2 10P_0402_50V8J
R1308 2.2K_0402_5% 100P_0402_50V8J
ACIN C531 1
ho
2
100P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
2006/08/04 2007/8/18 Title
f@
Issued Date Deciphered Date
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793
he
Date: Friday, May 21, 2010 Sheet 17 of 32
Add For NAV50 07/06
09/03 Change +5VS to +3VS
ON/OFF Button
+3VS 50@
SW1
3 4
(BLUE) ON/OFFBTN#
1
51 +-5% 0402 1 2
50@
R1388 EVQPLMA15 SPST PANASONIC H1.5
2
TOP Side
2
LED1 +3VALW
@
HT-191NB5-DT BLUE 0603
50@
FOR EMI R186 2
0_0805_5%
1
2
1
1
10mil Bottom Side D14
2 ON/OFF#
ON/OFF# (17)
ON/OFFBTN# 1
3 51ON#
51ON# (23)
PWR_PWM_LED# DAN202U_SC70
1
ON/OFFBTN# 2
C4 D1 @
1000P_0402_50V7K RLZ20A_LL34
1
3
D42
2
PJSOT24C_3P_C/A_SOT-23
50@
1
D
1
EC_ON 2 Q1
(17) EC_ON
G 2N7002W-T/R7_SOT323-3
2
S <BOM Structure>
3
R3
10K_0402_5%
1
PWR/B Conn LID Switch
+3VALW
+3VS
2 VDD
JP23
1 1 1 OUTPUT 3 LID_SW# (17)
ON/OFFBTN# 2 C155
2
10P_0402_50V8J
PWR_PWM_LED# 3 0.1U_0402_16V4Z 1
GND
(17) PWR_PWM_LED# 3
4 4 2 C150
5 G1
6 U5
1
G2 2
ACES_85201-0405N
APX9132ATI-TRL SOT-23 3P
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 18 of 32
5 4 3 2 1
To TP/B Conn.
D D
KSI[0..7]
KSI[0..7] (17) INT_KBD Conn. 1
JP11
KSO[0..15] +5VS 1
KSO[0..15] (17) 2 2
JKB1 TP_CLK 3
(17) TP_CLK 3
26 TP_DATA 4
G2 (17) TP_DATA 4
25 G1 5 5 GND 8
3
KSI0 24 6 7
KSI1 24 6 GND
23 23
KSI0 C136 1 2 100P_0402_50V8J KSO4 C104 1 2 100P_0402_50V8J KSI2 22
KSO0 22 ACES_85201-0605N
21 21
KSI1 C135 1 2 100P_0402_50V8J KSO5 C103 1 2 100P_0402_50V8J KSO1 20 D22
KSO2 20
19 19 CONN@
KSI2 C134 1 2 100P_0402_50V8J KSO6 C102 1 2 100P_0402_50V8J KSI3 18
KSO3 18
17 17
KSI3 C133 1 2 100P_0402_50V8J KSO7 C101 1 2 100P_0402_50V8J KSO4 16
1
KSO5 16 PJDLC05C_SOT23-3
15 15
KSI4 C132 1 2 100P_0402_50V8J KSO8 C100 1 2 100P_0402_50V8J KSO6 14
KSO7 14
13 13
KSI5 C131 1 2 100P_0402_50V8J KSO9 C99 1 2 100P_0402_50V8J KSO8 12
KSI4 12
11 11
KSI6 C127 1 2 100P_0402_50V8J KSO10 C98 1 2 100P_0402_50V8J KSO9 10
KSI5 10
9 9
KSI7 C126 1 2 100P_0402_50V8J KSO11 C97 1 2 100P_0402_50V8J KSI6 8
KSO10 8
7 7 Chage JP11 Pin define & Add D22 05/14
KSO0 C125 1 2 100P_0402_50V8J KSO12 C96 1 2 100P_0402_50V8J KSO11 6
KSI7 6
5 5
C KSO1 C124 1 100P_0402_50V8J KSO13 C95 100P_0402_50V8J KSO12 C
2 1 2
KSO13
4
3
4 Update TP/B Conn 05/04
KSO2 C114 1 100P_0402_50V8J KSO14 C93 100P_0402_50V8J KSO14 3
2 1 2 2 2
KSO15 1
KSO3 C113 1 100P_0402_50V8J KSO15 C92 100P_0402_50V8J 1
2 1 2
ACES_85202-24051
CONN@
B B
om
A A
l.c
ai
tm
ho
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 19 of 32
5 4 3 2 1
A B C D E
1 1
1
560_0402_5% 10 9 USB20_N7
D36 @ 10 9 USB20_N7 (13)
12 12 11 11 +3VALW
R1328 RB751V-40TE17_SOD323-2 14 13
(8) CLK_PCIE_WLAN 14 13
10K_0402_5% 16 15 USB_ON# (17)
(8) CLK_PCIE_WLAN# 16 15
+1.5VS 18 17
2
2 18 17 USB_OC#2 (13)
(17) EC_MUTE# 20 20 19 19 PLTRST# (4,5,13,15,17)
(17) EAPD 22 22 21 21 WWAN_LED# (15,16)
(16,17) BT_LED# 24 24 23 23 +1.5VS
MONO_IN_R 26 25
26 25 CARD_LED# (16)
(17) LAN_WAKE# 28 28 27 27 PCIE_DTX_C_IRX_P2 (13)
(17) WL_OFF# 30 30 29 29 PCIE_DTX_C_IRX_N2 (13)
(13,15) ICH_PCIE_WAKE# 32 32 31 31
(8) WLAN_CLKREQ# 34 34 33 33 PCIE_ITX_C_DRX_N2 (13)
2 2
(15,16) WLAN_LED# 36 36 35 35 PCIE_ITX_C_DRX_P2 (13)
38 38 37 37
(13) HDA_BITCLK_AUDIO 40 40 39 39 PCIE_DTX_C_IRX_N1 (13)
(13) HDA_SDOUT_AUDIO 42 42 41 41 PCIE_DTX_C_IRX_P1 (13)
(13) HDA_SDIN0 44 44 43 43
(13) HDA_RST_AUDIO# 46 46 45 45 PCIE_ITX_C_DRX_N1 (13)
(13) HDA_SYNC_AUDIO 48 48 47 47 PCIE_ITX_C_DRX_P1 (13)
50 50 49 49
52 51 USB20_N4
(8) CLK_PCIE_LAN 52 51 USB20_N4 (13)
(8) CLK_PCIE_LAN# 54 53 USB20_P4
54 53 USB20_P4 (13)
56 56 55 55
58 57 USB20_P2
+3VS 58 57 USB20_N2 USB20_P2 (13)
60 60 59 59 USB20_N2 (13)
+5VALW 62 61
GND GND
LOTES_YEA-BTB-006-260K12
+USB_VCCC
U13
C244 1 8
0.1U_0402_16V4Z GND VOUT
2 VIN VOUT 7
2 1 3 VIN VOUT 6
4 EN FLG 5 USB_OC#0_1 (13)
2
3 3
+USB_VCCC
W=40mils +USB_VCCC
W=40mils
1 1 1 1
C316 C318
C315 + C317 +
470P_0402_50V7K 470P_0402_50V7K
150U 6.3V M B LESR45M T520 H1.9 2 150U 6.3V M B LESR45M T520 H1.9 2
2 2
JUSB1 JUSB2
1 VCC 1 VCC
(13) USB20_N0 2 D- (13) USB20_N1 2 D-
(13) USB20_P0 3 D+ (13) USB20_P1 3 D+
4 GND 4 GND
2
3
5 GND1 5 GND1
6 GND2 6 GND2
7 GND3 7 GND3
8 D23 8
D21 GND4 GND4
SUYIN_020133GB004M25MZL SUYIN_020133GB004M25MZL
1
PJDLC05C_SOT23-3
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 20 of 32
A B C D E
Modify Hole location by (ME Drawing 06/12) 0615
H8 H20
H H
H_3P2X3P7N
@ @
1
H16 H9 H1
H H H
H_2P6
@ @ @
1
H7 H17
H H
@ @
1
H_3P2 @ @ @ @ @ @ @ FIDUCIAL_C40M80
1
1
H3
H
H_3P2
@
1
H11
H
om
H_3P2N
@
1
l.c
ai
tm
Compal Electronics, Inc.
ho
Security Classification Compal Secret Data
2006/08/18 2007/8/18 Title
f@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
in
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
D
xa
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401793
Date: Friday, May 21, 2010 Sheet 21 of 32
he
A B C D E
Change R51 R57 R70 R63 R317 R114 R190 to 0402 SIZE 04/30
Change C221 C218 C223 C 191 C201 C170 C392 C393 C394 to 0603 SIZE 04/30
2
6 3 1 1 6 3 1 1
5 C223 C219 470_0402_5% 5 C170 C176 470_0402_5%
1 1 1 1
C221 C218 C191 C201
10U_0603_6.3V6M R190 10U_0603_6.3V6M 1U_0603_10V4Z R114
4
10U_0603_6.3V6M 2 2
1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M 2 2
3 1
2 2 2 2
10U_0603_6.3V6M
3
Q12B
+VSB 1 2 5VS_GATE Q17B R139 2N7002DW-T/R7_SOT363-6 5 SUSP
R187 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 1 2
22K +-5% 0402 1 33K +-5% 0402
4
6
C208 1
6
C179
Q17A 0.1U 25V K X5R 0402
SUSP 2 Q12A 0.1U 25V K X5R 0402
2
2N7002DW-T/R7_SOT363-6 SUSP 2
2
2N7002DW-T/R7_SOT363-6
1
1
+5VALW
2
R141
100K_0402_5%
2 2
+1.8V to +1.8VS
1
+1.8V +1.8VS
SYSON#
SI4800BDY-T1-E3_SO8 Q27
8 1
7 2 1 1
2
6 3 C394 C395
6
470_0402_5%
1U_0603_10V4Z
1 1 5
C392 C393 10U_0603_6.3V6M ADD +5VS +VCCP +0.89V Cap for EMI
10U_0603_6.3V6M
2 2 R317
10U_0603_6.3V6M
Q14A
4
SYSON 2
(17,27) SYSON
1
2 2 2N7002DW-T/R7_SOT363-6
1
3
0.01U_0402_25V7K
0.01U_0402_25V7K
0.01U_0402_25V7K
200K +-1% 0402 1 2 2 2
0.01U_0402_25V7K
0.01U_0402_25V7K
C396
6
2 2
0.1U 25V K X5R 0402
Q28A 2
SUSP 2
2N7002DW-T/R7_SOT363-6 +0.9VS
1
3 3
RTCVREF
VL
2
R172 R173
100K_0402_5% 100K_0402_5%
@
1
+1.5VS +VCCP +0.9VS +1.8V SUSP
(28) SUSP
2
3
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
4
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 22 of 32
A B C D E
A B C D
PR1
1M_0402_1%
1 2
VIN VIN
VS
1
1 1
VIN @PR2
@ PR2
10K_0402_5%
PR3
84.5K_0402_1%
PR6
8
PL1 PR4 PR5 22K_0402_5%
2
HCB2012KF-121T50_0805 0_0402_5% 10K_0402_5% PU1A 3 1 2
P
DC_IN_S1 PACIN +
1 2 1 2 2 1 1 0
(13,17) ACIN
1
- 2
1
G
PC1
SP02000GC00
1
LM358DT_SO8 PR7 1000P_0402_50V7K
4
PJP1 PD1 PC2 20K_0402_1%
2
1
1
6 4 PR8 RLZ4.3B_LL34 .1U_0402_16V7K
2
GND 4 PC3 PC4 PC5 PC6 10K_0402_5%
5 GND 3 3
2 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
2
1 1
2 2
Vin Dectector
Min. Typ Max.
- PBJ1 + +RTCBATT
H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
ML1220T13RE
45@
PJ1 PJ2
VIN +3VALWP 2 2 1 1 +3VALW +5VALWP 2 2 1 1 +5VALW
.1U_0402_16V7K
.1U_0402_16V7K
JUMP_43X118 JUMP_43X118
1
2
PC194
PC193
PD2
2
RLS4148_LL34-2
PD3
RLS4148_LL34-2
1
BATT+ 2 1
1
3 3
PR10 PR11
68_1206_5% 68_1206_5% PJ4
PJ3 +VCCPP 2 1
PR12 PQ1 2 1 +VCCP
+1.8VP 2 1 +1.8V
2
2 1
.1U_0402_16V7K
200_0603_5% JUMP_43X118
1
.1U_0402_16V7K
CHGRTCP 1 2 N1 3 1 JUMP_43X118
VS
PC196
PC195
2
1
2
1
PR13 PC13
100K_0402_1% 0.22U_0603_25V7K PC14
<BOM Structure> 0.1U_0402_25V6
2
PR14 TP0610K-T1-E3_SOT23-3
2
22K_0402_1%
1 2
(18) 51ON# PJ5
+0.89VP 2 2 1 1 +0.89V
.1U_0402_16V7K
JUMP_43X79
1
RTCVREF
1
PC197
PR15
2
200_0603_5%
PR16 PR17 PU2
560_0603_5% 560_0603_5% 3.3V
2
1 2 1 2 3 2 N2
OUT IN
+CHGRTC
om
1
GND PC19
l.c
4
PC18 G920AT24U_SOT89-3 1U_0603_25V6K 4
10U_0603_6.3V6M 1
ai
2
tm
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f@
Security Classification Compal Secret Data Compal Electronics, Inc.
2007/09/20 2008/09/20 Title
in
Issued Date Deciphered Date
SCHEMATICS, MB A5651
xa
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
he
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 23 of 32
A B C D
A B C D
VMB
PH1 under CPU botten side :
PJP2 PL2
1
1 HCB2012KF-121T50_0805
CPU thermal protection at 90 degree C 1
1
2 2 BATT_S1 1 2 BATT+ Recovery at 70 degree C
3 B/I
3 TS
4 4
1
5 EC_SMCA
5 EC_SMDA PC21 PC22 VS VL
6 6
7 1000P_0402_50V7K 0.01U_0402_25V7K VL
2
7
8 8
GND 9
GND 10
2
1
1
SUYIN_200275MR008G15QZR PC129 PR157 PR154
0.1U_0402_25V6 442K_0402_1% 150K_0402_1%
2
2
PR155 1 2
2
9.76K_0402_1%
1
PR21 PR22
2
100_0402_1% 100_0402_1% PR152
8
82.5K_0402_1%
1
1 2 3
P
+
1
G
1K_0402_5% PU3A
100K_0402_1%_NCP15WF104F03RC
2 1 +3VALWP
LM393DR_SO8
4
2
1U_0402_6.3V6K
PR27
1
PC130
1K_0402_1% PC131 PR153
PH1
1000P_0402_50V7K 150K_0402_1%
2 1 VL
2
2
2
2 2
BATT_TEMP (17)
1
PR156
150K_0402_1%
EC_SMB_CK1 (17)
2
EC_SMB_DA1 (17)
PQ3
B+ 3 1 +VSB VS
1
8
PR30
100K_0402_1% PC200 5
P
TP0610K-T1-E3_SOT23-3 0.1U_0402_25V6 +
7
2
O
6 -
G
PU3B
VL LM393DR_SO8
4
2
PR32
22K_0402_1%
2
3 3
PR34
1
100K_0402_1%
1
D
1
2 PQ4
(28) SPOK G 2N7002W-T/R7_SOT323-3
S
3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 24 of 32
A B C D
A B C D
B+
0.1U_0603_25V7K
1 1
5600P_0402_25V7K
2200P_0402_25V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
CSIP PR58
4
PC165
47K_0402_1%
1
0.1U_0603_25V7K
PQ12 PQ13 TP0610K-T1-E3_SOT23-3 1 2
VIN
1
PC52
PC50
PC53
PC54
DTA144EUA_SC70-3 PR221
PC51
PR60 3 1 2 1 DCIN PD10
2
P3
2
PR59 2 200K_0402_1% 1SS355TE-17_SOD323-2
1
100K_0402_1%
47K_0402_1% 10_0603_5% PR62 1 2 ACOFF
2
PQ14 10K_0402_1%
2
1
PR61
DTC115EUA_SC70-3
PR64
1 1
PD11 200K_0402_1%
1
2
PR63 2 FSTCHG 1 2 VIN
FSTCHG (17)
2
1
PD12 2 1 2 1
1SS355TE-17_SOD323-2 3 SUSP# PD13
1 2 6251VDD 100K_0402_1% SUSP# (17,24,29,30) PQ16 1SS355TE-17_SOD323-2
2.2U_0603_6.3V6K
BAS40CW_SOT-323 DTC115EUA_SC70-3 2 1 2
PC55
2 PR65
3
1
PQ15 10K_0402_5%
DTC115EUA_SC70-3 2 1 PU5 PC57
(17) FSTCHG
0.1U_0603_25V7K
0.1U_0603_25V7K
3
1
1
D DCIN PQ18D
1 2 1 24 2 1
3
VDD DCIN
1
1
100K_0402_1%
PC58
2 PC56 2 PACIN
G .1U_0402_16V7K 2N7002W-T/R7_SOT323-3
G
PR67
S PQ17 PR66 2 23 S
3
3
2N7002W-T/R7_SOT323-3 150K_0402_1% ACSET ACPRN PR68
20_0402_5%
2
2
6251_EN 3 22 1 2 CSON
EN CSON
5
PC59
0.047U_0603_16V7K PQ19
4 21 1 2 CSOP
1
CELLS CSOP PR69
2
PC60 6800P_0402_25V7K 20_0402_5% SIS412DN-T1-GE3_POWERPAK8-5 2
1 2 5 ICOMP CSIN 20 2 1 4
1
2
PQ20 D PR70
2 PC61 PR71 6.81K_0402_1% PC62 20_0402_5%
G 2N7002W-T/R7_SOT323-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2
1
PR73 VCOMP CSIP PR72 PL5
S <BOM Structure>
3
3
2
1
0.01U_0402_25V7K 1 2 100_0402_1% 2_0402_5% 8.2UH_FDV0630-8R2M=P3_3.7A_20% PR74 0.05_1206_1% BATT+
PC63 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
4.7_1206_5%
PR75 @ 100P_0402_50V8J
1
22K_0402_5% (17) ADP_I 2 3
PR76
PACIN 1 2 PC64 6251VREF 8 17 DH_CHG
(25) PACIN VREF UGATE
PR77 1 2 PR78 PC65
10U_1206_25V6M
10U_1206_25V6M
62K_0402_1% 0_0603_5% 0.1U_0603_25V7K PQ21
2 1 .1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
2
(17) IREF CHLIM BOOT
1
1
PQ22 PR79 4 SIS412DN-T1-GE3_POWERPAK8-5
1
PC67
PC68
0.01U_0402_25V7K
680P_0402_50V7K
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1
PC66
<BOM Structure>
2
1
1
PC69
3
2
1
2
100K_0402_1% PR81 11 14 DL_CHG
VADJ LGATE
2
20K_0402_1% PR82
2
4.7_0603_5%
2
12 13 PC70
3
1
GND PGND 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
3 3
Iada=0~1.58A(30W) VMB
CP = 85%*Iada ; CP = 1.343A
PR83
15.4K_0402_1%
1
CP mode 1 2
Vaclim=2.39*(20K/(20K+38.3K))=0.8199V (17) CALIBRATE#
2
VS PR84
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05) PR85 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
where Vaclm=0.8199V, Iinput=1.343A 31.6K_0402_1%
2
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
1
Per cell=3.5V
PC71
1
PR86
CC=0.3~1.76A
2
499K_0402_1%
IREF=1.62*Icharge
2
8
PR87 PU1B
IREF=0.486V~2.85V 10K_0402_1% LM358DT_SO8 5
P
+
1 2 7 0
3.24V==>2A (17) BATT_OVP 6
-
0.01U_0402_25V7K
4
1
PR88
PC72
VADJ-->VREF-->4.41V 105K_0402_1%
Charging Voltage
BATT Type CV mode
2
(0x15) VADJ--->Ground--->3.99V
om
2
Vcell=(0.175*VADJ+3.99)
l.c
4 4
ai
12600mV 12.60V
tm
ho
f@
Security Classification Compal Secret Data Compal Electronics, Inc.
2007/09/20 2008/09/20 Title
in
Issued Date Deciphered Date
- SCHEMATICS, MB A5651
xa
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
he
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401793 D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 25 of 32
A B C D
5 4 3 2 1
ISL6237_B+
ISL6237_B+
PL11 PR36
HCB2012KF-121T50_0805 0_0805_5%
1 2 1 2
B+
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
5
PC163
VL
5
PC29
PC30
PC32
PC33
PC34
PC164
D D
1
PC31
PQ5
2
SIS412DN-T1-GE3_POWERPAK8-5
2
2
1U_0402_6.3V6K
PC35 4
4.7U_0603_6.3V6M
4 0.1U_0402_25V6
1
PC36
PQ6
PC37
1
SIS412DN-T1-GE3_POWERPAK8-5 +5VALWP
3
2
1
1
2
3
PL4
PL3 4.7UH_FDVE0630-H-4R7M=P3_5.5A_20%
7
8.2UH_FDV0630-8R2M=P3_3.7A_20% PU4 PC38 2 1
1 2 1U_0402_6.3V6K
LDO
VIN
VCC
+3VALWP
3
33 TP PVCC 19 1 2
4.7_1206_5%
1
PQ7 DH3 26 15 DH5
UGATE2 UGATE1
PR38
PR37 PR39 0_0603_5% PR40 0_0603_5%
150U_B2_6.3VM_R45M
@ 61.9K_0402_1%
1 2
2
2
2
PR41 2 PC41
2
+
PC39
PR42
0_0402_5% PC40 0.1U_0603_25V7K
2
680P_0402_50V7K
150U_B2_6.3VM_R45M
0.1U_0603_25V7K 1
1
1
PC43
LX3 25 16 LX5
2
1
2 PHASE2 PHASE1 +
PC44
PC42 IRFH3707TRPBF_PQFN8-3
2
680P_0402_50V7K
2
DL3 23 18 DL5
1
LGATE2 LGATE1 PQ8 2
IRFH3707TRPBF_PQFN8-3
2
0_0402_5%
C 22 C
PGND
2
FB3 30 OUT2
PR44
@ PR43
10K_0402_1% 10
OUT1
VL 32
1
REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 REF
PC45 0.22U_0402_6.3V6K
BYP 9
8 LDOREFIN @ PR45 0_0402_5%
SKIP 29 2 1 VL
PR46 0_0402_5%
1 2
20 NC POK2 28
PD6 PR47
GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK (26)
VS EN_LDO POK1 PR49
2
200K_0402_1%
309K_0402_1%
2
PR48
14 12 ILM1 2 1
PC46 EN1 ILIM1
0.22U_0402_6.3V6K
1
27 31 ILIM2 2 1
GND
TON
1
EN2 ILIM2
1
B B
NC
PR50
PD7 VL SN0806081RHBR QFN 32P 249K_0402_1%
2VREF_ISL6237 2
21
2VREF_ISL6237
1U_0402_6.3V6K
1SS355TE-17_SOD323-2
2
2
PR53
2
PC47
806K_0603_1%
1
0_0402_5%
2 1 Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
Vlimit=(5E-06 * 309K)/10=154.5mV
(26) MAINPWON
0.047U_0402_16V7K
PC48
=8.631A ~ 8.879A
Iocp=Ilimit+Delta I/2
2
=9.611A ~ 9.859A
Delta I=1.960A (Freq=400KHz)
3
2 PQ9
TP0610K-T1-E3_SOT23-3
+3.3VALWP Ipeak=5.731A Imax=4.012A Iocp=6.877A
Rds(on)=17.9m ohm(max) ; Rds(on)=14.5m ohm(typical)
A A
Vlimit=(5E-06 * 249K)/10=124.5mV
1
5 4 3 2 1
A B C D
PL12
HCB2012KF-121T50_0805
1.8V_B+ 1 2 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
2200P_0402_50V7K
PC166
1
1
PC74
PC75
PC73
5
2
PR89
300K_0402_5% 4
1 1 2 1
3
2
1
1
1
PR92 PL6
15
14
1
30K_0402_5% PC77 PU6 PC76 2.2U_FDV0630-2R2M-P3_7.2A_20%
1U_0402_6.3V6K BST_1.8V-1 1 2 1 2
BOOT
NC
EN/DEM
+1.8VP
2
2
2 13 DH_1.8V 0.1U_0603_25V7K
TON UGATE
4.7_1206_5%
PR94 LX_1.8V
IRFH3707TRPBF_PQFN8-3
3 VOUT PHASE 12
PR93
100_0603_1% 1
PQ24
220U_B2_2.5VM
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS
PC78
PR95 +
2
5 10 8.66K_0402_1%
FB VDDP
1
2
680P_0603_50V7K
6 9 DL_1.8V 2
PGOOD LGATE
PGND
PC80
PC79
GND
4.7U_0603_6.3V6K
2
1
RT8209BGQW_WQFN14_3P5X3P5 PC82
1
4.7U_0805_10V6K
2
<Vo=1.8V> VFB=0.75V
PR96
Vo=VFB*(1+PR96/PR97)=0.75*(1+28.7K/20.5K)=1.8V 28.7K_0402_1%
Fsw=328KHz 1 2
1
Cout ESR=15m ohm Rdson(max)=17.9m Rdson(typical)=14.5m
2 Ipeak=4.97A, Imax=3.479A, Iocp=5.964A PR97 2
+VCCP_B+ 1 2 B+
Vtrip=Rtrip*10uA=8.66K*10uA=0.0866V
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
Iocpmin=Vtrip/(Rdsonmax)+1.129
=0.0866/(0.0179)+1.129=5.967A
PC167
1
1
PC84
PC85
Iocpmax=(0.0866/(0.0145*1.2))+1.129A=6.106A
PC83
5
Iocp=5.967A~6.106A
2
PR98
300K_0402_5% 4
1 2
PR99 PR100 PQ25
2K_0402_1% 0_0603_5%
1 2 BST_1.05V1 2 SIS412DN-T1-GE3_POWERPAK8-5
(17,24,27,30) SUSP#
3
2
1
1
14
1
+VCCPP
2
2
4.7_1206_5%
2 13 DH_1.05V
TON UGATE
330U_B2_2.5VM_R15M
PR102
PR103 3 12 LX_1.05V 1
VOUT PHASE
3
100_0603_1%
IRFH3707TRPBF_PQFN8-3
PC88
1 2 4 11 1 2 +5VALW +
+5VALW VDD CS PR104
2
3 3
5 10 14K_0402_1%
FB VDDP 2
1
1
PQ26
680P_0603_50V7K
6 9 DL_1.05V 2
PGOOD LGATE
PGND
PC90
PC89
GND
4.7U_0603_6.3V6K
2
2
1
RT8209BGQW_WQFN14_3P5X3P5 PC92
7
1
4.7U_0805_10V6K
PR105 2
8.2K_0402_1%
1 2
1
PR106
20.5K_0402_1%
<Vo=1.05V> VFB=0.75V
2
Vo=VFB*(1+PR105/PR106)=0.75*(1+8.2K/20.5K)=1.05V
Fsw=280KHz
om
=>1/2DeltaI=1.774A
Vtrip=Rtrip*10uA=14K*10uA=0.14V
l.c
4 4
Iocpmin=Vtrip/(Rdsonmax)+1.774
ai
=0.14/(0.0179)+1.774=9.596A
tm
Iocpmax=(0.14/(0.0145*1.2))+1.774A=9.820A
Iocp=9.596A~9.820A
ho
Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
xa
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
he
Date: Friday, May 21, 2010 Sheet 27 of 32
A B C D
5 4 3 2 1
PL14
HCB2012KF-121T50_0805
0.89V_B+ 1 2 B+
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0603_25V7K
PC168
1
1
PC93
PC94
PC95
5
2
PQ27
PR107
D
300K_0402_5% 4 D
(17,24,27,29) 1 2 <Vo=0.89V> VFB=0.75V
PR108 PR109
SUSP# 2K_0402_1% 0_0603_5% Vo=VFB*(1+PR114/PR115)=0.75*(1+28.7K/20.5K)=0.89V
1 2 BST_0.89V1 2 SIS412DN-T1-GE3_POWERPAK8-5 Fsw=263KHz
3
2
1
1
15
14
1
30K_0402_5% PC96 PU8 PC97 2.2U_FDV0630-2R2M-P3_7.2A_20%
1U_0402_6.3V6K BST_0.89V-1 1 2 1 2
Ipeak=1.38A, Imax=0.966A, Iocp=1.656A
BOOT
NC
EN/DEM
+0.89VP
2
Delta I=((19-1.8)*(1.8/19))/(2.2u*263K)=1.467A
2
2 13 DH_0.89V 0.1U_0603_25V7K
TON UGATE =>1/2DeltaI=0.7335A
4.7_1206_5%
PR112 LX_0.89V Vtrip=Rtrip*10uA=8.66K*10uA=0.0866V
IRFH3707TRPBF_PQFN8-3
3 VOUT PHASE 12
220U_B2_2.5VM
PR111
100_0603_1% 1 Iocpmin=Vtrip/(Rdsonmax)+0.7335
PQ28
+5VALW 1 2 4 11 1 2 +5VALW
VDD CS =0.0866/(0.0179)+0.7335=5.572A
PC98
PR113 +
2
5 10 8.66K_0402_1%
FB VDDP Iocpmax=(0.0866/(0.0145*1.2))+0.7335A=5.711A
1
1
2 Iocp=5.572A~5.711A
680P_0603_50V7K
6 9 DL_0.89V 2
(17) +0.89V_PG PGOOD LGATE
PGND
PC100
PC99
GND
1
10K_0402_5%
4.7U_0603_6.3V6K
2
2
1
PR215
RT8209BGQW_WQFN14_3P5X3P5 PC102
1
4.7U_0805_10V6K
2
2
PR114
3.74K_0402_1%
1 2 +3VALW
1
C C
PR115
20.5K_0402_1%
2
Ipeak=1.48A, Imax=1.036A
+1.8V
+5VALW
1
PC105
1U_0402_6.3V6K
2
1
PC106 PU10
4.7U_0805_6.3V6K 6 VPP
5 3
2
PR117 9
VIN
TP
VO
VO 4 +1.5VS
1
22U_0805_6.3V6M
.1U_0402_16V7K
10K_0402_5%
1
1 2 8 PR118 PC107
VEN
1
(17,24,27,29) SUSP#
PC108
PC198
7 2 0.01U_0402_25V7K
GND
<BOM Structure>
2
2
B PR119 PC109 G9731F11U_SO8
+1.8V B
1
@ 47K_0402_5% .1U_0402_16V7K
2
1
1
PR120
1.74K_0402_1%
PU11
2
1 6
VIN VCNTL
+3VALW
2 GND NC 5
1
PC111
1
PC110 3 7 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR121 VREF NC
2
1K_0402_1% 4 8
VOUT NC
9
2
TP
APL5336KAI-TRL SOP
.1U_0402_16V7K
PR122
+0.9VS
1
0_0402_5% PQ29 D
10U_0805_6.3V6M
PC112
.1U_0402_16V7K
(24) SUSP 1 2 2 PR123
1
PC199
G 1K_0402_1% Ipeak=1A, Imax=0.7A
2
1
PC114
S
3
PC113 2N7002W-T/R7_SOT323-3
2
.1U_0402_16V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793
Date: Friday, May 21, 2010 Sheet 28 of 32
5 4 3 2 1
A B C D E F G H
1 1
(5)
(5)
(5)
(5)
(5)
(5)
(5)
VR_ON (17)
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
+3VS
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PR194
4.7K_0402_1% +5VS
+CPU_B+ PL9
2
HCB2012KF-121T50_0805
2
PR195
PR196
PR197
PR198
PR199
PR201
PR202
PR203
PR204
0_0402_5% 1 2 B+
2200P_0402_50V7K
13211_PWRGD PR200
4.7U_0805_25V6-K
4.7U_0805_25V6-K
(5,8,13,17) VGATE 2
10_0603_1%
0.1U_0402_25V6
1
1
PC121
PC116
PC147
PC148
3211_EN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
2
2 2
1
3211_VCC
5
+3VS PU12 PC182
1U_0805_25V6K
32
31
30
29
28
27
26
25
2
PQ30
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
1
24 PR206 PC183 4
PR205 VCC 0_0603_5% 0.22U_0603_25V7K SIS412DN-T1-GE3_POWERPAK8-5
1 PWRGD
10K_0402_1%
BST 23 CPU_BOOST 1 2CPU_BOOST-1
1 2
1
2
2
3
2
1
1000P_0402_50V7K DRVH 2.2U_FDV0630-2R2M-P3_7.2A_20%
(8) CLK_ENABLE# 3
2
1
ADP3211AMNR2G_QFN32_5X5 20 +5VS
PVCC
5
1 2 3211_FB 5 FB 3211_DRVL PR124
DRVL 19 2 1
1
2
PGND 2.2U_0603_10V6K
7
2
1 2 1 23211_COMP-1
1 2
GPU
17 4
OCP=7.85A
AGND
1
3211_ILIM 8 VID:0.75V~1.1V
CSCOMP
AGND Io(max)=6.04A
RAMP
LLINE
CSFB
RPM
2
RT
3
2
1
9
10
11
12
13
14
15
16
2
PR209
2.37K_0402_1%
3211_IREF
3211_RAMP
3211_RT
3211_CSCOMP
3211_CSFB
3211_CSCOMP
2 3211_RPM
PH4
3211_CSCOMP 1
100K_0402_1%_NCP15WF104F03RC
80.6K_0402_1%
1 2
200K_0402_1%
274K_0402_1%
2
2
PR210
PR212
499K_0402_1%
2 1
1
1
2
PR214
PR150 PR158
1
PC189 75K_0402_1%
1
1000P_0402_50V7K
2
PR219 2 1
1K_0402_1%
+CPU_B+ 2 1 3211_RAMP-1 PR218
309K_0402_1%
(6) VSSSENSE
(6)VCCSENSE
PC191 PC192
1000P_0402_50V7K 1000P_0402_50V7K
2
Shortest the
net trace
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Security Classification Compal Secret Data Compal Electronics, Inc.
2007/09/20 2008/09/20 Title
in
Issued Date Deciphered Date
SCHEMATICS, MB A5651
xa
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
he
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 29 of 32
A B C D E F G H
5 4 3 2 1
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D
5 change PL3,PL4 For design change 0.1 26 change PL3,PL4 to 4.7uH 2009.5.15 EVT
6 change PQ10,PQ11 For design change 0.1 25 change PQ10,PQ11 to P-Chanel 2009.6.5 EVT
12 change PR94,PR102 For design change 0.1 27 change PR94,PR102 to 100ohm 2009.6.5
13 change PC79,PC89 For design change 0.1 27 change PC79,PC89 to 4.7uF 2009.6.5
14 change PR112 For design change 0.1 28 change PR112 to 100ohm 2009.6.5
15 change PC99 For design change 0.1 28 change PC99 to 4.7uF 2009.6.5
B B
16 change +5VALW/+3VALW OCP For design change 0.1 26 change PR49 to 309ohm & PR50 to 249ohm 2009.6.5
19 Change net name For design change 0.1 25 Change net name +1.05V to +VCCP 2009.6.15
20 Change PJP2 For design change 0.1 24 Change PJP2 to DC040903020 2009.6.15
21 Change PBJ1 For design change 0.1 23 Change PBJ1 to SP020008Y00 2009.6.15
A A
23 Change net name For design change 0.1 29 Change net name GND_SIGNAL to GND 2009.6.18
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D D
1 Change PR194 For design change 0.1 29 change PR194 to 4.7K ohm 2009.6.30 EVT
3 Change PR4 For design change 0.1 23 change PR4 to 0 ohm 2009.7.2 EVT
4 Change PJP3 to PBJ1 For design change 0.1 23 change SP020008Y00 to SP093MX000 2009.8.4 EVT
5 Change PH1 & PH4 For design change 0.1 24 change SL210031F00 to SL200000V00 2009.8.12 EVT
6 Change PL10 For design change 0.1 29 change SH000006I80 to SH000000700 2009.8.12 EVT
7 Change PR99 & PR108 Modify power sequence 0.1 27 change SD028000080(0 ohm) to SD034200280(20K ohm) 2009.8.12 EVT
C 8 Change PR90 Modify power sequence 0.1 27 change SD028000080(0 ohm) to SD034100280(10K ohm) 2009.8.12 EVT C
9 Change PR83 Modify ISL6251 Charger KV 0.1 25 change SD034182280(18.2 ohm) to SD034154280(15.4K ohm) 2009.8.24 EVT
10 Change PR117 Modify power sequence 0.1 28 change SD028000080(0 ohm) to SD034100280(10K ohm) 2009.8.24 EVT
11 Change PR99 & PR108 Modify power sequence 0.1 27 change SD034200280(20K ohm) to SD034200180(2K ohm) 2009.8.24 EVT
12 Change PR90 Modify power sequence 0.1 27 change SD034100280(10K ohm) to SD034100180 (1K ohm) 2009.8.24 EVT
Change PC77 & PC86 & PC96 to pop
13 Change PC77 & PC86 & PC96 Modify power sequence 0.1 27 change SE076104KM8(0.1uf) to SE000000K80 (1uf)
2009.8.24 EVT
14 Change PC109 Change part number 0.1 27 change SE076104KM8(0.1uf) to SE076104K80(0.1uf) 2009.8.24 EVT
15 Change PL3.PL4 To slove high frequency noise 0.1 26 change SH00000BU00(4.7uH) to SH00000BS00(8.2uH) 2009.8.27 EVT
B B
16 Change PL9 For design change 0.1 29 change SM01000BY00 to SM01000C000 2009.9.4 DVT
17 Change PL4 To improve +5VALWP efficiency 0.1 26 change SH00000BS00(8.2uH) to SH00000F900(4.7uH) 2009.9.10 DVT
18 Change PR209 Modify CPU CORE OCP 0.1 29 change SD028180180(1.8K ohm) to SD034237180 (2.37K ohm) 2009.9.30 PVT
19
20
21
22
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A A
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Security Classification Compal Secret Data Compal Electronics, Inc.
f@
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
SCHEMATICS, MB A5651
in
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
xa
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401793 D
he
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, May 21, 2010 Sheet 31 of 32
5 4 3 2 1
5 4 3 2 1
<2009/4/28>
Update new power schematic, <2009/06/10> <2009/07/03>
release first version NAV50 schematic . Page 7- Add C116 @ . Page18 Add D41.2 to PWR_PWM_LED#
. Page 22- Modify USB_OC#1_2 to USB_OC#2 . Page8 Change co-lay net name to +1.5VM_CK505
<2009/04/29> . Page 17- Modify PLTRST# to PCI_RST# . Page20 Change JP2 Pin42 to +5VS
. Add R1182 R1183 L3 on page 9 . Page 17- Add @ on R1311
. Change J3 to R1184 on page 13 <2009/07/06>
<2009/04/30> . Page18 Add pwr switch for NAV50
. Change JDIM1 to SP07F001720 on page 7 <2009/06/12>
. Del SATA1 Port on page 12 . Page4 Add C314 C313 C1150 D19 on +VCC_FAN1
. Change R51 R57 R70 R63 R317 R314 R190 to 0402 Size on page 21 . Page8 Add C1145 C1146 C1147 <2009/07/08>
D
. Page10 Move CRT_DET# from Page13 to Page10 . Page5 Add 470pf on H_SMI# for known issue. D
<2009/05/04> . Page13 Add +RTCVCC circuit
. Add WWAN_CLKREQ# and R107 pull-high to +3VS on page 8
. Add CRT_DET# on page 10 <2009/06/15>
. Add CRT_DET# circuit on page 13 . Update New Power schematic (change PBJ1 to PJP3) <DVT START>
. Add 3 LEDS on page 16 . Page 10 modify C310 C308 C303 C307 C306 C304 Bom Structure <2009/08/04>
. Add BT/BTN Board CONN. on page 16 . Page 22 Modify Hole location by (ME drawing 06/12) . Page5 CLK_CPU_HPLCLK CLK_CPU_HPLCLK# exchange
. Update TP/B CONN. to SP01000LB00 on page 19 . Page9 Change JLVDS1 to P/N ACES 88341-3001 30P
<2009/06/16> . Page17 del PM_1.8V(U6.82) ,Del R1310 R1311
<2009/05/11> . Page7 Modify DDR Command Control Pin pull-high Resister location . Page18 Del D41
. Add INVT_PWM on Page 5 . Page9 Change R577 to 0402 type
. Del R323 on page 5
. C74 change to 2.2U_0603 on page 6
. C267 change to 22U on page 6
. C391 change to 0.1U on page 6 <2009/06/17>
. Del C67 C35 C33 C36 on page 6 . Update New Power schematic 06/17 <2009/09/03>
. Del +LGI_VID and U71.A21 direct connect to +VCCP on page 6 . Page9 modify LVDS Conn. Pin define . Page7 Change C112 to 0402 type
. Follow Intel checklist, add R52 on FSB on page 8 . Page9 Del C1110 . Page8 Add T6 on CLK_48M_CR
. Add D5 D7 D8 on page 4 . Page4 Add EMI solution D38 D39 D40 . Page16 Modify JP18 Pin define change +5VALW +5VS to +3VALW +3VS
. Add R174 on page 9 . Page20 Change Pin 18, 23 to +1.5VS change Pin7 , 9 to USB20_P7 N7
. Add PCI_RST# on page 11 <2009/06/18>
. Update New Power schematic 06/18 . Page21 Del H12
. Add C1115 C1114 C1116 C1117 C1118 on page 15
. Page8 modify U4 Pin define and Q31
. Page13 Add R1376, R1377 <2009/09/08>
C
<2009/05/12> . Page15 Modify C403 Update Power schematic 0904 C
. Follow Intel Layout Checklist, Add C141 on VDDSPD on page 7 . Page23 Modify H11 . Page18 Change R1388 to 100 ohm 0402
. Modify SRC CLK PORT LIST on page 8 . Page18 Change LED1 to SC591NB5A00
. Del CLKREQ_LAN# on page 8 <2009/06/19>
. Change PCIE Port list on page 13 . Page4 Add new signal CPU_ITP , CPU_ITP# <2009/09/10>
. Change USB Port list on page 13 . Page5 ADD R1378 Update Power schematic 0910
. Add W/L 3G SW on page 16 . Page6 ADD C1152,C1153,C1154 C1160,C1161,C1162 . Page22 unmount Q6 Q8
. Del R103 on page 18 . Page7 DDR_A_D8與DDR_A_D9互換
. Page8 ADD R1379,R1380,U77,R1381,C1157,R1382,R1383,R1384,C1157
<2009/05/13> , Page8 DEL C390
. Change JMINI1 to PCIE Port 3 on page 15 . Page9 ADD C1156
. Page11 DEL R1322, R1154
<2009/05/14> . Page13 DEL U77, ADD C1158 <2009/10/07>
. Page8 Change C174 C175 to 10U_0603 . Page17 ADD C1159 . Page4 U71 Change to SA00003M800
. Page6 R26 Change to SHI00009C00
<2009/05/14> . Page13 R152 Change to SD034200A80
. Update New Power schematic <2009/06/22> . Page18 R1388 Change to SD028510A80
. Del R376 R377 on page 8 . Page22 change IO Conn. pin34 from 48M to USB_ON#
. Del D5 D7 D8 on page 4 . Page10 change JCRT1 P/N to SP010906182
. Change JLVDS1 to SP010006810 on page 9 <2010/04/29>
. Add D6 for EMI on page 9 <2009/06/23> update new bom
. Change C1106 to C_0603 type on page 9 . Page15 Add C1163 C1164 C1165 C1166
. Change USB_OC# on page 13 . Page18 change PWR/B Conn. P/N to SP01000H300
B
. Add USB Port2 on page 20 . Page22 change JUSB1 JUSB2 P/N B
. Change JP11 Pin define & Add D22 on page 19
. Change C512 to 1u_0402 on page 15 <2009/06/24>
. Add U29 (MEDIA_LED#)) on page 16 . Page8 Change C1350 C1351 to 0402 type
. Page10 Add R1385 R1386 on JVGA_HS JVGA_VS
<2009/05/19>
.Update new clock GEN co-lay schematic on page 8
<2009/06/25>
<2009/06/05> . Page22 move some parts to I/O Board , Add the MONO_IN_R on M/B
.Update new clock GEN co-lay schematic on page 8 .
.Follow Intel check list change C161 C165 to 27P on page 8
.Follow Intel check list change C56 to 22uF on page 6
<2009/06/29>
<2009/06/08> . Page16 Change JP24 to ACES_88266_05001
.Update New Power schematic 06/06 version . Page15 Change JMINI1 to FOX_AS0B246-S50U-7F_52P-T
Page 13- a.Del R203 (pull-up GPIO6 Resister)
b.Change R1184 NU <2009/06/30>
Page 17- a. Add VGATE . Page18 Change PWR_LED# to PWR_PWM_LED#
b. Del R1294 . Page17 Add PWR LED DETECT PIN on Pin97
c. Change D30 NU
d. Change R1295 to 0 ohm <2009/07/02>
e. Add R1309 0 ohm on EC_RSMRST# . Update New Power schematic 07/02
f. Pull-up LAN_WAKE# +3VALW . Page9 Add C1167 C1168 for RF request.
A A
g. ICH_POK change to PCH_POK . Page13 Change R223 to 100K
h. Pull-up KB_RST# to +3VS . Page16 change JP24 to ACES_85201-0505N
Page 10- a. Add R1283 R1284 ,Change R247 R249 to 10 ohm . Page17 Del R1387 R1388 on EC Pin97
b. Add @ on U10 U11 C301 C298 . Page17 Add New Board ID to separate NAV50 NAV60
c. Del C302 C300 R1281 R1287 . Page17 Change 展頻IC to SA00003J400 (New)
. Page18 Add D41 for ESD Compal,Electronics,lnc
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL,INC. AND CONTAINS CONFIDENTIAL AND TRADE SCHEMATICS, MB A5651
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF COMPETENT DIVISION OF R&D DEPARTMENT Size Document Number Rev
EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR Custom
DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401793 D
Date: Friday, May 21, 2010 Sheet 32 of 32
5 4 3 2 1