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Power MOSFET
30 V, 40 A, Single N--Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
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• Optimized Gate Charge to Minimize Switching Losses
• These are Pb--Free Devices
V(BR)DSS RDS(ON) MAX ID MAX
Applications
13 mΩ @ 10 V
• CPU Power Delivery 30 V 40 A
• DC--DC Converters 24 mΩ @ 4.5 V
13NG
YWW
48
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
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NTD4813N
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NTD4813N
60 60
10 V TJ = 25°C VDS ≥ 10 V
6V 4.5 V
ID, DRAIN CURRENT (AMPS)
40 40
4V
30 30
3.8 V
20 3.6 V 20
TJ = 125°C
10 10 TJ = 25°C
3V TJ = --55°C
0 0
0 1 2 3 4 5 1 2 3 4 5 6 7
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) VGS, GATE--TO--SOURCE VOLTAGE (VOLTS)
Figure 3. On--Resistance vs. Gate--to--Source Figure 4. On--Resistance vs. Drain Current and
Voltage Gate Voltage
RDS(on), DRAIN--TO--SOURCE RESISTANCE
1.8 100,000
ID = 30 A VGS = 0 V
1.7
VGS = 10 V TJ = 150°C
1.6
1.5 10,000
IDSS, LEAKAGE (nA)
1.4
(NORMALIZED)
1.3 TJ = 125°C
1.2 1000
1.1
1.0
0.9 100
0.8 TJ = 25°C
0.7
0.6 10
--50 --25 0 25 50 75 100 125 150 175 5 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS)
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NTD4813N
1000 15
700 10.5
600 9
500 7.5
400 6
Q1 Q2
300 4.5
Coss ID = 30 A
200 3 VDD = 15 V
100 1.5 VGS = 11.5 V
Crss TJ = 25°C
0 0
0 5 10 15 20 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC)
100 30
IS, SOURCE CURRENT (AMPS) VGS = 0 V
tr 25 TJ = 25°C
20
t, TIME (ns)
td(off)
10 15
td(on)
10
tf VDD = 15 V
ID = 30 A 5
VGS = 11.5 V
1 0
1 10 100 0.5 0.6 0.7 0.8 0.9 1.0
RG, GATE RESISTANCE (OHMS) VSD, SOURCE--TO--DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage vs. Current
Variation vs. Gate Resistance
1000 80
EAS, SINGLE PULSE DRAIN--TO--SOURCE
VGS = 20 V ID = 12 A
I D, DRAIN CURRENT (AMPS)
SINGLE PULSE 70
TC = 25°C
AVALANCHE ENERGY (mJ)
60
100
10 ms 50
40
100 ms
30
10
1 ms 20
RDS(on) LIMIT
THERMAL LIMIT 10 ms 10
PACKAGE LIMIT dc
1 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN--TO--SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy vs.
Safe Operating Area Starting Junction Temperature
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NTD4813N
100
0.1
1 10 100 1000
PULSE WIDTH (ms)
1.0
D = 0.5
0.2
(NORMALIZED)
0.1
ORDERING INFORMATION
Device Package Shipping†
NTD4813NT4G DPAK 2500 / Tape & Reel
(Pb--Free)
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NTD4813N
PACKAGE DIMENSIONS
NOTES:
C 1. DIMENSIONING AND TOLERANCING PER ASME
A Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
E A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN
DIMENSIONS b3, L3 and Z.
b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
4 5. DIMENSIONS D AND E ARE DETERMINED AT THE
L3 Z OUTERMOST EXTREMES OF THE PLASTIC BODY.
D 6. DATUMS A AND B ARE DETERMINED AT DATUM
DETAIL A H PLANE H.
1 2 3
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
L4 A 0.086 0.094 2.18 2.38
b2 A1 0.000 0.005 0.00 0.13
b c b 0.025 0.035 0.63 0.89
b2 0.030 0.045 0.76 1.14
e 0.005 (0.13) M C H b3 0.180 0.215 4.57 5.46
c 0.018 0.024 0.46 0.61
GAUGE SEATING c2 0.018 0.024 0.46 0.61
L2 PLANE C PLANE D 0.235 0.245 5.97 6.22
E 0.250 0.265 6.35 6.73
e 0.090 BSC 2.29 BSC
H 0.370 0.410 9.40 10.41
L
A1 L 0.055 0.070 1.40 1.78
L1 L1 0.108 REF 2.74 REF
L2 0.020 BSC 0.51 BSC
DETAIL A L3 0.035 0.050 0.89 1.27
ROTATED 90° CW L4 ------ 0.040 ------ 1.01
Z 0.155 ------ 3.93 ------
STYLE 2:
SOLDERING FOOTPRINT* PIN 1. GATE
2. DRAIN
3. SOURCE
6.20 3.00 4. DRAIN
0.244 0.118
2.58
0.102
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NTD4813N
PACKAGE DIMENSIONS
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
A
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
SEATING PLANE D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
W K F 0.037 0.043 0.94 1.09
G 0.090 BSC 2.29 BSC
F H 0.034 0.040 0.87 1.01
J J 0.018 0.023 0.46 0.58
G K 0.134 0.142 3.40 3.60
H
R 0.180 0.215 4.57 5.46
D 3 PL V 0.035 0.050 0.89 1.27
0.13 (0.005) W W 0.000 0.010 0.000 0.25
B C NOTES:
1. DIMENSIONING AND TOLERANCING PER
V R E ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
--T-- F 0.037 0.045 0.94 1.14
SEATING G 0.090 BSC 2.29 BSC
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
J S 0.025 0.040 0.63 1.01
F V 0.035 0.050 0.89 1.27
H
Z 0.155 ------ 3.93 ------
D 3 PL
STYLE 2:
G 0.13 (0.005) M T PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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