VLSI Lab Manual

Experiment No: 1 Date:

Design and Implementation of an Inverter
Aim: To design schematic and draw the layout for a CMOS inverter using Mentor Graphics
Software.
Apparatus: Personal computer and Mentor Graphics Software.
Theory:
Complementary MOSFET technology is widely used today to form circuits in various
applications. Today’s computers CPUs and cell phones make use of CMOS due to several
key advantages. CMOS offers low power dissipation, relatively high speed, high noise
margins in both states, and will operate over a wide range of source and input voltages. The
CMOS circuit is a combination of both pMOS and nMOS circuits. When low voltage is
applied at the input then the pMOS network will be on and nMOS network will be off, and
vice-versa.
Procedure:
1. LPU=2U
WPU=10U
LPD=2U
WPD=5U
2. Set Delay value to 0S, width = 20nS, Period = 50nS for the voltage Source.
3. Set DC Value to 5V. 4. Maintain Width of 4U for Layout
Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subckt INVNOT Y A
MN1 Y A GROUND VSS N L=2u W=5u M=1
MP1 Y A VDD VDD P L=2u W=10u M=1
.end INVNOT
MAIN CELL: Component pathname: /root/invnot/invnot_sim
V2 VDD GROUND DC 5V
V1 A GROUND PULSE ( 0V 5V 0S 1nS 1nS 20nS 50nS )
X_INVNOT1 Y A INVNOT
.end
Layout diagram:

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 VLSI Lab Manual

Waveforms:

Transient response:

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Experiment No: 2 Date:

Design and implementation of universal gates
Aim: To design a schematic and draw the Layout for a two input CMOS NAND and NOR
gates using Mentor Graphics Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory: NAND gate is an universal logic gate in which, if any one of the input is ‘Logic 0’
or ‘Logic low’ then the output is ‘Logic 1’ or ‘Logic high’ otherwise equals to Logic 0’ or
‘Logic Low’. It is used to perform logical operations and is used to implement any other logic
gates.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U for all transistors of the
Circuit Diagram
2. Apply Pattern = 11010001 to V1 and Pattern = 00011011 to V2.
3. Keep Vhi = 5 and Vlo = 0 for V1 and V2.
4. Apply DC Voltage of 5V.
NAND GATE
Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktNANDGATE2 Y A B
MN2 N$7 B GROUND VSS N L=0.35u W=1.4u M=1
MN1 Y A N$7 VSS N L=0.35u W=1.4u M=1
MP2 Y A VDD VDD P L=0.35u W=1.4u M=1
MP1 Y B VDD VDD P L=0.35u W=1.4u M=1
.ends NANDGATE2
MAIN CELL: Component pathname: /root/nandgate2/nandgate2_sim

V3 VDD GROUND DC 5V
V2 A GROUND PATTERN 5 0 0 1n 1n 50n 00011011
V1 B GROUND PATTERN 5 0 0 1n 1n 50n 11010001
X_NANDGATE21 Y A B NANDGATE2
End
Waveforms:

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NOR GATE
Circuit diagram:

Test bench diagram:

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Net list:
.subckt NOR100 Y A B

M4 Y A GROUND GROUND N L=0.35u W=1.4u M=1

M3 Y B N$2 N$2 P L=0.35u W=1.4u M=1

M2 Y B GROUND GROUND N L=0.35u W=1.4u M=1

M1 N$2 A VDD VDD P L=0.35u W=1.4u M=1

.ends NOR100

MAIN CELL: Component pathname : /root/nor100/nor100_sim

V3 B GROUND PATTERN 5 0 0 1n 1n 50n 0001101101101011

V2 A GROUND PATTERN 5 0 0 1n 1n 50n 10101010101010

V1 VDD GROUND DC 5V

X_NOR1002 Y A B NOR100

.end

Waveforms:

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 VLSI Lab Manual

Experiment No: 3 Date:

Design and implementation of full adder
Aim: To design a schematic and draw the Layout for a Full Adder using Mentor Graphics
Software.
Apparatus: Personal computer and Mentor Graphics Software.
Theory:
A logic circuit which performs the addition of three onebit binary numbers at a time is
known as a full adder. The function of the circuit is to add three binary digits and producing
two outputs called sum and carry. Hence the basic difference between full adder and half
adder is, a full adder accepts an additional input that allows for handling input carriers. The
carry is produced with an OR gate.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U forall transistors of the
Circuit Diagram.
2. Apply Pattern = 11001100 for V1, Pattern = 11110000 for V2 andPattern = 10101010 for
V3.
3. Keep Vhi = 5 and Vlo = 0 for V1,V2 and V3.
4. Apply DC Voltage of 5V.

Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktFULLADD COUT SUM A B C
MP9 N$90 N$99 N$68 VDD P L=0.35u W=1.4u M=1
MP10 N$105 A N$68 VDD P L=0.35u W=1.4u M=1
MP11 N$106 B N$105 VDD P L=0.35u W=1.4u M=1
MN6 N$90 N$99 N$54 VSS N L=0.35u W=1.4u M=1
MP12 N$90 C N$106 VDD P L=0.35u W=1.4u M=1
MN7 N$54 A GROUND VSS N L=0.35u W=1.4u M=1
MN8 N$54 B GROUND VSS N L=0.35u W=1.4u M=1
MN9 N$54 C GROUND VSS N L=0.35u W=1.4u M=1
MN3 N$11 B GROUND VSS N L=0.35u W=1.4u M=1
MN4 N$120 A GROUND VSS N L=0.35u W=1.4u M=1
MN5 N$120 B GROUND VSS N L=0.35u W=1.4u M=1
MP6 N$68 C VDD VDD P L=0.35u W=1.4u M=1
MP7 N$68 B VDD VDD P L=0.35u W=1.4u M=1
MP8 N$68 A VDD VDD P L=0.35u W=1.4u M=1
MN1 N$99 C N$120 VSS N L=0.35u W=1.4u M=1
MN2 N$99 A N$11 VSS N L=0.35u W=1.4u M=1
MN14 COUT N$99 GROUND VSS N L=0.35u W=1.4u M=1

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MP1 N$4 A VDD VDD P L=0.35u W=1.4u M=1

MP2 N$4 B VDD VDD P L=0.35u W=1.4u M=1
MP4 N$99 B N$6 VDD P L=0.35u W=1.4u M=1
MP3 N$6 A N$4 VDD P L=0.35u W=1.4u M=1
MP5 N$99 C N$4 VDD P L=0.35u W=1.4u M=1
MN10 N$90 C N$107 VSS N L=0.35u W=1.4u M=1
MN11 N$107 B N$108 VSS N L=0.35u W=1.4u M=1
MN12 N$108 A GROUND VSS N L=0.35u W=1.4u M=1
MP13 SUM N$90 VDD VDD P L=0.35u W=1.4u M=1
MN13 SUM N$90 GROUND VSS N L=0.35u W=1.4u M=1
MP14 COUT N$99 VDD VDD P L=0.35u W=1.4u M=1
.ends FULLADD
*
* MAIN CELL: Component pathname: /root/fulladd/fulladd_sim
*
V4 VDD GROUND DC 5V
V3 A GROUND PATTERN 5 0 0 1n 1n 50n 10101010
V2 C GROUND PATTERN 5 0 0 1n 1n 50n 11110000
V1 B GROUND PATTERN 5 0 0 1n 1n 50n 11001100
X_FULLADD1 COUT SUM A B C FULLADD
*
.end
Waveforms:

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 VLSI Lab Manual

Experiment No: 4 Date:

Design and implementation of RS-latch

Aim: To design a schematic and draw the Layout for an SR LATCH using Mentor Graphics
Software.
Apparatus: Personal computer and Mentor Graphics Software.
Theory:
A latch is a sequential device that checks all of its inputs continuously and discharges
its outputs accordingly at any independent of a clocking signal. S-R latch uses two NAND
gates, these two gates are cross coupled so that the output of a NAND gate 1 is connected to
one of the input of NAND gate 2 and vice versa.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U for all transistors of the
Circuit Diagram inside the gate.
2. Apply Pattern = 010000010 for V1, Pattern = 10101000 for V2 and Pattern= 11011011 for
V3.
3. Keep Vhi = 5 and Vlo = 0 for V1,V2 and V3.
4. Apply DC Voltage of 5V.
Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktSRFLIPFLOP Q QB E R S
NAND2__NAND2 E R N$14
NAND2__NAND4 N$3 QB Q
NAND2__NAND5 Q N$14 QB
NAND2__NAND1 S E N$3
.ends SRFLIPFLOP
MAIN CELL: Component pathname: /root/srflipflop/srflipflop_sim
V4 VDD GROUND DC 1V
V3 E GROUND PATTERN 5 0 0 1n 1n 50n 11011011
V2 R GROUND PATTERN 5 0 0 1n 1n 50n 10101000
V1 S GROUND PATTERN 5 0 0 1n 1n 50n 01000010
X_SRFLIPFLOP1 Q QB E R S SRFLIPFLOP
.end

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Waveforms:

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 VLSI Lab Manual

Experiment No: 5 Date:

Design and implementation of D-latch
Aim: To design a schematic and draw the Layout for a D- latch using Mentor Graphics
Software.
Apparatus: Personal computer and Mentor Graphics Software.
Theory:
Latch is an electronic device that can be used to store one bit of information. The d-
latch is used to capture or latch the logic level which is present on the data line, when the
clock input is high. If the data on the d line changes state while the clock pulse is high, then
the output Q follows the input D. when the clock input is falls to logic zero the last state of
the D input is trapped
and hold in the latch.
D-latch is a level triggering device. Latches are used as temporary buffers. Many
logic synthesis tools use only D latch/D-flip-flops. The D-latch may be considered as a one
input synchronous SR-latch. This configuration prevents application of the restricted input
combination. It also known as transparent latch, data latch or simply Gated latch. It has a data
input and enable single (sometimes named clock or control signal). The word transparent
comes from the fact that, when the enable input is on, the signal propagates directly through
the circuit, from the input D to the output-Q.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U for all transistors of the
Circuit Diagram inside the gate.
2. Apply Pattern = 0110100101111000 for V1, Pattern = 0011001100110011 for V2 .
3. Keep Vhi = 5 and Vlo = 0 for V1 and V2.
4. Apply DC Voltage of 5V.

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Circuit diagram:

Test bench diagram:

15
 VLSI Lab Manual

Net list:
.subcktDFLIPFLOP Q QB CLKB D
INV3 CLKB N$18
X_SRFLIPFLOP2 Q QB N$18 N$16 N$6 SRFLIPFLOP
INV1 D N$2
X_SRFLIPFLOP1 N$6 N$16 CLKB N$2 D SRFLIPFLOP
.ends DFLIPFLOP
MAIN CELL: Component pathname: /root/dflipflop/dflipflop_sim
V3 VDD GROUND DC 5V
V2 CLKB GROUND PATTERN 5 0 0 1n 1n 50n 0011001100110011
V1 D GROUND PATTERN 5 0 0 1n 1n 50n 0110100101111000
X_DFLIPFLOP1 Q QB CLKB D DFLIPFLOP
.end
Waveforms:

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 VLSI Lab Manual

Experiment No: 6 Date:

Design and implementation Asynchronous counter
Aim: To design a schematic and draw the Layout for an Asynchronous Counter using
Mentor Graphics Software.
Apparatus used: Personal computer, Mentor Graphics Software.
Theory: Asynchronous counters are also known as ripple counters as the clock ripples from
one flip-flop to the next flip-flop. The external clock is connected to the clock input of the
first flip-flop only. If the accumulative ripple delay is longer than the clock pulse, it can result
incorrect count. A counter with n flip-flops can have 2 to the power n states. The number of
states in a counter is known as its mod (modulo) number. A mod-n counter may also called as
a divide-by-n counter. This is because the most significant flip-flop produces one pulse for
every n pulses at the clock input of the least significant flip-flop.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U for all transistors of the
Circuit Diagram inside the gate.
2. Apply Pattern = 0101010101010101 for V1
3. Keep Vhi = 5 and Vlo = 0 for V1.
4. Apply DC Voltage of 5V.
Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktCOUNTERAS Q0 Q1 Q2 CLK
X_DFLIPFLOP3 Q2 N$6 Q1 N$6 DFLIPFLOP
X_DFLIPFLOP2 Q1 N$4 Q0 N$4 DFLIPFLOP
X_DFLIPFLOP1 Q0 N$2 CLK N$2 DFLIPFLOP
.ends COUNTERAS
MAIN CELL: Component pathname: /root/counteras/counteras_sim
V2 VDD GROUND DC 5V
V1 CLK GROUND PATTERN 5 0 0 1n 1n 50n 0101010101010101
X_COUNTERAS1 Q0 Q1 Q2 CLK COUNTERAS
.end
Waveforms:

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 VLSI Lab Manual

Experiment No: 7 Date:

Design and Implementation of Static RAM cell
Aim: To design a schematic and draw the Layout for a static ram cell using Mentor Graphics
Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory: SRAM is a volatile memory, which retains its memory as long as power is being
supplied and its contents vanish if the power is removed. A Static RAM with address lines, m
data lines can store 2n words each of m bits wide. The Data lines are bidirectional in order to
reduce number of pins and package size of memory chip. When reading from the RAM, the
data lines are outputs. Similarly, when writing into RAM, the data lines are inputs.
Procedure:
1. Set Lpu = 1.4U, Wpu = 0.35U and Lpd = 1.4U, Wpd = 0.35U for all transistors of the
Circuit Diagram inside the gate.
2. Apply Pattern = 01101101 for V1, Pattern = 10100110 for V2
3. Keep Vhi = 5 and Vlo = 0 for V1 and V2.
4. Apply DC Voltage of 5V.
Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktSRAM Y BL WL
MN3 N$22 WL N$12 VSS N L=0.35u W=1.4u M=1
MN5 N$12 BL GROUND VSS N L=0.35u W=1.4u M=1
MN4 BL WL Y VSS N L=0.35u W=1.4u M=1
MP3 N$12 BL VDD VDD P L=0.35u W=1.4u M=1
MN2 Y N$22 GROUND VSS N L=0.35u W=1.4u M=1
MN1 N$22 Y GROUND VSS N L=0.35u W=1.4u M=1
MP2 Y N$22 VDD VDD P L=0.35u W=1.4u M=1
MP1 N$22 Y VDD VDD P L=0.35u W=1.4u M=1
.ends SRAM
MAIN CELL: Component pathname: /root/sram/sram_sim
V3 VDD GROUND DC 5V
V2 WL GROUND PATTERN 5 0 0 1n 1n 50n 10100110
V1 BL GROUND PATTERN 5 0 0 1n 1n 50n 01101101
X_SRAM1 Y BL WL SRAM
.end

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Waveforms:

21
 VLSI Lab Manual

Experiment No: 8 Date:

Design and implementation of full Sub tractor
Aim: To design a schematic and draw the Layout for a full Sub tractor using Mentor
Graphics Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory:

A Subtractor is a circuit that is capable of subtracting numbers (in particular, binary).

The circuit performs subtracting depending on a control signal. The full sub tractor is a
combinational circuit which is used to perform subtraction of three input bits: the minuend X,
subtrahend Y, and borrow in Bin. The full sub tractor generates two output bits: the difference
D and borrow out Bout. Bin is set when the previous digit borrowed from X. Thus, Bin is also
subtracted from X as well as the subtrahend Y.

Test bench diagram:

Net list:
.subckt NOT Y A
M2 Y A VDD VDD P L=0.35u W=1.4u M=1

M1 Y A GROUND GROUND N L=0.35u W=1.4u M=1

.ends NOT
* Component pathname : /root/FS1/FS1

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 VLSI Lab Manual

.subckt FS1 Y A B
M12 N$18 B GROUND GROUND N L=0.35u W=1.4u M=1

M11 N$18 B VDD VDD P L=0.35u W=1.4u M=1

M10 N$52 A GROUND GROUND N L=0.35u W=1.4u M=1

M9 N$52 A VDD VDD P L=0.35u W=1.4u M=1

M8 N$36 N$52 GROUND GROUND N L=0.35u W=1.4u M=1

M7 N$8 A GROUND GROUND N L=0.35u W=1.4u M=1

M6 Y N$18 N$36 GROUND N L=0.35u W=1.4u M=1

M5 Y B N$8 GROUND N L=0.35u W=1.4u M=1

M4 Y N$52 N$34 VDD P L=0.35u W=1.4u M=1

M3 N$34 B VDD VDD P L=0.35u W=1.4u M=1

M2 Y A N$25 VDD P L=0.35u W=1.4u M=1

M1 N$25 N$18 VDD VDD P L=0.35u W=1.4u M=1

.ends FS1

Wave forms:

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 VLSI Lab Manual

Experiment No: 9 Date:

Design and Implementation of differential amplifier
Aim: To design a schematic and draw the Layout for a differential amplifier using Mentor
Graphics Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory:

A differential amplifier is a type of electronic amplifier that amplifies the difference

between two input voltages but suppresses any voltage common to the two inputs. It is an
analog circuit with two inputs and one output in which the output is ideally proportional to
the difference between the two voltages

Where A is the gain of the amplifier?

Circuit diagram:

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Test bench diagram:

Net list:
.subckt DIFF1234 VOUT VBIAS VIN1 VIN2
M7 N$6 VBIAS GROUND GROUND N L=1u W=2u M=1
M6 N$6 VIN2 VOUT GROUND N L=1u W=2u M=1
M5 N$3 VIN1 N$6 GROUND N L=1u W=2u M=1
M3 VDD N$3 N$3 VDD P L=1u W=2u M=1
M2 VOUT N$3 VDD VDD P L=1u W=2u M=1
.ends DIFF1234
*
* MAIN CELL: Component pathname: /root/diff1234/diff1234_sim
*
V2 VBIAS GROUND DC 3V
V3 VIN2 GROUND DC 0V AC 1 0 SIN ( 0 1.5v 1k 0 0 )
V4 VDD GROUND DC 5V
V1 VIN1 GROUND DC 0V AC 1 0 SIN ( 0 1v 1k 0 0 )
X_DIFF12341 VOUT VBIAS VIN1 VIN2 DIFF1234
*
.end

25
 VLSI Lab Manual

Waveforms:

26
 VLSI Lab Manual

Experiment No: 10 Date:

Design and Implementation of ring oscillator
Aim: To design a schematic and draw the Layout for a ring oscillator using Mentor Graphics
Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory:

A ring oscillator is a device composed of an odd number of NOT gates in a ring,

whose output oscillates between two voltage levels, representing true and false. The NOT
gates, or inverters, are attached in a chain and the output of the last inverter is fed back into
the first.

If the ’t’ represents the time-delay for a single Inverter and 'n' represents the number
of Inverters in the Inverter chain, then the frequency of oscillation is given by

Circuit diagram:

27
 VLSI Lab Manual

Test bench diagram:

Net list:

.subckt INV2016 Y A

M2 Y A GROUND GROUND N L=0.35u W=1.4u M=1

M1 Y A VDD VDD P L=0.35u W=1.4u M=1

.ends INV2016

* MAIN CELL: Component pathname: /root/inv2016/inv2016_sim

X_INV20165 N$28 NET INV2016

X_INV20164 N$26 N$28 INV2016

V2 VDD GROUND DC 5V

X_INV20163 NET N$26 INV2016

.end

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Waveforms:

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 VLSI Lab Manual

Additional Experiments

Experiment No: 11 Date:

Design and Implementation of Dynamic RAM cell
Aim: To design a schematic and draw the Layout for a Dynamic RAM cell using Mentor
Graphics Software.
Apparatus: Personal computer, Mentor Graphics Software.
Theory: DRAM is a form of semiconductor memory, but it operates in a slightly different
way to other formats.
Procedure:
1. Set L = 1.4U, W = 0.35U for the transistor of the Circuit Diagram..
2. Apply Pattern = 01101101 for V1, Pattern = 10100110 for V2
3. Keep Vhi = 5 and Vlo = 0 for V1 and V2.
4. Apply DC Voltage of 5V.

Circuit diagram:

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 VLSI Lab Manual

Test bench diagram:

Net list:
.subcktDRAM Y BL WL
C1 Y Ground lp
MN1Y WL BL VSS N L=0.35u W=1.4u M=1
.ends DsRAM
MAIN CELL: Component pathname: /root/dram/dram_sim
V3 VDD GROUND DC 5V
V2 WL GROUND PATTERN 5 0 0 1n 1n 50n 10100110
V1 BL GROUND PATTERN 5 0 0 1n 1n 50n 01101101
X_DRAM1 Y BL WL DRAM
.end

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Waveforms:

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Experiment No: 12 Date:

Design and Implementation of 2 × 1 Multiplexer
Aim: To design a schematic and draw the Layout for a 2 × 1 Multiplexer using Mentor
Graphics Software.
Apparatus: Personal computer, Mentor Graphics Software

Theory:

Multiplexer is a device that selects one of several analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines,
which are used to select which input line to send to the output. Multiplexers are mainly used
to increase the amount of data that can be sent over the network within a certain amount of
time and bandwidth. A multiplexer is also called a data selector. Multiplexers can also be
used to implement Boolean functions of multiple variables.
Procedure:
1. LPU=2U
WPU=10U
LPD=2U
WPD=5U
2. Set Delay value to 0S, width = 20nS, Period = 50nS for the voltage Source.
3. Set DC Value to 5V. 4. Maintain Width of 4U for Layout
Circuit diagram:

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Test bench diagram:

Net list:
.subckt21MUXTRANS Y A B S

M17 N$150 N$73 VDD VDD P L=0.35u W=1.4u M=1

M9 N$81 N$150 GROUND GROUND N L=0.35u W=1.4u M=1

M8 N$135 S GROUND GROUND N L=0.35u W=1.4u M=1

M7 N$135 S VDD VDD P L=0.35u W=1.4u M=1

M18 N$150 N$73 GROUND GROUND N L=0.35u W=1.4u M=1

M16 N$77 S GROUND GROUND N L=0.35u W=1.4u M=1

M15 N$95 B N$77 GROUND N L=0.35u W=1.4u M=1

M14 N$76 N$135 GROUND GROUND N L=0.35u W=1.4u M=1

M13 N$73 A N$76 GROUND N L=0.35u W=1.4u M=1

M20 N$108 N$95 GROUND GROUND N L=0.35u W=1.4u M=1

M19 N$108 N$95 VDD VDD P L=0.35u W=1.4u M=1

M10 N$81 N$108 GROUND GROUND N L=0.35u W=1.4u M=1

M21 Y N$81 VDD VDD P L=0.35u W=1.4u M=1

M22 Y N$81 GROUND GROUND N L=0.35u W=1.4u M=1

M6 N$81 N$108 N$80 GROUND P L=0.35u W=1.4u M=1

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 VLSI Lab Manual

M5 N$80 N$150 VDD VDD P L=0.35u W=1.4u M=1

M4 N$95 B VDD VDD P L=0.35u W=1.4u M=1

M3 N$95 S VDD VDD P L=0.35u W=1.4u M=1

M2 N$73 N$135 VDD VDD P L=0.35u W=1.4u M=1

M1 N$73 A VDD VDD P L=0.35u W=1.4u M=1

.ends 21MUXTRANS

Waveforms:

Transient response:

35
 VLSI Lab Manual

APPENDIX - A

Mentors Graphics experiment procedure

1. Double click on the Xmanager Enterprize3 icon.

2. Click on the Xstart tab.

3. Enter a new session name as ‘w’ or ‘g’.

4. Enter the host address as “172.168.0.35”.

5. Enter the protocol “SSH”.

6. Enter the user name as “root”.

7. Enter the password as “root123”.

8. Enter the execution command: Xterm (Linux type2).

9. Click on the save tab.

10. Click on the run tab, then a security window appears.

11. Click on accept and save tab, then a Linux window appears.

12. Enter the following commands on the Linux window.

[root@host~]# csh

[root@host~]#source /home/software/cshrc/ams_2009.cshrc

[root@host~]#mkdir name (name of the experiment)

[root@host~]#cd name (name of the experiment)

[root@host~]#da_ic&

Then Pyxis Schematic window appears.

13. Click on the new pop up tab and select new Schematic tab.

14. Enter the name of the file as given in the directory and click ok tab.

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15. Click on the library tab and select the device lab tab.

16. Select the required components and drag the components to the window from the device
lab list. Provide the necessary connections using the nets. Provide the supply voltage and
ground connections from the generic tab.

17. Change the names of the nets and components by right clicking on them and selecting
edit names tab.

18. Click on check and save tab to check the warnings and errors.

19. To generate the symbol to the circuit, click on the add tab then generate symbol, which
opens a generate symbol window.

20. From the generate symbol window, select tick marks to activate symbol, replace existing
and select the edit symbol radio button. Select the choose shape tab and click ok tab.

21. A generated symbol window with the designed symbol is opened. Modify, if required and
click on check and save tab, close the symbol and schematic windows.

22. Again click on the new pop up tab and select new Schematic tab.

23. Enter the name of the file as given in the directory with an extension _sim and click ok
tab, then a new schematic window opens.

24. Right click on the window and select the instance and symbol tab. Then a file browser
window opens, select the inv folder and click ok tab.

25. A schematic window opens again with _sim extent ion which contains modified symbol.

26. To simulate the designed circuit, provide the supplies such as pulse and dc voltages with
sufficient voltages from the source library and connect them with input and output ports and
nets and provide the VDD and GND from generic library and save them.

27. Click on the simulation tab, then a simulation mode window appears.

28. In the simulation mode window, select the new configuration tab, then create new
configuration window appears, give configuration name as simand click ok tab. Again click
ok tab.

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29. To include the file path, select the Lib/Temp/Inc tab, and then include File tab, then Set
include paths window appears.

30. Give path as “$ADK/technology/ic/models/ami05.mod” in browse path tab and click ok

tab.

31. Select the analyses tab, and then a Setup simulation window appears. Enable type of
analyses required and click apply tab and apply required input for analyses by providing input
and output paths and start and end positions. Click apply tab.

32. To observe wave forms, give the input and output lines as probe by selecting probes tab
then setup simulation window appears, again select type of analysis and give task type.

33. Select the run ELDO tab to rum simulation.

34. To get the wave forms, select the view waves tab. Then EZwave 2008.2a production
window appears which gives corresponding waveforms.

35. From the wave form calculate the required measurements and stop simulation.

36. To draw the layout, change the properties of the schematic by clicking the dropdown tab
that left side of the test bench window.

37. After the changing the properties of the schematic, Save the modified circuit and close all
the windows.

38. On the Linux window, enter “IC &” and click enter then “Pyxis Layout” window opens.

39. Click on the new pop up tab in the session then a new Layout window appears.

40. Click on the connectivity, in the logic module give component name as given in the
schematic and in the cell information module give cell name, process and rules as follows and
then click OK tab

CELL NAME : as given in schematic

PROCESS : $ADK/technology/ic/process/ami05

RULES : $ADK/technology/ic/process/ami05.rules

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41. Click on the MGC tab then go to SETUP tab then a SETUP Preferences window opens.
In this window select General then activate the following radio buttons.

“Use Additional, Default View, Left Right Tiling in Window layout”

Then click on OK tab.

42. on the Pyxis layout window there appears two window named as “IC 0: exp name>exp
name (i)” and “/ exp name”.

43. select the “IC 0: exp name>exp name (i)” window .then select Setup tab in the menu bar
and go to Setup Pyxis Assemble tab ,then a Setup Pyxis Assemble window appears. In this
,select the Floor planning radio button, change the Area estimation multiplier as 0.5 ,tick the
Enable fixed pitch grid and change the grid origin from 0.5 (X & Y). Then click OK.

44. Select Setup tab in menu bar and go to SDL tab, then a Setup SDL window appears. On
the window, give Component subtype as “asim_model”. Select the “Prompt user” radio
button, setup Values as “SDL Port Styles” and also select “Setup Tab” ,then a SET
ACTIVE PORT STYLES windows appears in which select metal 1 then click OK Tab.
Then set active port styles window disappears, then again click OK tab.

45. Select the transistors in schematic window and place its layouts in layout window until all
transistors are covered correctly.

46. Select the interconnections in schematic window and place its layouts in layout window
until all interconnections are covered correctly.

47. Select the polysilicon layer to connect two transistors from the layer palette and select the
easy edit from the IC palatte. Draw polysilicon layer from one transistor to other such that all
edges perfectly matched.

48. To draw metal layers between two transistors, go to tool, then iroute and again go to
iroute. Set the required width and place the metal 2 contact.

49. To draw the power supply layer and ground layer, select the metal 1 layer from the layer
palette and select the easy edit from the IC palette and then select shape then draw layers
above and below the transistors.

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50. Place the n-well and p-well contacts for Pmos and Nmos transistors. Thus the layout is
completed.

51. Select the DLA layout from IC Palettes and then select Load rules from IC rules Then a

Select Rules File window appears. Then give Rules file and then click OK tab.

52. Click check tab from the IC Rules. Then the DRC RULES will be checked.

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APPENDIX– B
1. To open the Mentor Server from client machine, one should open the Xmanager tool
from Windows Desktop

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2. This opens the terminal as below and follow the steps shown in the below screen shot

3. Run the commands displayed in the above picture and run “da_ic&” to open Pyxis
Schematic tool for design entry

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4. In order to create new schematic select new _ Schematic and specify the name for the
design in file name tab

Click OK. It opens a new schematic page

5. Select Library _ Device Lib then add Pmos Transistor (4-pin) and Nmos Transistor (4-
pin) on to the schematic area

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6. After adding the transistors create the connections as per the screen shot and also addthe
ports.
7. Click on the worksheet and select the following options from the palette Library_ Device
Library
8. Add a 4-pin PMOS and NMOS from the device lib.
9. Connect the PMOS and NMOS as shown in the figure below to connect from onenode to
another node select “w” to select wire.
10. Click on “back” tab on device lib palette. Select generic lib and add a input portand
output port by selecting the portin and portout tabs.
11. Select the input NET, and right click the mouse button and select “NameNets:”.Change
the net names.
12. Change the properties of transistors by selecting the transistor and pressing‘Q’.or right
click and select edit properties, Change the ASIM_Model from NCH toN for NMOS & PCH
to P for PMOS
13. Change the W & L values of the Transistors to
For PMOS : L = 2u; W=10u
For NMOS : L = 2u; W =5u

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14. After editing the schematic check for errors by selecting check & save option.
15. Go to Add _ Generate Symbol
16. Select Replace existing & activate symbol options
17. Click Ok. Symbol gets generated for you. Change the shape of symbol if required. Save
the symbol.
Test Bench Creation
1. Close all schematics & symbols.
2. Create a new schematic inv_sim by selecting new schematic from session.
3. Add symbol of the schematic made. Add_ Instance_ Choose Symbol.
4. Add a Pulse Source at the input to inverter and a DC Voltage source VDD port.
And do the necessary connections as per the figure given below.
** (from sources library we can pick various sources)
5. Right click on the Pulse Generator Source and select Edit Properties.
6. Change the values of the below mentioned parameters and apply the changes.
Once you change the values that have to be reflected once you click on OK tab.
Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS
Fall = 1nS Width = 25nS Period = 50ns.
7. Also change the magnitude of the Voltage Source from 1V to 5V by following the below
step.
8. Right Click on the Voltage source adjacent to VDD and then Edit properties

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9. Now from the menu bar click on check and save button. This will report if any errors
present.
10. Now click on “back” tab and then select ‘Simulation’ from the palette to run the
simulation and select ok.
11. Select a New configuration (Give a new name for simulation).
12. Now select the Session tab _simulator/viewer from Setup on the palette and ensure
That the following options are set.
Simulator _ Eldo and Viewer _ EZwave and then Ok.
13. Select Lib/Temp/In _ “include files”provide the following path by selecting
thebrowsebutton. $ADK/technology/ic/models/ami05.mod.
14. Select Analyses _and enable “DC” and ”Transient”.
15. Drop down the Analysis setup and select DC setup give the parameters as
Select option Source
Select the voltage source as V1
Start: 0 stop: 5 Step 0.1

16. Select Transient Setup and change the stop time to 1000N.
17. Select the input path A and then hold CTRL key and then output path Y and click
on“ Probes” from the palette. Select DC in Analysis tab, Plot from Task tab
Select add. Similarly select TRAN from Analysis tab and select add and close the
Window

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18. Now click on Run Eldo tab from the palette where it opens 2 windows showing

various steps running in command line. Once it finishes it will invoke the EZWave
waveform viewer. If it is not invoked Click on the View Waves Tab from the palette
to invoke the EZWave Waveform Viewer.
19. Now the EZWave displays the input and output signals.
20. Here if you go and explore the folders and search for spi file in the simulation folder
inside test bench folder. It will be something like the below path
/home/student/inv/inverter_sim/simulation_name/inverter.spi
This .spifile will be used at post layout simulation

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Inverter Layout Generation

1. Before Layout generation, change the ASIM_Model of PMOS from P to PMOS
and NMOS
2. from N to NMOS in inverter schematic.
3. Invoke the IC station tool by typing the following command_ ic& on command
prompt
4. Now choose the “create” option from the palette.
5. Select Component.
6. Component_ to the path of inverter schematic Cell name_ name of inverter
Schematic
7. Process_$ADK/technology/ic/process/ami05
8. Rules_$ADK/technology/ic/process/ami05.rules

9. MGC _ setup _ select left right tiling

10. Set Grid to 0.5. (select the layout window)
Setup _ Pyxis Assemble, and set the parameters as shown below
11. Setup_ SDL
In Component Subtype change ‘model ‘to ‘asim _model’
Choose SDL portstyles.Prompt user
Click setup and select layer 49 (METAL 1 as default layer)

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12. Go to Place_Inst in Palate Area.

13. This will place transistor in Layout view.
14. Similarly do for NMOS transistor and ports

15. Select POLY for Layer Palate and connect the two gates of Transistors.
Easy Edit _ Shape
16. Similarly connect the Drain of PMOS and Drain of NMOS with Metal-1.
17. Extend the Metal-1 layer that connects drains with IRoute option
Tools_IRoute_ IRoute the after extending a layer of metal from M-1 layer that
connects drains & press Space barwhich adds a via on which the port has to be
placed

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18. Draw a square of 6X6 at POLY layer connecting two gates. At 1.5 distance from
sides of square
19. Draw a square with CONTACT TO PLOY as an inner square with 2Lx2L to
POLY.
20. Now connect input pin to Via drawn with Metal 1 layer using IRoute method

21. Connect VDD to Source of PMOS and VSS to Source of NMOS using M1 layer.
Easy Edit_ shape (M1 from Layer palate).
22. Draw M1 layer above PMOS & below NMOS to keep NWELL and PSUB
contacts.
23. Rightclick on the layout area Add _ Layout
Go to $ADK/technology/ic/process/ami05_via
Add Pwell_contact at M1 layer below NMOS and also add on the top of PMOS
transistor, now to change this Pwell to Nwell select the well contact and press ‘Q’
and browse the location to $ADK/technology/ic/process/ami05_via and select
Nwell_contact.

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DRC Checking
DRC check using Calibre:
1. First we have to generate GDSII file:
File_ Export GDSII
2. Give the path where it has to be saved.
Go Options.
Check Replace Existing GDSII File & Add Text on Ports

3. Tools_Calibre_ Run DRC

4. Give details as
Rules: $ADK/technology/ic/process/ami05.rules
Inputs: To the gds file
UnCheck ‘Export from layout Viewer’
Run DRC:
It will report with no results when the design is error free

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Layout versus Schematic:

1. Tools _ Calibre _ Run LVS
Give details as
Rules: $ADK/technology/ic/process/ami05.calibre.rules
Inputs:_ layout Browse for GDS file
Inputs _ netlist Browse for inverter.spi (in your simulation directory of testbench);
Format:SPICE
UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’ Format:
SPICE
Run LVS

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Parasitic Extraction
Tools_ Calibre_ Run PEX
Give details as
Rules: $ADK/technology/ic/process/ami05.calibre.rules
DRC Run Directory: your directory
Inputs:_ layout _GDSII file ;Format : GDSII
Inputs _ netlist _ inverter.spi in your simulation directory; Format: SPICE
UnCheck ‘Export from layout Viewer’ & ‘Export from schematic Viewer’
Outputs: Netlist _Format= DSPF
Used Names for _Schematic
Select only R+C instead of R+C+C
Run LVS
It will generate a PexNetlist file has to be used in post layout simulation

POST LAYOUT SIMULATION

Open your Test Bench: by running da_ic& command in terminal window.
Descend into your schematic and change the Asim_model of PMOS to P and NMOS to
N
Check and Save.
Simulate your Test Bench.
In Simulation Window on top palette,
Tools_Parasitics_Add DSPF

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Go to the directory to find inverter.pex (inverter.pex.netlsit)

Select RC, DSPF and click OK
Now Simulate with Eldo.
You can Add & Remove DSPF in Parasitic which show results with & without Parasitic

This ends the full custom IC design flow for an Inverter using HEP1 Design tools from
Mentor Graphics

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