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Fig. 4. The N-curve and the butterfly curve of the cell, both obtained by sim-
Fig. 2. The static voltage transfer characteristics (VTCs) of the two cross-cou- ulation, are shown. The three points A, B, and C correspond to the two stable
pled inverters during read access of the cell are represented by the solid curves. points A and C and the meta-stable point B of the butterfly curve. The voltage
When the worst-case static noise is applied, the VTCs move horizontally and/or in A is determined by the PDN to PG ratio or cell ratio while the voltage in B is
vertically until point A and B coincide (dotted curves). With more noise applied, related to the PDN to PUP ratio and PG of the cell. The voltage in C is defined
the VTCs have only one common point C and the cell content is flipped. by the PUP to PG ratio or the pullup ratio of the cell.
Fig. 3. For extracting the N-curve during read operation, the bit-lines are
clamped at V and the word-line is activated. Next, a voltage sweep V
from 0 V to V is applied at “0” internal storage node V to obtain the
corresponding current I .
TABLE I
COMPARISON OF THE USUAL SNM AND THE N-CURVE READ STABILITY
METRICS SVNM AND SINM FOR TWO DIFFERENT CELL DESIGNS
Fig. 6. The setup for comparing the usual SNM definition and the N-curve
stability metrics SVNM and SINM.
Fig. 8. The usual write margin of a SRAM cell is defined by the write-trip
point. This is the maximum bit-line voltage, needed to flip the state of the cell.
(1)
(2)
classical DSM transistor model are used [9], but with some sim-
plifications. The channel length modulation effect (CLM) is al-
ways considered in velocity saturation region and only for sat-
uration and linear region when a analytical solution is feasible.
Additionally, no curve smoothing is implemented with the pur-
pose of simplifying the analytical solution. Two solutions for
(3) are found for the SINM. Solution I corresponds to
PDN1 in subthreshold region and solution II corresponds
to PDN1 in velocity saturation. (See the first set of equations at
the bottom of the page.) The correspondent analytical solutions
in the neighborhood of SINM then become
(7)
(8)
Fig. 11. Good agreement is observed between the HSPICE simulations and the
analytical N-curve model, which is solved numerically due to the complexity of
(9)
the classical DSM transistor model. To avoid discontinuities, smoothing of the
transition regions is implemented in DSM transistor model.
(10)
from linear to velocity saturation region. Equation (2) is then
simplified to (4): is obtained by replacing and in (9) with
and , respectively. The SINM is then obtained by
setting the derivative of to to zero:
(3)
(4)
Similar reasoning in the neighborhood of the WTI results in the By solving the simplified analytical equations (5) and (6), the
following simplified equations: voltage solution is as shown in the second set of equations at the
bottom of the page. The analytical solution in the neighborhood
(5) of WTI becomes
(6)
Fig. 14. (a)–(b) An increase in cell ratio improves the read stability of the cell, while the write-ability of the cell degrades. The positive impact of the cell ratio on
the read stability of the cell is more significant for the SINM. (c)–(d) An decrease in pull-up ratio improves the write-ability of the cell but due to the conflicting
read and write needs the read stability degrades.
of different SRAM cells. As mentioned before, between two dif- the write-ability but also on the other performance parameters
ferent cell designs, having the same SVNM but different SINM, (e.g., read current, retention currents, etc.). Finally, the analysis
the one with the highest SINM ensures the most stable cell. The of the N-curve metrics is completed in the next section by using
same reasoning can be done for the write-ability metrics of the them for statistically optimizing the cell in the presence of vari-
N-curve. However, when two different cell designs have both ability, as this is a growing concern in nanometer technologies.
a different SVNM and SINM, one should compare the unit of
power SPNM for the read stability of the cell. For example, if IV. STATISTICAL OPTIMIZATION OF THE SRAM CELL
cell 1 has a low SVNM and a high SINM, while cell 2 has a SRAM cell design uses minimum-sized transistors and the
high SVNM and a low SINM, then it is the cell with the highest performance parameters depend heavily on matched transistors.
SPNM that is more stable. On the other hand, it is also important In this paper, only mismatch is considered because of the
to look at the other performance metrics of the cell, since the cell significant impact of this parameter on the stability [14], the
with the highest SPNM can have a low SVNM metric, resulting standby leakage power [20], and the access time of the cell.
in higher WTV metric and therefore degrading the write-ability Intra-die variations are further worsened by random dopant
of that cell. For the write-ability of the cell it is preferable to have variations in the channel region of the device [1]. The extended
a small WTV and a small absolute WTI, which means the cell Pelgrom model with gate length and width dependency [21] is
design with the smallest WTP. It should be notified that the risk used here for the estimation of the magnitude of the mis-
of obtaining an unstable cell rises by choosing the cell with the match. Extension to any other transistor parameter can easily
smallest WTP. Of course, the SPNM or the WTP metric could be done. The increasing variability and the increasing leakage
be the same for both cell designs. The circuit designer has to currents, together with the conflicting read and write constraints
compare in this case the cell not only on the read stability and on and the limited cell area make the cell design very difficult. In
2584 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
[13], we proposed a statistically-aware optimization approach The same reasoning is applied for the other performance
to tackle this problem by optimizing the design statistically for parameters of the SRAM cell. The pdfs of the N-curve metrics
a given yield target. This approach, originally proposed in [19] are shown in Fig. 15(a)–(d) together with their distributions ob-
for digital circuits, uses the statistical information during the op- tained by Monte Carlo simulations. The Gaussian distributions
timization of the circuit for speed, energy and yield. The prob- assumed for modeling the pdfs match well with the results of the
ability density functions (pdfs) of the performance parameters simulations, which are based on 130-nm technology. Although
are considered and statistical sensitivities are used to guide the it is clear that the Gaussian modeling is not equally accurate
optimization of the leakage power of the cell. The cell is opti- for all the N-curve metrics, it is good enough for designing the
mized for minimal standby leakage power by using the dual- cell. For example, the WTI metric in Fig. 15(d) shows a long
optimization approach. Also in [13], we indicated that the statis- tail at the right side of the distribution. The samples in this tail
tically obtained results reduce the problem of over-design sig- represent SRAM cell designs that require more energy to write
nificantly, which is a major issue in the worst-case optimiza- the cell due to a much lower write-trip point corresponding
tion approach, even in the enhanced worst-case optimization to the low negative WTI values. The intra-die variations
approach [24]. In this paper, we apply this approach both in cause an asymmetrical behavior of the SRAM cell, resulting
130-nm and 65-nm technology, taking the N-curve read stability in different performance parameters with respect to and .
and write-ability metrics as the functionality constraints. Since The actual SINM is then the minimum of two SINMs obtained
the read current ( ) of the weakest SRAM cell mainly limits from the two N-curves of the cell at and , respectively.
the access time of the SRAM memory, as long as the bit-line ca- According to order statistics and assuming that the two SINMs
pacitance is dominating, the read current is used as first approx- are independent identically distributed random variables, in this
imation for the delay constraint during the read operation. The case and , the pdf for the
total leakage of the SRAM cell is the sum of different contribu- minimum of the two SINMs distributions yields [17]
tions [16], namely, the subthreshold leakage current , the
gate leakage current, and the band-to-band-tunneling leakage
current. Since has an exponential relation to the of with the cumulative distribution function (cdf) of either
the transistor [11], only this component is considered here. Next, of the two SINMs. In reality, although and are
two important steps of this statistically-aware optimization ap- normally distributed, they are not independent since they orig-
proach are applied. inate from the same six transistors. Therefore, any deviation in
for one of the transistors affects both SINMs (Fig. 16). The
A. Statistical Definition of the Performance Parameters of the assumption of independence is a first-order approximation.
SRAM Cell
B. Optimization of the Cell Guided by Statistical Sensitivities
Performance parameters are formulated statistically to take As well as considering the pdfs of the performance parame-
the variability into account. In other words, for each target ters, it is also useful to evaluate the improvement in performance
value of the performance parameters (e.g., SINM, WTI, etc.) yield, e.g., SINM yield of the cell, during the optimization. In
the corresponding performance yield target is formulated. The fact, this statistical sensitivity gives information about the direc-
SINM of the SRAM cell depends on the variations of of tion and the magnitude in which a design parameter, in our case
all six transistors. Each is considered as an independent the transistor width, has to move to improve the performance
random variable with a Gaussian distribution defined by mean yield. The sensitivity of the performance yield to the transistor
and variance . Consequently, the mean and variance width is derived as the slope of the yield improvement graph
of the random variable SINM can be estimated by (Fig. 17) [18]. Each point corresponds to the percentage of sam-
applying the Taylor series theorem [15]: ples of the SINM distribution which fulfills the design target of
100 A. For this particular SRAM design, this graph shows the
different sensitivities of the SINM yield to the increasing widths
of the PUP, PDN and PG transistors. In particular, an increase in
PUP width increases the SINM yield to the maximum value, an
increase in PDN width slightly increases the SINM yield and an
increase in PG width will drastically decrease the SINM yield.
This information can then be used to guide the optimization of
(11) the circuit design [7].
C. Results
The intra-die variations used for the 130-nm results
are estimated on data obtained from measurements on test
structures. For 65 nm, the estimation of the variations is based
on [22]. For the 130-nm technology, the analytical modeling
explained above is used for the statistical results. Fig. 18(a)
(12) shows the optimized leakage power of the cell versus a range
of SINM targets for a given SVNM and read current target.
GROSSAR et al.: READ STABILITY AND WRITE-ABILITY ANALYSIS OF SRAM CELLS FOR NANOMETER TECHNOLOGIES 2585
Fig. 15. The estimated Gaussian distributions match well with the simulated distributions. (a) Modeling of the SVNM distribution. (b) Modeling of the SINM
distribution. (c) Modeling of the WTV distribution. (d) Modeling of the WTI distribution.
Fig. 17. The SINM yield improvement or degradation for a particular SRAM
Fig. 16. Dependency between SINM and SINM of the SRAM cell. design is shown versus the transistor width. The increase in PUP width increases
the SINM yield to 100% while the increase in PDN width slightly improves the
SINM yield, and an increase in PG width degrades the SINM yield.
The correspondent nominal SINM and the area penalty are
represented in Fig. 18(b) and (c), respectively. Fig. 19(a) in-
cludes the optimized leakage power results, simulated in 65-nm a SVNM target of 100 mV. The correspondent nominal SINM
technology with supply voltage of 1 V, versus SINM targets for values and area penalty of the optimized results are shown in
2586 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006
Fig. 18. SRAM cell optimization for minimum standby leakage power in 130 nm for both the statistical and the worst-case approach. (a) Standby leakage power
versus a range of SINM targets. (b) Actual SINM value versus the SINM targets. (c) Area penalty versus the SINM targets.
Fig. 19(b) and (c), respectively. From Figs. 18(a) and 19(a), values (with A) of the statistical
it is clear that the SRAM cell optimization allows gaining in approach. Consequently, with the worst-case design approach
leakage power with respect to the worst-case design approach the SRAM cell cannot be optimized for the conflicting read
while meeting the SVNM and read current targets. With the and write constraints and the statistically-aware optimization
worst-case design approach, meeting the SINM constraint approach is thus imperative.
results in over-designing for the actual read stability (~25% for
130 nm [Fig. 18(b)] and ~40% for 65 nm [Fig. 19(b)]) and for V. CONCLUSION
the area (~15% for 130 nm [Fig. 18(c)] and ~26% for 65 nm In this paper, we introduced new N-curve metrics for the
[Fig. 19(c)]). The percentage of over-designing is drastically write-ability of the SRAM cell. For the first time, a comparison
increased with respect to the 130-nm results in Fig. 18(a)–(c). has been made between the N-curve metrics for the read sta-
Moreover, designing for SVNM and SINM targets with the bility and the usual SNM definition and between the N-curve
worst-case approach is only feasible when drastically relaxing write-ability metrics and the write-trip point of the cell. The
the WTV and even more the WTI. To meet the read stability N-curve current information is critical for designing a cell in
target, the worst-case design approach yields WTI values, nanometer technologies. Moreover, it allows overcoming the
obtained from simulation, around 55 A, well outside the read stability limit of . Finally, a statistical optimization
desired range of WTI values located in the far left tail of approach is used to deal with the intra-die variability of the
the WTI distribution, which has a mean of 21.5 A SRAM cell. The obtained results show a gain both in leakage
[Fig. 15(d)]. Therefore, the minimum WTI constraint, e.g., power and area with respect to the worst-case design approach.
30 A, for a particular SRAM design is violated strongly by SRAM cell optimization with the worst-case design approach is
the worst-case design, while this is not the case for worst-case even not feasible when considering intra-die variations due
GROSSAR et al.: READ STABILITY AND WRITE-ABILITY ANALYSIS OF SRAM CELLS FOR NANOMETER TECHNOLOGIES 2587
Fig. 19. SRAM cell optimization for minimum standby leakage power in 65 nm for both the statistical and the worst-case approach. (a) Standby leakage power
versus a range of SINM targets. (b) Actual SINM value versus the SINM targets. (c) Area penalty versus the SINM targets.
to the conflicting read and write constraints of the cell. The in- [4] L. Chang et al., “Stable SRAM cell design for the 32 nm node and
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ACKNOWLEDGMENT hancement,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2004, pp.
The authors would like to thank P. Roussel for the statistical 64–67.
[7] E. Grossar, “A yield-aware modeling methodology for nano-scaled
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[12] J. T. Kao et al., “A 175-mV multiply-accumulate unit using an adap- Michele Stucchi was born in Bari, Italy. After re-
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sistor,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1056–1064, Aug. She continued her research at the Interuniversity Mi-
2002. croelectrics Center (IMEC) as a Research Director of
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[24] Y. Tsukamoto et al., “Worst-case analysis to obtain stable read/write Coordinator of the Strategic Research within the Silicon Process and Device
DC margin of high density 6T-SRAM-array with local Vth variability,” Technology Divrtision. She started the Master of Nanoscience and Nanotech-
in Proc. IEEE/ACM ICCAD, Nov. 2005, pp. 398–405. nology program at KULeuven. She has authored or coauthored more than 200
publications. In 2001, she was appointed an IMEC Fellow. In 2005, she started
her new role as Vice-Rector of the Group Exact Sciences at the K.U.Leuven.