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VLSI Material - Finite State Machines PDF
VLSI Material - Finite State Machines PDF
n n
Q D
Registers
CLK
present state S
• Mealy FSM:
direct combinational path!
outputs
yk = fk(S, x0...xn)
inputs S+ Comb.
x0...xn Comb. D Q
n Registers Logic
Logic
CLK
n
Level to
L Pulse P
Converter
...output P produces a
Whenever input L goes
single pulse, one clock
from low to high...
CLK period wide.
unsynchronized Level to
user input
D Q D Q L Pulse P
FSM
CLK
00 11
11
L=0 01
Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
L=1
P=0 P=1 P=0
L=0
L=0 This is the output that results
“if L=0 at the clock
edge, then stay in state from this state. (Moore or
00.” Mealy?)
L=1 L=1
00 11
L=0 01
Low input, High input,
Waiting for rise
Edge Detected!
Waiting for fall
L=1
P=0 P=1 P=0
L=0
L=0
For N states, use ceil(log2N) bits to encode the state with each
state represented by a unique combination of the bits.
Tradeoffs: most efficient use of state registers, but requires
more complicated combinational logic to detect when in a
particular state.
For N states, use N bits to encode the state where the bit
corresponding to the current state is 1, all the others 0.
Tradeoffs: more state registers, but often much less
combinational logic since state decoding is trivial.
L 00 01 11 10
0 0 0 0 X
L S+ P
1 0 1 1 X Comb. D Q Comb.
n Registers S1
for P:
S1S0 for S0
+: Logic Logic
CLK S0 0 1
L 00 01 11 10 n
0 0 X
0 0 0 0 X S
S1+ = LS0 P = S1S0 1 1 0
1 1 1 1 X S0+ = L
present state S
S1+ = LS0 P = S1S0
S0+ = L
D Q
S1+ S1
Q
S+ Comb.
Comb. D Q
n Registers Logic
Logic
CLK
n
S
• Since outputs are determined by state and inputs, Mealy FSMs may
need fewer states than Moore FSM implementations
1. When L=1 and S=0, this output is
asserted immediately and until the
state transition occurs (or L L 1
changes). 2
P
L=1 | P=1 Clock
L=0 | P=0 0 1 Stat
Input is low Input is high e
Output transitions immediately.
L=0 | P=0
State transitions at the clock
L=1 | P=0 edge.
2. While in state S=1 and as long as L remains
at 1, this output is asserted until next clock.
L=0 | P=0 0 0 0 0
L=0 | P=0 L=1 | P=0 0 1 1 1
1 1 1 0
1 0 0 0
CLK Q
S
L L
P P
Clock Clock
State[ State
0]
STEPS:
1. Design lock FSM (block diagram, state transitions)
2. Write Verilog module(s) for FSM
lock
Clock
fsm_clock fsm
generator
unlock Unlock
reset button LED
Button
reset
Enter
RESET
1
1 0
0
1 0
0
“01011” 1 “0101” 1 “010”
Unlock = 1 Unlock = 0 Unlock = 0
0
6 states 3 bits
6.111 Fall 2017 Lecture 6 16
Step 2: Write Verilog
module lock(input clk,reset_in,b0_in,b1_in,
output out);
// generate output
assign out = ???;
// debugging?
endmodule
parameter S_01011 = 5; 0
1 0
0
reg [2:0] state, next_state; “01011 ” 1 “0101 ” 1 “010”
Unlock = 1 Unlock = 0 Unlock = 0
always @(*) begin
// implement state transition diagram 0
– DC - dispense can
– DD - dispense dime
– DN - dispense nickel
Dispense Dispense
got45c Dime Nickel
N=1
D=1 got15c
N=1 Q=1
D=1 got20c
N=1 Q=1
D=1 got25c *
N=1 Q=1
See a better way?
D=1 got30c
So do we. DC=1 *
Don’t go away... Q=1
got35c chg35
DC=1 DN=1
*
got40c chg40
* *
DD=1
DC=1
*
got45c
DC=1
* chg45
DD=1
chg45b
DN=1 *
got50c chg50 chg50b
DC=1
* DD=1 DD=1
combinational logic
parameter RETURN_20c = 11;
parameter RETURN_15c = 12;
(comb. always block with case) parameter
parameter
RETURN_10c = 13;
RETURN_5c = 14;
Output 10¢ 5¢
If the soda dispenser is glitch-sensitive, your customers can get a 20-cent soda!
next
Next- state
inputs State D State Q
n
Comb. Registers
Logic CLK
n
present state S
always block
always @ (posedge clk or negedge reset) begin
if (!reset) state <= IDLE;
else if (clk) state <= next;
Calculate outputs based
on next state
DC <= (next == GOT_30c || next == GOT_35c ||
next == GOT_40c || next == GOT_45c ||
next == GOT_50c);
Delays outputs by one DN <= (next == RETURN_5c);
D Q CLK2
CLK1 CLK1
6.111 Fall 2017 Lecture 6 32