Effect of Vds Variation on the Trapped Charge

Distribution of a SONOS Memory

Dary Mochamad Rifqie1, Muhammad Amin Sulthoni1,2, Akhmadi Surawijaya1,2, Irman Idris1,2
1
School of Electrical Engineering and Informatics, Bandung Institute of Technology
2
Centre of Excellence on Microlectronics, Bandung Institute of Technology
Bandung, Indonesia

Abstract - In this paper, simulation of SONOS memory cell
has been performed. We investigate the effect of various
Vds values in order to observe the charge distribution in
the floating gate. By varying drain voltage from 0 to 5 V
and maintaining gate voltage constant at 8 volt, we
observed a decreasing programming threshold voltage. I-V
curve shows threshold voltage shifts according to the
variation of voltage drain. Furthermore, we also observed a
spatial distribution of trapped electrons in floating gate
which is changing as the voltage drain is varied.
Keyword – SONOS memory, trapped charge, Threshold
voltage, floating gate
I. INTRODUCTION
A concept of Silicon-oxide-nitride-oxide-silicon (SONOS) is
interesting for use in silicon-based nonvolatile memory. as
declared in International Technology Roadmap for
Semiconductor (ITRS), floating gate silicon-based memory
will reach thickness limit of tunnel oxide around 8 nm[1]. The
key construct of this technology is based on trapped charge
storage inside a nitride layer[2].
Compared to floating gate memory, resilience toward
physical defects in SONOS memory storage is one of the
important aspect. Charge trapping storage device like SONOS
memory seems to be technologically promising to replace
floating gate flash technology. Double-bit operation has been
achieved in SONOS technology electrons placement in the
storage layer[3]. Localizing electron in SONOS can be
achieved by the channel hot electron injection method. The
electrons are injected above the drain junction of the cell
transistor in case when high voltage values are applied at the
gate and drain. Variation of the voltage applied to the drain and
gate resulted the placement of the trapped electrons in different
part of the storage layer due to the kinetic energy variation. The
charge injection placement is a key performance parameter for
program, read and erase. The threshold voltage value and its
stability depends on the position of the trapped charge in the
storage layer, injected charge and the quality (energy depth) of
the traps. Futhermore, a 4-bit operation has been performed in
silicon-on-insulator (SOI)-based SONOS memory which store
electrons on the top and bottom side of oxide-nitride-oxide
layers [4].
In this paper, we will investigate the distribution of electrons
trapped in the storage layer with respect to the drain voltage
variations by using Synopsis simulator.
II. DEVICE STRUCTURE
By using Structure Device Editor (SDE) simulation, we
simulate a SONOS memory device with the design rule as
follow:
Tabel 1.design rule of SONOS cell
Physical part Dimension (nm)
Tunnel Oxide thickness 2
Blocking oxide thickness 4
Nitride layer thickness 8
Channel length 130

1

The SONOS memory device structure shown in tecplot
view can be seen in Figure.1 below:
Figure 1. Details of SONOS memory device
In this simulation, we use Sdevice to varied voltage value
for program condition in drain. The voltage variation are
listed below:
Table 2.Voltage variations for program state
Sample Gate voltage Drain voltage
1 8 volt 0 volt
2 8 volt 1 volt
3 8 volt 3 volt
4 8 volt 5 volt
III. SIMULATION
For device simulations, the general idea is to give a voltage
bias to source,drain and gate electrodes. In order to simulate
the programming and erasing function in synopsis CAD tools,
simulation of transient mode is applied. Using different
voltages at the drain and gate electrodes for programming
(shown at table 2), we then observe the distribution of trpped
charges in the storage layer. This states is saved as
programmed state and it is use for the other sdevice command
in order to calculate its I-V characteristic. This characteristic
will be calculated by applying a constant drain voltage (5 volt)
and varying gate voltage (from -1.25 to 3.25 volt).
Futhermore, we examined the resulting I-V characteristic
curve to determine the threshold voltage shifting. Moreover,
we also defined channel hot electron injection for the
programming mechanism. In order to simulate the channel hot
electron injection, we use spherical harmonics expansion to
2
obtain the probability of hot electron which can passed over
oxide barrier.
IV. RESULTS AND DISCUSSION
Figure 2 to 5 shows the distribution of trapped electrons
inside nitride layer after programming. The figure shows that
the distribution of trapped electrons is changing as the voltage
is varied. Higher drain voltage will result in location of the
trapped electrons in the storage layer to shift to right side of
the nitride layer. This can be explained that as the voltage in
drain increase, the electron gains more energy from source
side.
Figure 2. Distribution of trap occupation in 0 volt drain voltage, 8
volt gate voltage
Figure 3. Distribution of trap occupation in 1 volt drain voltage, 8
volt gate voltage
Figure 4. Distribution of trap occupation in 3 volt drain voltage, 8
volt gate voltage
Figure 5. Distribution of trap occupation in 5 volt drain voltage, 8
volt gate voltage
From Figure 6 to 9, we found that I-V curve threshold
voltage shifts from 1.45, 1.15, 0,8 and 0.6 Volt for voltage
drain of 0, 1, 3 and 5 Volt respectively. Inspection of I-V
curve of the programmed states indicate that the threshold
voltage have larger value for a lower voltage drain. As voltage
drain is rising, electrons trapped in the nitride layer will not
spread and became more concentrated in a specific location
within the nitride layer. Therefore, the value of threshold
voltage is shifting to the left side as the programming drain
voltage increase.
The shifting of the values of the threshold voltage can be
applied to determine the memory performance. An I-V curve
for the erased state is provided for comparison. The change in
shifting of threshold values is wide enough so we can easily
select the read voltage. A low valued threshold voltage ensure
that the Vread will be low enough, so the power consumption
also will be low[5].
Figure 6. Threshold voltage shift for erase (red) and programmed
state (black) at 0 volt drain voltage
Figure 7. Threshold voltage shift for erase (red) and programmed
state (black) at 1 volt drain voltage
Figure 8. Threshold voltage shift for erase (red) and programmed
state (black) at 3 volt drain voltage
3
Figure 9. Threshold voltage shift for erase (red) and programmed
state (black) at 5 volt drain voltage
V. CONCLUSION
A SONOS nonvolatile memory device has been simulated. The
results show that spatial distribution of electron in nitride layer
shift as the voltage drain is varied. Futhermore, by varying
drain voltage from 0 to 5 V and maintaining gate voltage
constant at 8 volt, we observed a decreasing programming
threshold voltage. I-V characteristic curve shows threshold
voltage shift to the left side as the drain voltage is increased.
REFERENCE
[1]. ([Online] Available: http://public.itrs.net/ 2001) ITRS Roadmap.
[2]. Fukuda, M., Nakanishi, T., & Nara, Y. (2003). New nonvolatile
memory with charge-trapping sidewall. IEEE Electron Device
Letters, 24(7), 490–492. doi:10.1109/led.2003.815002.
[3]. Detlev Richter, Flash Memory : economic principle of
performance, cost and reliability optimization., springer, 2013
[4]. Datta, A., Kumar, P. B., & Mahapatra, S. (2007). Dual-Bit/Cell
SONOS Flash EEPROMs: Impact of Channel Engineering on
Programming Speed and Bit Coupling Effect. IEEE Electron
Device Letters, 28(5), 446–448. doi:10.1109/led.2007.895406
[5]. Sentaurus Device (sdevice) user manual..
[6] Kartiwa, G. M., Hendrayana, Y. H., Prihatiningrum, N.,
Sulthoni, M. A., Surawijaya, A., & Idris, I. (2017). Effect of
Lsg/Lfg ratio variation to the IV curve of split-gate 1st
generation superflash. 2017 International Symposium on
Electronics and Smart Devices (ISESD).
doi:10.1109/isesd.2017.8253345
we do also a simulation varying gate voltage(5 volt/6 volt/ 7
volt) and then tune the thickness of the tunneling layer so we
can find almost the same amount of electron traped in the
floating gate. The voltage and thickness variation are listed
below:
Example Gate voltage (v) Tunnelling layer
thickness (nm)
1 5 1.8
2 6 3.66
3 7 4.3

Tabel 3. voltage variation for program state