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Nonvolatile memory operations of metal-ferroelectric-insulator-

semiconductor (MFIS) FETs using PLZT/STO/Si(100) structures

Article in IEEE Electron Device Letters · May 1997

DOI: 10.1109/55.563315 · Source: IEEE Xplore

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160
Nonvolatile Memory Operations of Metal-
Ferroelectric-Insulator-Semiconductor (MFIS)
FET’s Using PLZT/STO/Si(100) Structures
Eisuke Tokumitsu, Member, IEEE, Ryo-ichi Nakamura, and Hiroshi Ishiwara, Senior Member, IEEE
Abstract— We report fabrication and characterization of
p-channel metal-ferroelectric-insulator-semiconductor (MFIS)-
FET’s using the PLZT/STO/Si(100) structures and demonstrate
nonvolatile memory operations of the MFISFET’s. It is found
that ID –VG characteristics of PLZT/STO/Si MFIS-FET’s show
a hysteresis loop due to the ferroelectric nature of the PLZT
film. It is also demonstrated that the ID can be controlled by
the “write” pulse, which was applied before the measurements,
even at the same “read” gate voltage.
I. INTRODUCTION
R ECENTLY, there has been a growing interest on ferro-
electric materials for nonvolatile memory applications.
Non-volatile memories using ferroelectric capacitors have
been widely studied, which utilize basically destructive
read operations. On the other hand, nonvolatile memories
using metal-ferroelectric-semiconductor field-effect-transistors
(MFSFET’s) [1] make nondestructive read operation possible.
In addition, MFSFET’s can be used as adaptive-learning
analog memories in neural networks [2]. However, preparation
of ferroelectric/Si structures with good interface is difficult
because of the chemical reaction of Si and ferroelectric
materials. Particularly, it is well known that ferroelectric
Pb(Zr,Ti)O (PZT) films easily react with Si and inter-
diffusion of Pb and Si at the PZT/Si interface occurs even
at temperatures as low as 500 C [3], [4]. Nakao et al.
[5] reported metal-ferroelectric-metal-insulator-semiconductor
(MFMIS) FET structure using PZT and SiO as a ferroelectric
film and a gate insulator. In this structure, the excellent
interface properties of SiO /Si is available. However, it
becomes difficult to apply sufficient voltage to the PZT film
because the dielectric constant of PZT films is much higher
than that of SiO Consequently, it needs high
operation voltage to apply large enough voltage to reverse the
polarization of the PZT film.
In this work, we fabricated p-channel Si FET’s with a fer-
roelectric (Pb,La)(Zr,Ti)O (PLZT) gate insulator. A SrTiO
(STO) buffer layer [4], [6] is used to grow the PLZT films
on Si substrates because the dielectric constant of STO is as
large as 300, so that one can apply the large enough voltage
Manuscript received August 16, 1996; revised December 5, 1996. This work
was supported in part by a Grant-in-Aid for Scientific Research on Priority
Areas (072 481 05) from the Ministry of Education, Science, and Culture, and
by the Asahi Glass Foundation.
The authors are with the Precision and Intelligence Lab., Tokyo Institute of
Technology, Yokohama 226, Japan.
Publisher Item Identifier S 0741-3106(97)02662-1.
0741–3106/97$10.00  1997 IEEE
IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 4, APRIL 1997
to reverse the polarization of ferroelectric PLZT film. Since
we use an STO buffer layer, we refer to the PLZT/STO/Si
structure FET’s as metal-ferroelectric-insulator-semiconductor
(MFIS) FET’s. In this paper, we demonstrate nonvolatile
memory operations of p-channel MFISFET’s, by using a
combination of a high- STO buffer layer and a ferroelectric
PLZT film with a relatively low dielectric constant.
II. SAMPLE PREPARATION
The device structure is illustrated in Fig. 1 First, boron-
diffused source and drain regions were formed using n-Si(100)
substrates. Then, the STO buffer layer and the PLZT (La:
6%, Zr/Ti ) film were deposited by the sol-gel or
metal-organic decomposition (MOD) [7] method. STO films
were spin-coated on Si substrates, dried at 120–150 C for 10
min, pre-annealed at 470 C for 30 min and finally annealed
at 800 C for 30 min for crystallization. Then PLZT films
were prepared on STO/Si. The growth conditions of the PLZT
films were similar to that for STO films except that the final
annealing was performed at 700 C for 1–3 min using the rapid
thermal annealing (RTA) technique. The typical thicknesses of
STO and PLZT films were 70 nm and 400 nm, respectively.
Experimentally measured relative dielectric constant of the
STO buffer layers was about 70, which is lower than that
of the bulk, suggesting the presence of a low- layer at
the interface. If we assume SiO as the low- layer, it is
estimated from thickness dependence of a total capacitance
that about 3 nm of SiO layer was formed at the STO/Si
interface during the STO growth, although it is difficult to
determine the exact composition and thickness of the low-
layer. Hence, to apply the voltage large enough to reverse
the polarization of the ferroelectric film, a ferroelectric film
with a relatively low dielectric constant is required. In this
work, to reduce the dielectric constant, we use the PLZT
film with a low Zr/Ti ratio (Zr/Ti ), whose dielectric
constant is about 240. Remanent polarization P and coercive
field estimated from the P-E characteristics of PLZT films
grown on Pt/SiO /Si substrates are 2.7 C/cm and 50 kV/cm,
respectively. Finally, after contact holes for source and drain
were opened by wet chemical etching, Al electrodes were
formed by vacuum evaporation. For comparison, MISFET’s
with only STO gate insulator was also fabricated. The channel
length and width were 40 m and 160 m, respectively. The
TOKUMITSU et al.: NONVOLATILE MEMORY OPERATIONS OF MFIS FET’S
Fig. 1. Schematic cross section of the p-channel PLZT/STO/Si MFIS-FET’s
fabricated in this work.
Fig. 2. ID –VD characteristics of p-channel STO/Si MISFET.
details of the film quality of the PLZT films along with device
processing will be reported elsewhere [8].
III. RESULTS AND DISCUSSION
First, we confirmed capacitance–voltage (C–V) characteris-
tics of STO(70 nm)/Si structures have no hysteresis, indicating
that charge injection or ion drift effects is negligibly small. The
interface state density estimated from the C–V characteristics
is eV cm Improvements of the interface
property along with the reduction of the residual impurities
during the sol-gel process will be necessary in future. Next,
MISFET’s were fabricated using only STO as a gate insulator.
Fig. 2 shows (drain current)– (drain voltage) character-
istics of STO/Si MISFET without a ferroelectric PLZT film.
It is worth noting that normal MISFET characteristics are
obtained, showing a stable operation of STO/Si MISFET’s
with no hysteresis.
Fig. 3 shows – (gate voltage) characteristics of
PLZT/STO/Si MFIS-FET’s. A hysteresis loop was obtained
with a counter-clockwise trace as indicated by arrows. Since
no hysteresis was observed in – characteristics of STO/Si
MISFET’s except for the small current range, this hysteresis
is believed to be due to the ferroelectric nature of PLZT
films. A memory window, i.e. threshold voltage shift of the
fabricated device was 0.9 V for a sweep from 7 to 2
V An estimated field-effect hole mobility is 110 cm Vs The
relatively low field-effect hole mobility is presumably due to
inferior interface properties of STO/Si structures fabricated in
this work to that of SiO /Si in conventional MOSFET’s.
Next, to examine the memory effect of the fabricated
PLZT/STO/Si MFISFET’s, – characteristics were mea-
sured by varying “write” and “read” voltages. First, 2 or 7
V “write” voltage was applied to the gate for about 1 s. Then
161
Fig. 3. ID –VG characteristics of p-channel PLZT/STO/Si MFIS-FET. A
hysteresis loop is due to the ferroelectric nature of the PLZT film.
Fig. 4. ID –VD characteristics of PLZT/STO/Si MFIS-FET. Solid and
+ 0
dashed lines show the drain currents after 2 V and 7 V “write” voltages
0
were applied to the gate, respectively. The “read” gate voltages are 2 or
0 3 V for both cases.
the gate voltage is adjusted at 2 or 3 V (“read” voltage)
for the drain current measurements. Fig. 4 shows measured
– characteristics of PLZT/STO/Si MFISFET’s. Solid and
dashed lines show the drain currents after the “write” voltage
of 2 and 7 V were applied to the gate, respectively. The
“read” gate voltages are 2 or 3 V for both cases. The
saturated drain current is 74 A when the “write” and
“read” voltages are 7 and 3 V respectively, whereas the
is reduced to as small as 3 A even at the same gate
voltage of 3 V when the “write” voltage is 2 V This is
because the polarization of the ferroelectric PLZT film was
reversed by the previously applied “write” voltage. It is also
demonstrated that when the “read” gate voltage is 2 V a
transition from “on” to “off” states can be obtained due to
the polarization reversal of the ferroelectric PLZT film. The
drain current of “on” state (37 A) is more than three orders of
magnitude larger than the “off” state drain current (10 nA) at a
V It is worth noting that the can be significantly
changed due to the “write” voltage, which was applied before
the measurements, even at the same “read” gate voltage. This
clearly demonstrates the memory operation of the p-channel
PLZT/STO/Si MFIS-FET fabricated in this work.
IV. SUMMARY
P-channel MFISFET’s using PLZT/STO/Si structures were
fabricated and electrical properties of the MFISFET’s have
162
been demonstrated. – characteristics of STO/Si MIS-
FET without a ferroelectric PLZT film showed no hysteresis,
whereas a hysteresis loop due to the ferroelectric nature
of PLZT films was clearly observed in – characteris-
tics of PLZT/STO/Si MFIS-FET’s. It was also demonstrated
that the drain current of the PLZT/STO/Si FET’s was con-
trolled by a previously applied “write” pulse. This demon-
strates the nonvolatile memory operations of MFISFET’s using
PLZT/STO/Si structures.
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