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High-Temperature Performance of Silicon Junctionless MOSFETs

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DOI: 10.1109/TED.2009.2039093 · Source: IEEE Xplore

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620 www.DownloadPaper.ir IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 3, MARCH 2010

High-Temperature Performance of Silicon

Junctionless MOSFETs
Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Member, IEEE, Ran Yan, Nima Dehdashti Akhavan,
Pedram Razavi, and Jean-Pierre Colinge, Fellow, IEEE

Abstract—This paper investigates the temperature dependence nel, and drain [2]. The absence of doping concentration gradient
of the main electrical parameters of junctionless (JL) sili- eliminates diffusion of impurities and the problem of sharp
con nanowire transistors. Direct comparison is made to silicon doping profile formation altogether. Any increase of temper-
nanowire (trigate) MOSFETs. Variation of parameters such as
threshold voltage and ON–OFF current characteristics is analyzed. ature induces variations of the electrical parameters of MOS
The JL silicon nanowire FET has a lager variation of threshold devices (e.g., threshold voltage shift, increase of leakage cur-
voltage with temperature than the standard inversion- and accu- rent, and reduction of mobility [3].) In this paper, we investigate
mulation-mode FETs. Unlike in classical devices, the drain current the temperature dependence of the electrical characteristics of
of JL FETs increases when temperature is increased. JL transistors. It is already known that MuGFET devices
Index Terms—High temperature, junctionless (JL) FET, present excellent properties for high-temperature applications
multiple-gate MOSFET, silicon nanowire FET. [4]. In this paper, we investigate the variation of electrical char-
acteristics, such as the ON–OFF current and leakage current in
I. I NTRODUCTION gate-induced drain leakage (GIDL) of conventional inversion-
mode (IM) nMOS, accumulation-mode (AM) pMOS, and
HE SCALING OF gate length in MOSFETs poses in-
T creasingly difficult challenges as leakage current and
short-channel effects increase due to the decreasing control
JL pMOS and nMOS MuGFETs, with temperature.

efficiency of the gate on the channel. To meet those challenges, II. D EVICE D ESIGN AND M EASUREMENTS
new device architectures such as fully depleted silicon-on- The devices were fabricated on standard Unibond SOI wafers
insulator (FDSOI), double-gate MOSFETs, and multigate SOI with a 340-nm top silicon layer and a 400-nm buried oxide. The
MOSFETs (MuGFETs) have been proposed. The International starting SOI film is p-type with a resistivity of 10–20 Ω · cm.
Technology Roadmap for Semiconductors predicts a 10-nm The SOI layer was thinned down to 10–15 nm by sacrificial
gate length with FDSOI technology in 2015 and a 7-nm gate oxidation and wet chemical removing process and was pat-
length with double gate devices in 2018 [1]. In a MuGFET, the terned to form silicon nanowires using e-beam lithography.
gate electrode is wrapped around a silicon nanowire, forming Gate oxidation was performed, and ion implantation was used
a multigate structure with excellent control of the channel po- to dope the devices uniformly n+ and p+ with a concentration
tential, which allows one to fully deplete the channel region. In of 1−2 × 1019 cm−3 to realize n- and p-channel devices, re-
very-short-channel devices, the formation of ultrasharp source spectively. “Classical” IM n-channel trigate nanowire transis-
and drain junctions is quite a challenge and imposes drastic tors were fabricated as well with a channel acceptor doping
conditions on doping techniques and thermal budget. Recently, concentration of NA = 2 × 1018 cm−3 . AM pMOS trigate
junctionless (JL) MuGFETs have been proposed to avoid this nanowire devices were fabricated as well with unimplanted
problem. The JL transistor is a resistor with uniform doping. channels (NA ∼ = 5 × 1015 cm−3 .) A 50-nm polysilicon layer
The doping concentration is constant through the source, chan- was deposited by low-pressure chemical vapor deposition on
the gate oxide and doped either by p2+ (JL nMOS devices)
or n2+ (IM nMOS, JL pMOS, and AM pMOS). The devices
Manuscript received August 7, 2009; revised November 25, 2009. First
published January 26, 2010; current version published February 24, 2010. This studied here have a gate length of 1 µm. The source and drain
work was supported in part by the Science Foundation Ireland under Grant regions were formed by arsenic and BF2 ion implantation for
05/IN/I888: Advanced Scalable Silicon-on-Insulator Devices for Beyond-End- n-channel IM and p-channel AM devices, respectively, but no
of-Roadmap Semiconductors, by the Programme for Research in Third-Level
Institutions, and by the European Community Seventh Framework Program source or drain implant was performed on the JL MuGFETs.
through the Networks of Excellence NANOSIL and EUROSOI+ under Con- Oxide was deposited and etched to form contact holes, and
tract 216171 and Contract216373. The review of this paper was arranged by TiW + Al metallization completed the process. Nanowires
Editor M. Reed.
C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti Akhavan, P. Razavi, were fabricated with a silicon thickness ranging from 5 to
and J.-P. Colinge are with the Tyndall National Institute, University College 10 nm. The gate oxide thickness is 10 nm. During processing
Cork, Cork, Ireland. (including gate oxidation), the width of the nanowire was
A. Borne is with the Institut de Microélectronique Electromagnétisme et
Photonique (IMEP)-Phelma, Micro and Nanotechnology Innovation Centre reduced by 10 nm. The as-written (e-beam) width of the
(MINATEC), Grenoble National Polytechnic Institute (INPG), 38016 Grenoble nanowires width is 30 nm, which means that the final width
cedex 1, France. is 20 nm. Fig. 1 shows a 3-D schematic view of the different
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. types of devices presented in this paper and a cross-sectional
Digital Object Identifier 10.1109/TED.2009.2039093 view of the source and drain structures.

0018-9383/$26.00 © 2010 IEEE

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Fig. 1. Schematic view of the silicon nanowire FET and cross-sectional view of JL nMOS, JL pMOS, IM nMOS, and AM pMOS silicon nanowire FETs.

III. R ESULTS AND D ISCUSSION

current increases in a monotonous manner, and there is no
Fig. 2 shows measured drain current as a function of gate ZTC point.
voltage at different temperatures for (a) JL pMOS and JL Fig. 4 shows the measured ON current as a function of
nMOS and (b) IM nMOS and AM pMOS transistors at VDS = temperature in devices with W = 20 nm and L = 1 µm at
±1.0 V. The device width is W = 20 nm. The threshold voltage VDS = ±1.0 V. The ON current is taken at a fixed gate volt-
decreases and the subthreshold slope increases in all devices age overdrive (GV 0 = |VGS − VTH(roomtemperature) |). Here,
as temperature is increased. Fig. 3 presents the measured we used GV 0 = 0.8 V. The ON current of IM nMOS and
threshold voltage of the different devices as a function of AM pMOS devices decreases with temperature as gate bias
temperature at VDS = ±1.0 V. Planar FDSOI MOSFETs have a is larger than ZTC bias. In JL MuGFETs, on the other hand,
smaller threshold voltage variation with temperature than bulk the ON current increases continuously with temperature. This is
MOSFETs [3], [5]. The use of the MuGFET structure can fur- because the threshold voltage of the JL devices decreases more
ther reduce the temperature dependence of the threshold voltage with temperature than in IM and AM devices, while mobility
when narrow silicon fingers are used due to the reduction in the reduction is lower. The extracted maximum effective mobility
surface potential variation with the temperature [4]. As a result, of JL, AM, and IM MuGFETs is shown in Fig. 5. The effective
the value of dVTH /dT in narrow IM MMOS and AM pMOS mobility is extracted in linear regime (VDS = ±50 mV) using
MuGFETs is smaller than in planar FDSOI MOSFETs [3], [5]. the Y = IDS /(gm )1/2 function method [8]. The mobility in
The threshold voltage variations of JL MuGFETs are more than Fig. 5 was extracted at the peak of transconductance, for a
twice as large as in AM and IM MuGFETs, reaching values GV 0 of nearly zero volts. The mobility in the IM devices
similar to bulk MOSFETs [3] (Fig. 3). is a surface mobility involving a mixture of (100) and (110)
In a conventional MOSFET, the decrease of threshold voltage interface at the top and sidewall of the device, respectively.
with temperature tends to increase drain current, while the Due to interface scattering, interface mobility drops quickly as
reduction of mobility due to increasing phonon scattering with GV 0 is increased. In the JL devices, on the other hand, the
temperature tends to decrease it [6], [7]. There exists a gate channel is within the bulk of the device, and mobility drops
bias point at which these effects compensate one another, much less as GV 0 is increased. As a result, the current in the
called the “zero temperature coefficient” (ZTC) point. The IM device at GV 0 = 0.8 V is only 50% larger than in the JL
ZTC point is located at VG = 1 V for IM n-channel devices device at room temperature (Fig. 4), while IM devices have a
and VG = −0.5 V for AM p-channel devices in Fig. 2(b). In peak mobility that is three times higher than JL devices. One
JL transistors, the reduction of mobility with temperature is can see the mobility of the IM and AM MuGFETs decreases
much lower than in the other types of transistors. As a result, with temperature. In these devices, doping concentration is

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Fig. 2. Measured IDS –VGS characteristics with various temperatures of (a) JL nMOS and JL pMOS and (b) IM nMOS and AM pMOS silicon nanowire FET
(VDS = ±1.0 V, L = 1 µm, and W = 20 nm).

Fig. 3. Measured threshold voltage of JL nMOS, JL pMOS, IM nMOS, and Fig. 4. Measured drain ON current of JL nMOS, JL pMOS, IM nMOS, and
AM pMOS as a function of temperature (VDS = ±1.0 V, L = 1 µm, and AM pMOS as a function of temperature (VDS = ±1.0 V, L = 1 µm, and
W = 20 nm). W = 20 nm).

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Fig. 5. Extracted the peak of the effective mobility of JL nMOS, JL pMOS,

IM nMOS, and AM pMOS as a function of temperature (VDS = ±50 mV,
L = 1 µm, and W = 20 nm).

small, and mobility is limited mainly by phonon scattering,

which explains the decrease of mobility with temperature. The
JL devices, on the other hand, have heavily doped channels in
which the mobility is mainly limited by impurity scattering.
Mobility that is limited by pure phonon scattering varies as
T −3/2 , while mobility that is limited by impurity scattering
varies as T 3/2 [12]. Thus, in JL devices, a compensation effect
occurs between the two types of scattering, and the mobility
is almost independent of temperature (Fig. 5). These effects
explain the continuous increase in ON current with temperature
in JL MuGFETs. Fig. 6 shows the output characteristics of
(a) JL pMOS and JL nMOS and (b) IM nMOS and AM pMOS
devices at room temperature and at 200 ◦ C. These curves clearly Fig. 6. Measured IDS –VDS characteristics at room and high temperatures for
show that the current drive of JL MuGFETs increases with various gate voltage values of (a) JL nMOS and JL pMOS and (b) IM nMOS
and AM pMOS silicon nanowire FETs (L = 1 µm and W = 20 nm).
temperature, while it decreases in IM nMOS and AM pMOS
MuGFETs.
The off–leakage current increases with temperature because GIDL of devices as a function of the temperature at a high drain
of the increase of intrinsic carrier concentration ni , which voltage. GIDL is defined as the current at VGS = VTH − |1.2 V|
increases both diffusion and generation currents. We mea- and VDS = ±2.5 V. The GIDL of JL FETs is lower than those
sured the drain current of JL pMOS and JL nMOS transistors of IM nMOS and AM pMOS for temperatures below 150 ◦ C. At
[Fig. 7(a)] and IM nMOS and AM pMOS [Fig. 7(b)] as a room temperature, the IM device has the highest GIDL because
function of gate voltage at different temperatures. The leakage it is the only device with true p-n junctions. The temperature
currents at low drain voltages were too small to be measured. dependence of the GIDL current suggests it dominated by BBT.
Therefore, drain voltage was increased to VDS = ±2.5 V to The other devices have no p-n junctions and show lower
produce observable leakage currents. The evolution of leakage GIDL levels, with a temperature dependence suggesting that
current in all types of devices is shown in Fig. 8. All transistors BDT is the dominant GIDL mechanism. The JL FETs have
show low leakage levels (below 100 pA) at a temperature lower overall GIDL currents, possibly because the absence of
of 200 ◦ C. a source and drain implantation step reduces the defect density
GIDL manifests itself as an increase of drain current when at the drain-channel contact (or “junction”).
a negative (positive) gate voltage is applied to the gate of
an n-channel (p-channel) device. It increases with junction
IV. C ONCLUSION
abruptness as well as reduction of gate oxide thickness [9].
The GIDL is one of the major problems for dynamic random The temperature dependence of the main electrical parame-
access memory of data retention time [10]. The GIDL current ters of JL silicon nanowire transistors has been analyzed. Direct
is caused by band-to-band tunnelling (BBT) or band-to-defect comparison was made to silicon nanowire (trigate) AM and
tunnelling (BDT) in the gate and drain overlap region. The IM MOSFETs. Variation of parameters such as threshold volt-
GIDL is sensitive to temperature, particularly when BDT is the age and ON–OFF current characteristics was analyzed. The
dominant GIDL mechanism [11]. Fig. 9 shows the extracted JL silicon nanowire FET has a lager variation of threshold

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624
Fig. 7. Measured IDS –VGS characteristics at high drain voltage at various
temperatures of (a) JL nMOS and JL pMOS and (b) IM nMOS and AM pMOS
silicon nanowire FETs (VDS = ±2.5 V, L = 1 µm, and W = 20 nm).
Fig. 8. Extracted drain OFF current of JL nMOS, JL pMOS, IM nMOS, and
AM pMOS as a function of temperature (extracted from Fig. 7; VDS = ±2.5 V,
L = 1 µm, and W = 20 nm).
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Fig. 9. GIDL of JL nMOS, JL pMOS, IM nMOS, and AM pMOS as a
function of temperature (extracted from Fig. 7; VDS = ±2.5 V, L = 1 µm,
and W = 20 nm).
voltage with temperature than the standard IM and AM FETs.
Unlike in classical devices, the drain current of JL FETs in-
creases when temperature is increased.
ACKNOWLEDGMENT
The authors would like to thank B. O’Neill, A. Blake,
M. White, A.M. Kelleher, B. McCarthy, S. Gheorghe, and
R. Murphy for device fabrication.
R EFERENCES
[1] International Technology Roadmap for Semiconductor, 2008. [Online].
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J. P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys.
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[3] G. Groeseneken, J. P. Colinge, H. E Maes, J. C. Alderman, and
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[4] K. Akarvardar, A. Mercha, E. Simoen, V. Subramanian, C. Claeys,
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of-the-art triple-gate transistors,” Microelectron. Reliab., vol. 47, no. 12,
pp. 2065–2069, Dec. 2007.
[5] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI.
New York: Springer, 2004.
[6] P. Aminzadeh, M. Alavi, and D. Scharfetter, “Temperature dependence of
substrate current and hot carrier-induced degradation at low drain bias,”
in VLSI Symp. Tech. Dig., 1998, pp. 178–179.
[7] D. S. Jeon and D. E. Burk, “MOSFET inversion layer motilities—A
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[8] G. Ghibaudo, “New method for the extraction of MOSFET parameters,”
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[9] S. A. Parke, J. E. Moon, C. Wann, P. K. Ko, and C. Hu, “Design for
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[10] T. Hamamoto, S. Sugiura, and S. Sawada, “On the retention time distribu-
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[11] D. Rideau, A. Dray, F. Gilibert, F. Agut, L. Giguerre, G. Gouget,
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1981, p. 28.
LEE et al.: HIGH-TEMPERATURE PERFORMANCE OF SILICON JUNCTIONLESS MOSFETs
Isabelle Ferain received the M.Sc. degree in electri-
cal engineering from both the Faculté Polytechnique
de Mons, Mons, Belgium, and the Ecole Supérieure
d’Electricité, Gif-sur-Yvette, France, in 2001 and
the Ph.D. degree in electrical engineering from the
Katholieke Universiteit Leuven, Leuven, Belgium,
in 2008.
In 2001, she joined AMI Semiconductor (now
ON Semiconductor), Oudenaarde, Belgium, where
she was involved in SPC and line yield control.
From 2004 to 2008 she was with IMEC, Leuven,
Belgium, where she worked on the integration and electrical characterization
of metal gate electrodes on fully depleted multiple-gate FETs (MuGFETs)
on silicon-on-insulator. She is currently a Postdoctoral Researcher with the
Tyndall National Institute, University College Cork, Cork, Ireland, working on
the characterization of low temperature directly bonded substrates and on the
fabrication of nanowires.
Aryan Afzalian (S’03–M’05) was born in Ottignies,
Belgium, in 1977. He received the B.S. degree in
electromechanical engineering and the Ph.D. degree
from the Université Catholique de Louvain, Louvain-
la-Neuve, Belgium, in 2000 and 2006, respectively.
He is currently a Postdoctoral Research Fellow
at the Tyndall National Institute, University Col-
lege Cork, Cork, Ireland, working on semiconductor
physics and, in particular, on modeling quantum
transport in nanoscale silicon devices, such as SOI
multigate nanowire transistors. His previous works
include modeling, optimization, and characterization of SOI integrated optical
sensors and analog circuits such as APS, optical communication receivers, and
UV detectors, with an emphasis on physical modeling and multidisciplinary
approach.
Dr. Afzalian is the recipient of the 2001 AILV price for his M.S. thesis on
SOI image sensors.
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Chi-Woo Lee received the B.S. degree in physics Ran Yan received the B.S. degree in electronic
from the University of Suwon, Hwaseong, Korea, science and technology from Tsinghua University,
and the M.S. degree in electronic engineering from Beijing, China, in 2006. She then became a Research
the University of Incheon, Incheon, Korea, in 2004 Assistant in the Computer-Aided-Design (CAD)
and 2006, respectively. He is currently working to- Technologies at the Research Center of Microelec-
ward the Ph.D. degree on the physics of multigate tronics Institute, Tsinghua University. She is cur-
SOI MOSFETs at the Tyndall National Institute, rently working toward the Ph.D. degree in physics
University College Cork, Cork, Ireland. of multigate SOI MOSFETs at the Tyndall National
From 2004 and 2006, he was teaching and was Institute, University College Cork, Cork, Ireland.
a Research Assistant at the University of Incheon,
Incheon, Korea.
Nima Dehdashti Akhavan received the B.S. de-
Adrien Borne is currently working toward a gree in electronic engineering and the M.S. degree
B.S. degree with the Institut de Microélectronique in electronic engineering from Semnan University,
Electromagnétisme et Photonique (IMEP)-Phelma, Semnan, Iran, in 2005 and 2007, respectively. He
Micro and Nanotechnology Innovation Centre is currently working toward the Ph.D. degree on
(MINATEC), Grenoble National Polytechnic Insti- modeling of multigate SOI MOSFETs at the Tyndall
tute (INPG), Grenoble, France. National Institute, University College Cork, Cork,
He was with the Tyndall National Institute, Uni- Ireland.
versity College Cork, Cork, Ireland, for a 2009 sum-
mer internship.
Pedram Razavi received the B.Sc. degree in elec-
tronic engineering from Gilan University, Rasht,
Iran, in 2004 and the M.Sc. degree in electronic
engineering from Semnan University, Semnan, Iran,
in 2008. He is currently working toward the Ph.D.
degree on modeling and simulation of ultrascaled
SOI multigate transistors at the Tyndall National
Institute, University College Cork, Cork, Ireland.
Jean-Pierre Colinge (M’86–SM’89–F’96) received
the B.S. degree in philosophy, the B.S. degree
in electrical engineering, and the Ph.D. degree in
applied sciences from the Université Catholique
de Louvain, Louvain-la-Neuve, Belgium, in 1980,
1980, and 1984, respectively.
He has been with the Centre National d’Etudes des
Télécommunications, Meylan, France, the Hewlett-
Packard Laboratories, Palo Alto, CA, and IMEC,
Leuven, Belgium, where he was involved in SOI
technology for VLSI and special device applications.
From 1991 to 1997, he was a Professor with the Université Catholique de
Louvain, where he led a research team in the field of SOI technology for low-
power radiation-hard high-temperature RF applications and reduced-dimension
devices (thin double-gate and quantum-wire MOSFETs). From 1997 to 2006,
he was a Professor with the University of California, Davis, where he worked
on advanced multigate SOI MOS devices. He is currently a Professor with the
Tyndall National Institute, University College Cork, Cork, Ireland, working on
the modeling, fabrication, and characterization of advanced SOI MOS devices.
He is the author of more than 300 scientific papers and four books in the field
of SOI and two books on semiconductor device physics.
Prof. Colinge has been a member of the committee of several conferences,
including the International Electron Devices Meeting and the International
Conference on Solid State Devices and Materials, and was the General Chair-
man of the IEEE SOS/SOI Technology Workshop in 1988.