1

BASIC GATES
While each logical element or condition must always have a logic
value of either "0" or "1", we also need to have ways to combine different
logical signals or conditions to provide a logical result.

For example, consider the logical statement: "If I move the switch on
the wall up, the light will turn on." At first glance, this seems to be a correct
statement. However, if we look at a few other factors, we realize that
there's more to it than this. In this example, a more complete statement
would be: "If I move the switch on the wall up and the light bulb is good
and the power is on, the light will turn on."

If we look at these two statements as logical expressions and use

logical terminology, we can reduce the first statement to:

Light = Switch

This means nothing more than that the light will follow the action of the
switch, so that when the switch is up/on/true/1 the light will also be
on/true/1. Conversely, if the switch is down/off/false/0 the light will also be
off/false/0.

Looking at the second version of the statement, we have a slightly

more complex expression:

Light = Switch and Bulb and Power

Normally, we use symbols rather than words to designate the and

function that we're using to combine the separate variables of Switch,
Bulb, and Power in this expression. The symbol normally used is a dot,
which is the same symbol used for multiplication in some mathematical
expressions. Using this symbol, our three-variable expression becomes:

Light = Switch Bulb Power

When we deal with logical circuits (as in computers), we not only need
to deal with logical functions; we also need some special symbols to
denote these functions in a logical diagram. There are three fundamental
logical operations, from which all other functions, no matter how complex,
can be derived. These functions are named and, or, and not. Each of
these has a specific symbol and a clearly-defined behavior, as follows:
Binary gates deals with digital signal & digital is 0 or 1.
 2

The AND Gate

The AND gate implements the AND

function. With the gate shown to the left,
both inputs must have logic 1 signals
applied to them in order for the output to
be a logic 1. With either input at logic 0,
the output will be held to logic 0.

An algebraic function is F = x - y

There is no limit to the number of

inputs that may be applied to an AND
function, so there is no functional limit to
the number of inputs an AND gate may
have. However, for practical reasons,
commercial AND gates are most
commonly manufactured with 2, 3, or 4
inputs. A standard Integrated Circuit (IC)
package contains 14 or 16 pins, for
practical size and handling. A standard
14-pin package can contain four 2-input
gates, three 3-input gates, or two 4-input
gates, and still have room for two pins for
power supply connections.

The truth table of And can be given

as.
x y f
0 0 0
0 1 0
1 0 0
1 1 1
Where x & y are inputs f is output.
The OR Gate

The OR gate is sort of the reverse of

the AND gate. The OR function, like its
verbal counterpart, allows the output to be
true (logic 1) if any one or more of its
inputs are true. Verbally, we might say, "If
it is raining OR if I turn on the sprinkler,
the lawn will be wet." Note that the lawn
will still be wet if the sprinkler is on and it
is also raining. This is correctly reflected
by the basic OR function.
 3

In symbols, the OR function is

designated with a plus sign (+). In logical
diagrams, the symbol to the left
designates the OR gate.

An algebraic function is f = x + y

As with the AND function, the OR

function can have any number of inputs.
However, practical commercial OR gates
are mostly limited to 2, 3, and 4 inputs, as
with AND gates.

The truth table of And can be given

as.
x y f
0 0 0
0 1 1
1 0 1
1 1 1
Where x & y are inputs f is output.

The NOT Gate, or Inverter

The inverter is a little different from

AND and OR gates in that it always has
exactly one input as well as one output.
Whatever logical state is applied to the
input, the opposite state will appear at the
output.

The NOT function, as it is called, is

necesasary in many applications and
highly useful in others. A practical verbal
application might be:

The door is NOT locked = You may

enter

The NOT function is denoted by a

horizontal bar over the value to be
inverted, as shown in the figure In some
cases a single quote mark (') may also be
used for this purpose: 0' = 1 and 1' = 0.
For greater clarity in some logical
expressions, we will use the overbar most
 4

of the time.

It has circle at the output which

denotes the logical inversion. The circle
could have been placed at the input
instead, and the logical meaning would
still be the same.
The truth table of And can be given
as.
x f
0 1
0 0
Where x & y are inputs f is output.

The logic gates shown above are used in various combinations to

perform tasks of any level of complexity. Some functions are so commonly
used that they have been given symbols of their own, and are often
packaged so as to provide that specific function directly.

While the three basic functions AND, OR, and NOT are sufficient to
accomplish all possible logical functions and operations, some
combinations are used so commonly that they have been given names
and logic symbols of their own.

The first is called NAND, and consists of an AND function followed by

a NOT function. The second, as you might expect, is called NOR. This is
an OR function followed by NOT. The third is a variation of the OR
function, called the Exclusive-OR, or XOR function. As with the three basic
logic functions, each of these derived functions has a specific logic symbol
and behavior, which we can summarize as follows:

The NAND Gate

The NAND gate implements the

NAND function, which is exactly inverted
from the AND function you already
examined. With the gate shown to the left,
both inputs must have logic 1 signals
applied to them in order for the output to
be a logic 0. With either input at logic 0,
the output will be held to logic 1.
The circle at the output of the NAND
gate denotes the logical inversion, just as
 5

it did at the output of the inverter note that

the overbar is a solid bar over both input
values at once. This shows that it is the
AND function itself that is inverted, rather
than each separate input.
As with AND, there is no limit to the
number of inputs that may be applied to a
NAND function, so there is no functional
limit to the number of inputs a NAND gate
may have. However, for practical reasons,
commercial NAND gates are most
commonly manufactured with 2, 3, or 4
inputs, to fit in a 14-pin or 16-pin
package.

The algebraic function is

F = (xy) for NAND gate

x y f
0 0 1
0 1 1
1 0 1
1 1 0

The NOR Gate

The NOR gate is an OR gate with the

output inverted. Where the OR gate allows
the output to be true (logic 1) if any one or
more of its inputs are true, the NOR gate
inverts this and forces the output to logic 0
when any input is true.

In symbols, the NOR function is

designated with a plus sign (+), with an
overbar over the entire expression to
indicate the inversion. In logical diagrams,
the symbol to the left designates the NOR
gate. As expected, this is an OR gate with
a circle to designate the inversion.

The NOR function can have any

number of inputs, but practical commercial
NOR gates are mostly limited to 2, 3, and
4 inputs, as with other gates in this class,
to fit in standard IC packages.
 6

F = xy’ + x’y
= x + y where x & y are inputs.
x y f
0 0 0
0 1 1
1 0 1
1 1 0

The Exclusive-OR, or XOR Gate

The Exclusive-OR, or XOR function is

an interesting and useful variation on the
basic OR function. Verbally, it can be
stated as, "Either A or B, but not both."
The XOR gate produces a logic 1 output
only if its two inputs are different. If the
inputs are the same, the output is a logic
0.

The XOR symbol is a variation on the

standard OR symbol. It consists of a plus
(+) sign with a circle around it. The logic
symbol, as shown here, is a variation on
the standard OR symbol.

Unlike standard OR/NOR and

AND/NAND functions, the XOR function
always has exactly two inputs, and
commercially manufactured XOR gates
are the same. Four XOR gates fit in a
standard 14-pin IC package.

F = xy’ + x’y
= x + y where x & y are inputs.
x y f
0 0 0
0 1 1
1 0 1
1 1 0

The three derived functions shown above are by no means the only
ones, but these form the basis of all the others.
 7

Derivation X-OR gate

Exclusive-OR, or XOR function can be described verbally as, "Either A

or B, but not both." In the realm of digital logic there are several ways of
stating this in a more detailed and precise format. We won't go here into
such devices as Truth tables and graphic representations. We will stick
with the more complete verbal statement, "NOT A and B, or A and NOT
B."

The circuit required to implement this description is shown below:

The practical problem with the circuit above is that it contains three
different kinds of gates: AND, OR, and NOT. While this illustrates a
practical application using all three of the basic gate types, it is
cumbersome to construct on a printed circuit board.

There are commercial packages which contain four XOR gates, but
often only a single XOR function is wanted in a given application.

Exclusive – NOR or equivalence

Exclusive NOR gate can be defined as

F = xy + x’ y’
=x.y

The truth table is shown as & symbol is

 8

x y f
0 0 1
0 1 0
1 0 0
1 1 1

This can easily be done with a single quad two-input NAND gate, as
shown in the circuit below:

There are many ways in which the simple logic gates we have
examined can be combined to perform useful functions. Some of these
circuits produce outputs which are only dependent upon the current logic
states of all inputs. These are called combinational logic circuits. Other
circuits are designed to actually remember the past states of their inputs,
and to produce outputs based on those past signals as well as the current
states of their inputs. These circuits can act in accordance with a
sequence of input signals, and are therefore known as sequential logic
circuits.

Multiplexer

A digital multiplexer is a combinational circuit that selects binary

information form one of many input lines and direct it to a single output
line. The selection of a particular input line is controlled by a set of
selection lines. Normally there are 2^ input lines & n selected lines whose
it combinations determine which input is selected.

A two-input multiplexer is shown below.

 9

The multiplexer circuit is

typically used to combine two or
more digital signals onto a single
line, by placing them there at
different times. Technically, this is
known as time-division
multiplexing.

Input A is the addressing input,

which controls which of the two
data inputs, X0 or X1, will be
transmitted to the output. If the A
input switches back and forth at a
frequency more than double the
frequency of either digital signal,
0 both signals will be accurately
input 1 4x1 reproduced, and can be separated
outp
2 y again by a demultiplexer circuit
3 Mux synchronized to the multiplexer.

In multiplexer one of the input

is selected as output depending
Select upon select input. In general a 2 to
dig – block diagram
1 line multiplexer is constructed
from an n-to2n decoder by adding
to it 2 input lines, one of each and
gate. The outputs of the And gates
are applied to a single OR gate to
provide the l-line output.

Function table
S1 S0 Y
0 0 IO
0 1 I1
1 0 I2
1 1 I3

This size of a multiplexey is specified by the number 2 of its input lines

and the single output line. It is then implied that it also contains n selection
lines. A multiplexes is often abbreviated as MUX.

Multiplexer is a used for connecting two or more sources to a single

destination among computer units & it is useful for constructing a common
bus system.

A very common application for this type of circuit is found in

computers, where dynamic memory uses the same address lines for both
 10

row and column addressing. A set of multiplexers is used to first select the
row address to the memory, then switch to the column address. This
scheme allows large amounts of memory to be incorporated into the
computer while limiting the number of copper traces required to connect
that memory to the rest of the computer circuitry. In such an application,
this circuit is commonly called a data selector.

Multiplexers are not limited to two data inputs. If we use two addressing
inputs, we can multiplex up to four data signals. With three addressing
inputs, we can multiplex eight signals. If you would like to see a
demonstration of a four-input multiplexer, This demonstration requires 64
separate images, each approximately 4K bytes in size, so it will take a
little while to load. For this reason, it is not included in the list of digital
pages at the top of each page.

Decoder and demultiplexer:

The opposite of the multiplexer circuit, logically enough, is the

demultiplexer. This circuit takes a single data input and one or more
address inputs, and selects which of multiple outputs will receive the input
signal. The same circuit can also be used as a decoder, by using the
address inputs as a binary number and producing an output signal on the
single output that matches the binary address input. In this application, the
data input line functions as a circuit enabler — if the circuit is disabled, no
output will show activity regardless of the binary input number.

A one-line to two-line decoder/demultiplexer is shown below.

This circuit uses the

same AND gates and the
same addressing scheme
as the two-input
multiplexer circuit shown in
these pages. The basic
difference is that it is the
inputs that are combined
and the outputs that are
separate. By making this
change, we get a circuit
that is the inverse of the
two-input multiplexer. If
you were to construct both
circuits on a single
breadboard, connect the
multiplexer output to the
data IN of the
 11

demultiplexer, and drive

the (A)ddress inputs of
both circuits with the same
signal, you would find that
the initial X0 input would
be transmitted to OUT0
and the X1 input would
reach only OUT1.

The one problem with

this arrangement is that
one of the two outputs will
be inactive while the other
is active. To retain the
output signal, we need to
add a latch circuit that can
follow the data signal while
it's active, but will hold the
last signal state while the
other data signal is active.
An excellent circuit for this
is the D (or Data) Latch.
By placing a latch after
each output and using the
Addressing input (or its
inverse) to control them,
we can maintain both
output signals at all times.
If the Address input
changes much more
rapidly than the data
inputs, the output signals
will match the inputs
faithfully.

Like multiplexers, demultiplexers are not limited to two data signals. If

we use two addressing inputs, we can demultiplex up to four data signals.
With three addressing inputs, we can demultiplex eight signals. The
demonstration of the 2-to-4 line decoder/demultiplexer is much smaller
than the demo for the four-input multiplexer, because it has fewer
independent input signals. With one data input and two addressing inputs,
the decoder/demultiplexer only needs 8 images for the full demonstration.

Basic NAND gate:

In order for a logical circuit to "remember" and retain its logical state even
after the controlling input signal(s) have been removed, it is necessary for
 12

the circuit to include some form of feedback. We might start with a pair of
inverters, each having its input connected to the other's output. The two
outputs will always have opposite logic levels.

The problem with this is that we don't have any additional inputs that
we can use to change the logic states if we want. We can solve this
problem by replacing the inverters with NAND or NOR gates, and using
the extra input lines to control the circuit.

The circuit shown below is a basic NAND latch. The inputs are
generally designated "S" and "R" for "Set" and "Reset" respectively.
Because the NAND inputs must normally be logic 1 to avoid affecting the
latching action, the inputs are considered to be inverted in this circuit.

The outputs of any single-bit latch or memory are traditionally

designated Q and Q'. In a commercial latch circuit, either or both of these
may be available for use by other circuits. In any case, the circuit itself is:

For the NAND latch circuit, both

inputs should normally be at a logic 1
level. Changing an input to a logic 0
level will force that output to a logic 1.
The same logic 1 will also be applied
to the second input of the other NAND
gate, allowing that output to fall to a
logic 0 level. This in turn feeds back to
the second input of the original gate,
forcing its output to remain at logic 1.

Applying another logic 0 input to

the same gate will have no further
effect on this circuit. However,
applying a logic 0 to the other gate will
cause the same reaction in the other
direction, thus changing the state of
the latch circuit the other way.

Note that it is forbidden to have

both inputs at a logic 0 level at the
same time. That state will force both
outputs to a logic 1, overriding the
feedback latching action. In this
condition, whichever input goes to
logic 1 first will lose control, while the
other input (still at logic 0) controls the
resulting state of the latch. If both
 13

inputs go to logic 1 simultaneously, the

result is a "race" condition, and the
final state of the latch cannot be
determined ahead of time.

This circuit has quite a number of limitations, and can be improved in

many ways as you'll see shortly. However, it does have a very practical
application almost without changes. Any mechanical switch experiences a
phenomenon called "contact bounce." Whenever you press the button or
change the switch position, the physical contacts will flex a little, causing
them to make and break several times before settling down. You don't
notice this when turning on a light in your home, but digital circuits are fast
enough that they do notice this behavior and transmit it faithfully. If you
are trying to test a new digital circuit by sending it one clock pulse at a
time, this will cause all sorts of headaches.

The solution is to use an SPDT (Single-Pole, Double-Throw)

pushbutton or switch, as shown in the figure to the right. Normally, the
switch is of the break-before-make type, so there will be some part of the
switch motion when all three contacts are disconnected from each other.
Now, the unconnected input is held at a logic 1 through its resistor (an
electronic component that allows an electrical connection without causing
a dead short), while the connected input is held at logic 0 by the direct
connection through the switch.

When the switch is moved to the other setting or the button is pressed,
the very first contact will cause the latch to change state, but additional
bounces will have no further effect. This eliminates the contact bounce
and sends a single, clean digital transition to the next circuit. All of the
interactive digital demonstrations behave in a debounced fashion, and
would use this type of circuit if constructed physically.

One problem with the basic RS NAND latch is that the input levels
need to be inverted, sitting idle at logic 1, in order for the circuit to work. It
would be helpful, as well as more intuitive, if we had normal inputs which
would idle at logic 0, and go to logic 1 only to control the latch. This much
we can do simply by placing inverters at the inputs.
 14

However, there is another problem we need to address: How to control

when the latch is allowed to change state, and when it is not. This is
necessary if we have a group of latches and want to be sure they all
change state (or not) at the same time. We'll see how both of these
concerns can be easily addressed on the next page.

RS Flip Flop

To adjust the clocked RS latch for edge triggering, we must actually

combine two identical clocked latch circuits, but have them operate on
opposite halves of the clock signal. The resulting circuit is commonly
called a flip-flop, because its output can first flip one way and then flop
back the other way. The clocked RS latch is also sometimes called a flip-
flop, although it is more properly referred to as a latch circuit.

The two-section flip-flop is also known as a master-slave flip-flop,

because the input latch operates as the master section, while the output
section is slaved to the master during half of each clock cycle.

The edge-triggered RS NAND flip-flop is shown below.

Q S R Q (t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 indeterminate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 indeterminate

fig. Characteristics table of clocked RS FF

 15

The edge-triggered RS flip-flop actually consists of two identical RS

latch circuits, as shown above. However, the inverter connected between
the two CLK inputs ensures that the two sections will be enabled during
opposite half-cycles of the clock signal. This is the key to the operation of
this circuit.

If we start with the CLK input at logic 0 as initially depicted above, the
S and R inputs are disconnected from the input (master) latch. Therefore,
any changes in the input signals cannot affect the state of the final
outputs.

When the CLK signal goes to logic 1, the S and R inputs are able to
control the state of the input latch, just as with the single RS latch circuit
you already examined. However, at the same time the inverted CLK signal
applied to the output (slave) latch prevents the state of the input latch from
having any effect here. Therefore, any changes in the R and S input
signals are tracked by the input latch while CLK is at logic 1, but are not
reflected at the Q and Q' outputs.

When CLK falls again to logic 0, the S and R inputs are again isolated
from the input latch. At the same time, the inverted CLK signal now allows
the current state of the input latch to reach the output latch. Therefore, the
Q and Q' outputs can only change state when the CLK signal falls from a
logic 1 to logic 0. This is known as the falling edge of the CLK signal;
hence the designation edge-triggered flip-flop.

By going to a master-slave structure and making the flip-flop edge-

triggered, we have made sure that we can precisely control the moment
when all flip-flops will change state. We have also allowed plenty of time
for the master latch to respond to the input signals, and for those input
signals to change and settle following the previous change of state.

There is still one problem left to solve: the possible race condition
which may occur if both the S and R inputs are at logic 1 when CLK falls
from logic 1 to logic 0. In the example above, we automatically assume
that the race will always end with the master latch in the logic 1 state, but
this will not be certain with real components. Therefore, we need to have a
way to prevent race conditions from occurring at all. That way we won't
have to figure out which gate in the circuit won the race on this particular
occasion.

The solution is to add some additional feedback from the slave latch to
the master latch. The resulting circuit is called a JK flip-flop.
 16

JK flip flop

To prevent any possibility of a "race" condition occurring when both the S

and R inputs are at logic 1 when the CLK input falls from logic 1 to logic 0,
we must somehow prevent one of those inputs from having an effect on
the master latch in the circuit. At the same time, we still want the flip-flop
to be able to change state on each falling edge of the CLK input, if the
input logic signals call for this. Therefore, the S or R input to be disabled
depends on the current state of the slave latch outputs.

If the Q output is a logic 1 (the flip-flop is in the "Set" state), the S input
can't make it any more set than it already is. Therefore, we can disable the
S input without disabling the flip-flop under these conditions. In the same
way, if the Q output is logic 0 (the flip-flop is Reset), the R input can be
disabled without causing any harm. If we can accomplish this without too
much trouble, we will have solved the problem of the "race" condition.

The circuit below shows the solution. To the RS flip-flop we have

added two new connections from the Q and Q' outputs back to the original
input gates. Remember that a NAND gate may have any number of
inputs, so this causes no trouble. To show that we have done this, we
change the designations of the logic inputs and of the flip-flop itself. The
inputs are now designated J (instead of S) and K (instead of R). The entire
circuit is known as a JK flip-flop.

Fig. Clocked master slave JK FF

In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q
and Q' outputs will only change state on the falling edge of the CLK signal,
and the J and K inputs will control the future output state pretty much as
before. However, there are some important differences.
 17

Q J K Q (t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Since one of the two logic inputs is always disabled according to the
output state of the overall flip-flop, the master latch cannot change state
back and forth while the CLK input is at logic 1. Instead, the enabled input
can change the state of the master latch once, after which this latch will
not change again. This was not true of the RS flip-flop.

If both the J and K inputs are held at logic 1 and the CLK signal
continues to change, the Q and Q' outputs will simply change state with
each falling edge of the CLK signal. (The master latch circuit will change
state with each rising edge of CLK.) We can use this characteristic to
advantage in a number of ways. A flip-flop built specifically to operate this
way is typically designated as a T (for Toggle) flip-flop. The lone T input is
in fact the CLK input for other types of flip-flops.

The JK flip-flop must be edge triggered in this manner. Any level-

triggered JK latch circuit will oscillate rapidly if all three inputs are held at
logic 1. This is not very useful. For the same reason, the T flip-flop must
also be edge triggered. For both types, this is the only way to ensure that
the flip-flop will change state only once on any given clock pulse.

Because the behavior of the JK flip-flop is completely predictable

under all conditions, this is the preferred type of flip-flop for most logic
circuit designs. The RS flip-flop is only used in applications where it can
be guaranteed that both R and S cannot be logic 1 at the same time.

At the same time, there are some additional useful configurations of

both latches and flip-flops. In the next pages, we will look first at the major
configurations and note their properties. Then we will see how multiple
flip-flops or latches can be combined to perform useful functions and
operations.

D flip flop

The edge-triggered D flip-flop is easily derived from its RS counterpart.

The only requirement is to replace the R input with an inverted version of
the S input, which thereby becomes D. This is only needed in the master
latch section; the slave remains unchanged.
 18

One essential point about the D flip-flop is that when the clock input
falls to logic 0 and the outputs can change state, the Q output always
takes on the state of the D input at the moment of the clock edge. This
was not true of the RS and JK flip-flops. The RS master section would
repeatedly change states to match the input signals while the clock line is
logic 1, and the Q output would reflect whichever input most recently
received an active signal. The JK master section would receive and hold
an input to tell it to change state, and never change that state until the
next cycle of the clock. This behavior is not possible with a D flip-flop.

Q D Q (t + 1
0 0 0
0 0 1
1 0 0
1 1 1

The edge-triggered D NAND flip-flop is shown below.

2 Note that because of the feedback connection in the JK FF, a CP

signal which remains a 1 (while J = K = 1) after the output have been
complemented once will cause repeated & continuous transition, the clock
pulses must have a time direction which is shorter than the propagation
delay through the flip flop. This is a restrictive requirement since the
operation of the circuit depends on the width of the pulses. Fro this
reason. JK flip flops are never construction.
 19

Fig. Logic dig of T – FF

Q T Q (t + 1)
0 0 0
0 1 1
1 0 1
1 1 0

Digital Counter
One common requirement in digital circuits is counting, both forward
and backward. Digital clocks and watches are everywhere, timers are
found in a range of appliances from microwave ovens to VCRs, and
counters for other reasons are found in everything from automobiles to
test equipment.

A sequential circuit that goes through a prescribed sequence of states

upon the application of input pulses is called a counter. The input pulses
called count pulses may be clock pulses or they may orgimate from an
external source and may occur at prescribed intervals of timer at random.
In a counter the sequence of states may follow a binary count or any other
sequence of states.
An n bit binary counter consists of n flipflops & can count in binary
from o to 2n- 1.
 20

In the 4-bit counter to

the right, we are using
edge-triggered master-
slave flip-flops similar to
those in the Sequential
portion of these pages.
The output of each flip-
flop changes state on the
falling edge (1-to-0
transistion) of the T input.

The count held by

this counter is read in the
reverse order from the
order in which the flip-
flops are triggered. Thus,
output D is the high order
of the count, while output
A is the low order. The
binary count held by the
counter is then DCBA,
and runs from 0000
(decimal 0) to 1111
(decimal 15). The next
clock pulse will cause the
counter to try to
increment to 10000
(decimal 16). However,
that 1 bit is not held by
any flip-flop and is
therefore lost. As a result,
the counter actually
reverts to 0000, and the
count begins again.
 21

Instead of changing
the state of the input
clock with each click, you
will send one complete
clock pulse to the
counter when you click
the input button. The
button image will reflect
the state of the clock
pulse, and the counter
image will be updated at
the end of the pulse. For
a clear view without
taking excessive time,
each clock pulse has a
duration or pulse width of
300 ms (0.3 second).
The demonstration
system will ignore any
clicks that occur within
the duration of the pulse.
A major problem with the counters is that the individual flip-flops do
not all change state at the same time. Rather, each flip-flop is used to
trigger the next one in the series. Thus, in switching from all 1s (count =
15) to all 0s (count wraps back to 0), we don't see a smooth transistion.
Instead, output A falls first, changing the apparent count to 14. This
triggers output B to fall, changing the apparent count to 12. This in turn
triggers output C, which leaves a count of 8 while triggering output D to
fall. This last action finally leaves us with the correct output count of zero.
We say that the change of state "ripples" through the counter from one
flip-flop to the next. Therefore, this circuit is known as a "ripple counter."

This causes no problem if the output is only to be read by human

eyes; the ripple effect is too fast for us to see it. However, if the count is to
be used as a selector by other digital circuits (such as a multiplexer or
demultiplexer), the ripple effect can easily allow signals to get mixed
together in an undesirable fashion. To prevent this, we need to devise a
method of causing all of the flip-flops to change state at the same
moment. That would be known as a "synchronous counter" because the
flip-flops would be synchronized to operate in unison.

A Synchronous binary counter

In our initial discussion on counters (A Basic Digital Counter), we

noted the need to have all flip-flops in a counter to operate in unison with
each other, so that all bits in the ouput count would change state at the
 22

same time. To accomplish this, we need to apply the same clock pulse to
all flip-flops.

However, we do not want all flip-flops to change state with every clock
pulse. Therefore, we'll need to add some controlling gates to determine
when each flip-flop is allowed to change state, and when it is not. This
requirement denies us the use of T flip-flops, but does require that we still
use edge-triggered circuits. We can use either RS or JK flip-flops for this;
we'll use JK flip-flops for the demonstrations on this page.

States
Count
To determine the gates required at each flip- D C B A
flop input, let's start by drawing up a truth table for 0 0 0 0 0
all states of the counter. Such a table is shown to
the right. 0 0 0 1 1

Looking first at output A, we note that it must 0 0 1 0 2

change state with every input clock pulse.
0 0 1 1 3
Therefore, we could use a T flip-flop here if we
wanted to. We won't do so, just to make all of our 0 1 0 0 4
flip-flops the same. But even with JK flip-flops, all
we need to do here is to connect both the J and K 0 1 0 1 5
inputs of this flip-flop to logic 1 in order to get the
correct activity. 0 1 1 0 6

Flip-flop B is a bit more complicated. This 0 1 1 1 7

output must change state only on every other input
clock pulse. Looking at the truth table again, output 1 0 0 0 8
B must be ready to change states whenever output
1 0 0 1 9
A is a logic 1, but not when A is a logic 0. If we
recall the behavior of the JK flip-flop, we can see 1 0 1 0 10
that if we connect output A to the J and K inputs of
flip-flop B, we will see output B behaving correctly. 1 0 1 1 11

Continuing this line of reasoning, output C may 1 1 0 0 12

change state only when both A and B are logic 1. 1 1 0 1 13
We can't use only output B as the control for flip-
flop C; that will allow C to change state when the 1 1 1 0 14
 23

counter is in state 2, causing it to switch directly

from a count of 2 to a count of 7, and again from a
count of 10 to a count of 15 — not a good way to
count. Therefore we will need a two-input AND
gate at the inputs to flip-flop C. Flip-flip D requires a
three-input AND gate for its control, as outputs A, 1 1 1 1 15
B, and C must all be at logic 1 before D can be
allowed to change state.

The resulting circuit is shown in the

demonstration below.

States
Count
Johnson Counter A B C D E
0 0 0 0 0 0
In some cases, we want a counter that
provides individual digit outputs rather than a 1 0 0 0 0 1
binary or BCD output. Of course, we can do
this by adding a decoder circuit to the binary 1 1 0 0 0 2
counter. However, in many cases it is much
1 1 1 0 0 3
simpler to use a different counter structure,
that will permit much simpler decoding of 1 1 1 1 0 4
individual digit outputs.
1 1 1 1 1 5
For example, consider the counting
sequence to the right. It actually resembles 0 1 1 1 1 6
the behavior of a shift register more than a 0 0 1 1 1 7
counter, but that need not be a problem.
0 0 0 1 1 8
 24

Indeed, we can easily use a shift register to

implement such a counter. In addition, we can
notice that each legal count may be defined
by the location of the last flip-flop to change
states, and which way it changed state. This
can be accomplished with a simple two-input
AND or NOR gate monitoring the output
states of two adjacent flip-flops. In this way,
we can use ten simple 2-input gates to
provide ten decoded outputs for digits 0-9.
This is known as the Johnson counting
sequence, and counters that implement this
approach are called Johnson Counters.

We could also make an octal counter by

using four flip-flops in this configuration. In
0 0 0 0 1 9
fact, this is done commercially: the CMOS ICs
4017 and 4022 are counters that implement
this technique easily and cheaply.

There is one caveat that must be

considered here: The 5-stage circuit uses five
flip-flops, and therefore has 32 possible
binary states, yet we only use ten states. The
4-stage counter uses only eight of 16 possible
states. We must include circuitry that will filter
out the illegal states and force this circuit to
go towards the correct counting sequence,
even if it finds itself in an illegal mode when
first powered up. This is not difficult, and the
demonstration circuit below includes the
necessary gating structure..
 25

The demonstration above initially implements only the legitimate

counting sequence of the Johnson counter.

However, you can see the count correction gates operating at the
bottom ,how they work.

Serial to Parallel shift Register

The term register can be used in a variety of specific applications, but

in all cases it refers to a group of flip-flops operating as a coherent unit to
hold data. This is different from a counter, which is a group of flip-flops
operating to generate new data by tabulating it.

In this context, a counter can be viewed as a specialized kind of

register, which counts events and thereby generates data, rather than just
holding the data or changing the way it is handled. More commonly,
however, counters are treated separately from registers. The two are then
handled as separate concepts which work together in many applications,
and which have some features in common.

The demonstration circuit below is known as a shift register because

data is shifted through it, from flip-flop to flip-flop. If you apply one byte (8
bits) of data to the initial data input one bit at a time, and apply one clock
pulse to the circuit after setting each bit of data, you will find the entire
byte present at the flip-flop outputs in parallel format. Therefore, this circuit
is known as a serial-in, parallel-out shift register. It is also known
sometimes as a shift-in register, or as a serial-to-parallel shift register.
 26

By standardized convention, the least significant bit (LSB) of the byte

is shifted in first.

The counterpart to the shift register above is the parallel-in, serial-out

shift register, sometimes called a shift-out register.

Parallel to Serial Shift register

Where there is a need for serial-to-parallel conversion, there is also a

need for parallel-to-serial conversion. The parallel-in, serial-out register (or
parallel-to-serial shift register, or shift-out register), however, is a bit more
complex than its counterpart. Since each flip-flop in the register must be
able to accept data from either a serial or a parallel source, a small two-
input multiplexer is required in front of each input. An extra input line
selects between serial and parallel input signals, and as usual the flip-
flops are loaded in accordance with a common clock signal.

The shift-out demonstration circuit below is limited to four bits so it can

fit horizontally on a reasonable page. A 4-bit shift register with parallel and
serial inputs and outputs will fit nicely into a 14-pin DIP IC.

In addition, this demonstration circuit introduces a new input button: a

mode control. The button labelled "S" indicates that the shift-out register is
currently in serial mode. Thus, input signals present at the serial input just
above the "S" button will be shifted into the register one by one with each
clock pulse. If you click on the "S" button, it will change state as expected,
but will also change to a "P" to indicate that the register now operates in
parallel mode. This enables you to load the entire register at once from the
parallel inputs just below the multiplexers. Thus, we can have a parallel
input and a serial output. The inclusion of a serial input makes it possible
to cascade multiple circuits of this type in order to increase the number of
bits in the total register. This is common practice in real-world circuits.
Because this circuit has both parallel and serial inputs and outputs, it
can serve as either a shift-in register or a shift-out register. This capability
can have advantages in many cases.
 27

The least significant bit (LSB) is always available first at the serial
output.

Summary:-

This chapter has introduced the logical gates and the advantages of the
logical gates can be extended to use them as Multiplexer or counter.
Multiplexer: It is a device which has many outputs.
Counter: Counter can be used tocount the value upto certain states.
Demultiplexer:: Demultiplexer is a device which has one input and many
outputs.
Review Exercises:
1. How NAND and NOR gates can be used as universal gates?
2. Draw the diagram of 3 bit asynchronous counter.
3. How 4 bit asynchronous counter can be used to count 10.