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Twin-Tub CMOS Fabrication
Twin-Tub CMOS Fabrication
Dr. D. V. Kamat
Professor, Department of E&C Engg.,
Manipal Institute of Technology, Manipal
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MOS Fabrication
CMOS fabrication
N-well process
P-well process
Twin-tub process
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TWIN-TUB CMOS PROCESS
N -type Si
Epitaxial layer
N -type Si
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TWIN-TUB CMOS PROCESS
SiO2
Epitaxial layer
N -type Si
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TWIN-TUB CMOS PROCESS
MASK 1
Positive Photoresist
SiO2
Epitaxial layer
N -type Si
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Removal of soluable photo resist using organic solvents
Positive Photoresist
SiO2
Positive Photoresist
Epitaxial layer
N - type Si
Epitaxial layer
N-type Si 7
TWIN-TUB CMOS PROCESS
SiO2
Epitaxial layer
N-type Si
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TWIN-TUB CMOS PROCESS
SiO2
N-Well
Epitaxial layer
N-type Si
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Formation of P-well using ion implantation
P-Well N-Well
N-type Si
P-Well N-Well
N-type Si 10
TWIN-TUB CMOS PROCESS
Polysilicon layer
Thinox
P-Well N-Well
Epitaxial layer
N-type Si
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Lithography(MASK2) to patternize polysilicon
Polysilicon layer
Thinox
P-Well N-Well
Epitaxial layer
N-type Si
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P-Well N-Well
N-type Si
P-Well N-Well
N-type Si
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Lithography(MASK3)
Poly Poly
Thinox
P-Well N-Well
Epitaxial layer
N-type Si
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P-Well N-Well
Epitaxial layer
N-type Si
N+ N+ N+
P-Well N-Well
Epitaxial layer
N-type Si 15
TWIN-TUB CMOS PROCESS
P+ N+ N+ P+ P+ N+
P-Well N-Well
Epitaxial layer
N-type Si
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TWIN-TUB CMOS PROCESS
Thickox
P+ N+ N+ P+ P+ N+
P-Well N-Well
Epitaxial layer
N-type Si
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TWIN-TUB CMOS PROCESS
Thickox
P+ N+ N+ P+ P+ N+
P-Well N-Well
Epitaxial layer
N-type Si
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Metallization and MASK 6 for Metal Patterning
VSS VDD
Vout
Thickox
+
PP+ N++ N++ P+ P+ N+
P-Well N-Well
Epitaxial layer
N-type Si
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RECAP OF TWIN-TUB CMOS PROCESS
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Twin-tub CMOS process
Merits:
Doping of substrate and diffusion regions can be controlled in an
independent manner. This helps in overcoming latch-up.
Twin-tub process allows separate optimization of the n- and p-
transistors
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Twin-tub CMOS
process
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Latch-up in Bulk CMOS
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Latch-up in Bulk CMOS
In Bulk CMOS structure there is a pair of parasitic
bipolar transistors.
The collector of each BJT is connected to the base of
the other transistor in a positive feedback structure.
A phenomenon called latchup can occur when
(i) both BJT's conduct, creating a low resistance path
between Vdd and GND and
(ii) the product of the gains of the two transistors in
the feedback loop, (β1 . β2 ) , is greater than one.
The result of latch-up is at the minimum a circuit
malfunction, and in the worst case, the destruction
of the device.
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Latch-up in Bulk CMOS
Latch-up may begin due to a noise spike or an improper
circuit connection. If sufficient current flows through Rsub
to turn on 𝑄2 (I. Rsub > 0.7 V), this will draw current
through Rwell. If the voltage drop across Rwell is high
enough, 𝑄1 will also turn on, and a self-sustaining low
resistance path between the power rails is formed. If the
gains are such that 𝜷𝟏 . 𝜷𝟐 > 𝟏, latch-up may occur. Once
latch-up has begun, the only way to stop it is to reduce the
current below a critical level, usually by removing power
from the circuit.
The most likely place for latch up to occur is in pad drivers,
where large voltage transients and large currents are
present. 26
Latch-up prevention
in Bulk CMOS
Fab/Design Approaches
[2] Reduce the well and substrate resistances, producing lower
voltage drops
• By increasing substrate doping level to reduce Rsub
• Place substrate and well contacts as close as possible to the source
connections of the MOS transistors to reduce the values of Rwell
and Rsub.
• To make low resistance contact to VDD to reduce Rwell
• Reduce the BJT gains by lowering the minority carrier lifetime
through Gold doping of the substrate (solution might cause
excessive leakage currents).
• Use of guardband rings 28
Latch-up
prevention in
Bulk CMOS
Fab/Design Approaches
[2] Reduce the well and substrate resistances, producing lower voltage drops
Use of guardband rings
Use p+ guardband rings connected to ground around nMOS transistors and n+
guard rings connected to VDD around pMOS transistors to reduce Rwell and
Rsub and to capture injected minority carriers before they reach the base of
the parasitic BJT.
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CMOS transistors with guard rings
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Contact
• reachdvkamath@yahoo.com
• dv.kamath@manipal.edu
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