This document describes a logic circuit with inputs S1, S2, and EN and outputs E1, F1, G1, and H1. The outputs are assigned logic expressions using the inputs and a MUX_OUT signal, where E1, F1, and G1 are assigned expressions combining MUX_OUT with S3, S4, and EN, and H1 is not yet defined.
This document describes a logic circuit with inputs S1, S2, and EN and outputs E1, F1, G1, and H1. The outputs are assigned logic expressions using the inputs and a MUX_OUT signal, where E1, F1, and G1 are assigned expressions combining MUX_OUT with S3, S4, and EN, and H1 is not yet defined.
This document describes a logic circuit with inputs S1, S2, and EN and outputs E1, F1, G1, and H1. The outputs are assigned logic expressions using the inputs and a MUX_OUT signal, where E1, F1, and G1 are assigned expressions combining MUX_OUT with S3, S4, and EN, and H1 is not yet defined.