OPEN ENDED EXPERIMENT

BASIC ELECTRONICS ENGINEERING (ES201)

3CSE-9Y

GROUP ENROLLMENT NAME EXPERIMENT

NUMBER
1 A2305218575 JALAJ AGARWAL To design a voltage
A2305218576 LAVNEESH SAINI regulator using Zener
A2305218579 VARSHA AGRAWAL diode that will
A2305218580 VABHAV SHARMA maintain a constant
output across load
resistor with a
variable dc input
voltage. Also
calculate maximum
Zener current and
power.
2 A2305218581 HIMANSHU VERMA To design voltage
A2305218584 SUNIDHI divider biasing circuit
A2305218586 RAHUL YADAV for BJT as an amplifier
A2305218587 ATUL CHAUDHARY to obtain the
frequency response
curve and determine
the mid frequency
gain, lower and
higher cutoff
frequency of the
amplifier circuit.
3 A2305218589 TANYA GOYAL Design a two stage
A2305218590 DIGANT CHANDELA transistor amplifier
A2305218591 SAURABH which employs
A2305218592 HEMANYA MEHTA emitter follower
configuration prior to
common base
configuration to
ensure that the
maximum percentage
of applied signal
 appears at the input
terminals of
common base
amplifier. The
following information
is given:
Emitter Follower: Z i
=10K Ω, Zo = 12Ω, A V
=1. Common Base: Z i
=26 Ω, Zo = 5.1KΩ, A
V =240.
R S = 1K Ω, R L = 8.2K
Ω
4 A2305218595 KARAN MALIK Design of common
A2305218597 VANSH GOYAL source amplifier for
A2305218598 CHANDAN SHARMA desired ac voltage
A2305218601 KSHITIZ SHARMA gain using self-biasing
circuit and determine
various parameters
and draw drain
characteristics.
5 A2305218602 SIDDHARTH MAKOL Design and
A2305218603 VANDIT JAIN implement clippers
A2305218604 AYUSH GUPTA (biased and unbiased)
A2305218605 SAKSHI NIMJE using OP-AMP IC 741
and other necessary
components.
6 A2305218606 GUNJAN SAINI Design and
A2305218737 ABHINAV SAXENA implement full
A2305218738 RAJ THAKUR subtractor by using
A2305218037 PRERIT RAJPUT minimum number of
A2305218065 YUGANSH PREET Universal gates.