Nombre: Víctor Andrés Euceda Flores

Número de Cuenta: 11211125

Docente: Ing. Franklin Sánchez

Asignatura: Microelectrónica

Actividad: Tarea#7.1

Sección: 47

Periodo: 1

Fecha: 03/09/19
Código

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX4_1 is
port (
E0: in STD_LOGIC;
E1: in STD_LOGIC;
E2: in STD_LOGIC;
E3: in STD_LOGIC;
S0: in STD_LOGIC;
S1: in STD_LOGIC;
F: out STD_LOGIC;
);
end MUX4_1;

architecture MUX4_1 of MUX4_1 is

begin

PROCESS (E0, E1, E2, E3, S0, S1)

BEGIN
IF (S1= ‘0’ AND S0= ‘0’) THEN
Q<=E0;
ELSIF (S1= ‘0’ AND S0= ‘1’) THEN
Q<=E1;
ELSIF (S1= ‘1’ AND S0= ‘0’) THEN
Q<=E2;
ELSE
Q<=E3;
END IF;

END PROCESS;

end MUX4_1;