Professional Documents
Culture Documents
Floorplan Terminology
Floorplan Terminology
1
Agenda:
● Basic Terminologies before Floorplan
● Input Files for Floorplan
● Introduction
● Floorplan Steps
● Target Utilization Display
● Density calculation
● Power Planning
2
Basic Terminologies before Floorplan:
● Aspect Ratio: It is the ratio between height
and width of the core or a block. Routing
resources, congestion, placement of stan-
dard cells, timing, clock-tree, placement
of IO pads and packaging depends on the
aspect ratio of the core or a block.
CORE 3
Basic Terminologies before Floorplan:
● Core Utilization: It defines the total area
occupied by the standard cells and macros
in the block or top-level design. Typically,
70-80% utilization is taken into account
for blocks as timing optimization involves
placement of buffers or inverters which
requires area.
○ R0 - No rotation.
○ MX - Mirror through x-axis.
○ MY - Mirror through y-axis.
○ R90 - Rotate 90 degrees counter-clockwise.
○ R180 - Rotate 180 degrees counter-clockwise.
○ R270 - Rotate 270 degrees counter-clockwise.
○ MX90 - Mirror through x-axis and rotate 90 degrees counter-clockwise.
○ MY90 - Mirror through y-axis and rotate 90 degrees counter-clockwise.
5
Basic Terminologies before Floorplan:
● Core Boundary: It is the area or region within which standard cells and
macros are placed in the design. From top-level of a design, core boundary
will be rectangular or square shaped. From block-level of a design, core
boundary may have rectangular or rectilinear shape.
6
Basic Terminologies before Floorplan:
● Instance: A single occurance or a single object of a standard cell type or a
macro or a block defined with a unique instance name. Ex: a 2-input AND
gate could be instantiated as CELL_AND_1 and a usb 2.0 macro could be
instantiated as USB_2_0_1.
8
Basic Terminologies before Floorplan:
● Physical Cells: These cells do not have any logical functionality in the
design. Some of the standard physical cells are tap cells, tie cells, endcap
cells, decap cells, filler cells, spare cells.
10
Basic Terminologies before Floorplan:
● Placement Grid: Placement grid is a multiple of the manufacturing grid in which
all the standard cells are placed. Based on the placement grid, rows are formed
and standard cells are placed.
● Power Domain: It is the collection of instances or blocks that share the same
supply voltage in a design. Each power domain has a separate library associated
with it.
● Routing Blockage: It is the area defined by the designer for the PnR tool to block
routing resources in single or multiple metal layers at a particular area. Routing
blockages can be created and removed at any point in the design based on the
requirements. It is possible to create routing blockages over a block or an
instance using it’s cell type or instance name without the area numbers.
11
Basic Terminologies before Floorplan:
● Row: Standard cell row is the area defined for placing standard cells in the
design. Every standard cell in the design sits on the standard cell row. The
row height is based on the standard cell height used in the design. Different
types of rows are possible in a design based on sites or heights of standard
cells used.
● Track: Track is a virtual line (guideline) for the PnR tool in which routing of
metal wires happen in the design. For each metal layer in the design, tracks
are defined for preferred and non-preferred direction with specific pitch
and offset. The PnR tool routes the metal wires by assuming the track at
the center of metal piece.
12
Basic Terminologies before Floorplan:
● Voltage Island: It is a dedicated area in the design which has its own row,
site, cells and power structure defined for better power consumption.
Level-shifters are used to convert from one voltage level to another.
13
Input files of Floorplan:
● Gate level netlist
● Logical (Timing) & Physical views of standard cells & all other IPs used in
the design
● Timing constraints (SDC)
● Power Intent (UPF / CPF)
● FP DEF & Scan DEF
● Technology file
● RC Co-efficient files
14
Introduction:
After given input files this is the first step of physical layout
implementation.
The early stage plan, a.k.a. a floorplan, is fleshed out with increasing
details with the design flow.
16
Floorplan Steps :
Step 1: Define the outline
Rectangular shape 17
Plus shape T-shape
Floorplan Steps (Step 2) :
Step 2: Define the Core Area
Core area
IO boundary 18
Floorplan Steps (Step 3):
Step 3: Placements of IO pads and
Pins
21
Floorplan Steps (Step 4) :
So we place those blocks or hard macros to complete the floorplan stage.Because
a good macro placement have following qualities :
Note: Hard macros are basically any kind of instance which is not a standard cell.
Example : Memory ,Ram , Rom & OTP
22
Target Utilization Display (Step 4):
The Module constraints, display a target utilization (TU=%) value to represent their physical design size.
This is an estimation of module utilization for the given size of the module where only standard cell and
hard macro areas are considered. Floorplan constraints such as placement blockages are not
considered. This value is calculated by the standard cells area plus the hard macros area, divided by
the module area. The initial TU values are calculated during design import.
The TU percentage helps judge the physical size of a module guide to customize the shape of the
module in the floorplan.
For example, modules P1 and P2 have a TU values of 77.2%. If the modules are reshaped with the same
area, they retain their TU values.
P1
P1
P2
P2 23
Target Utilization Display (Step 4):
We can determine the core utilization of the core and module sizes by total area
or density or standard cell density.
In determining the size of the core area and module guides, standard cells and
hard macros are treated the same.
In PnR tools we can specify the floorplan by using the Core Utilization or Cell
Utilization options.
25
Floorplan Steps:
Step 5: Power Planning = (Power + Ground ) routing
power grid network is created to distribute power to each part of the design
equally. Power router create power routings which is considered as pre routes.
And this pre routes will not modified by the detailed router when the signal nets
are routed.
Few things can be considered while we do power planning :
➔ All cells and macros need to be covered during power planning
➔ Minimize routing congestion
➔ Meet electro migration requirements
➔ Acceptable power drop.
26
Power Planning (block level) (Step 5):
2. Vertical
stripes
3.Power Rails
stripes are added around the stripes over switch cell pins
for each different layer Power rails added 29
Power Planning (Chip level)(Step 5) :
30
Pad pins are connected to rings
End of Floorplanning
31