Modeling of Drain Current, Transconductance and

Flicker Noise in Presence of Doping

Non-Uniformity

A Thesis Submitted
in Partial Fulfillment of the Requirements
for the Degree of

Doctor of Philosophy (Ph.D.)

by

Harshit Agarwal
(12104168)

to the

Department of Electrical Engineering

Indian Institute of Technology Kanpur
March, 2017
i
ii
 SYNOPSIS

Name of the Student: Harshit Agarwal

Roll Number: 12104168
Degree for which Submitted: Ph.D.
Department: Electrical Engineering
Thesis Title: Modeling of Drain Current, Transconductance and Flicker Noise in Presence of
Doping Non-Uniformity
Name of the Thesis Supervisor: Dr. Yogesh Singh Chauhan
Month and Year of the Submission: March, 2017

Compact models are an important part of the Process Design Kit (commonly known as
PDK), which is the interface between circuit designers and foundries. A good compact model
must accurately capture all the real device effects, and at the same time, it should produce them
in a form suitable for maintaining high computational efficiency. BSIM4 is a very celebrated
and popular model among the device and circuit designer community, and is used even for
advanced nodes (e.g. 28 nm). However, analog and RF designers have complained about a
subtle but important issue of asymmetry around Vds = 0V, whose origin lies in several places
such as BSIM’s threshold voltage based core, implementation of bias dependent effects, etc. To
address asymmetry issue and to capture advanced CMOS effects, a new compact MOS model
BSIM6 is developed. BSIM6 was declared industry standard in 2013 after rigorous testing by
the companies under the umbrella of Compact Model Coalition (CMC).
State of the art CMOS process makes use of halo implants. In halo implantation process,
two highly doped pocket regions are created near the source and the drain regions. This lim-
its the extension of the source/drain depletion width into the channel, and increases the gate
control. A good compact model is supposed to capture all the effects of such process enhance-
ments. For e.g., halo implants have significant impact on various aspects of device perfor-
mance, e.g. transconductance (gm ), output conductance, drain induced threshold shift (DITS),
low frequency (1/f) noise, etc. While output conductance degradation and DITS effects are well

iii
 iv

E mobility model disabled in TCAD -20

vertical 10 TCAD Simulation
NMOS
60
-21

/Hz)
10
V = 50mV
A/V)

DS
dotted line: UD
-22
40 10 L=2 m

2
L = 2 m solid lines: Halo

(A
W=1 m
-23
W = 1 m 10

ID
(

S
17
m

-24
N = 5 x10
20 CH 10 TCAD
g

NMOS 17
Halo doping: 8 x10 to Unified Noise Model
-25
18 10
2 x10

-26
0 10
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0

Gate Voltage (V) Gate Voltage (V)

(a) (b)

Figure 1: Impact of doping non-uniformity along the channel (a) Comparison of transconductance of
halo implanted and uniformly doped device. The Halo device exhibits peaky transconductance behavior
even when the mobility degradation models were turned off in TCAD (b) Drain current noise power
spectral density of a gradual channel device. Unified models are based on the assumption of uniform
channel doping and underestimates 1/f noise in weak inversion region.

understood in the literature, the impact on gm and 1/f noise behavior need more understand-
ing. Halo devices carry high on-current as compared to the uniformly doped (UD) devices with
same threshold voltage. Therefore, if one measures gm in the linear region, it comes out that
the peak gm of the halo device is higher than that of the UD. Since gm is an indicator of mo-
bility, this directly leads to the conclusion that carrier mobility in the Halo device is higher as
compared to UD devices. This is against the intuition, since the highly doped pocket regions
should either decrease effective mobility or at best, it should not have any impact because of
their short length. This is indeed true, thanks to mobility extracted from split CV measurements.
Therefore, it is established that gm is no more an indicative of effective mobility in lateral non
uniformly doped devices and this is termed as mobility artefact. Fig. 1(a) illustrates the impact
of halo implants on gm through TCAD simulations. The mobility degradation model is turned
off to elucidate the explicit impact of the doping non-uniformity. It is clearly observed that halo
implants introduce peaking transconductance behavior.
Doping non-uniformity also results in unconventional 1/f noise properties. Low frequency noise
has been critical in sub-micron technology, both for analog and digital designs. Equivalent
 v

threshold voltage variation due to Random Telegraphic Noise exceeds the threshold voltage
variation due to the random dopant fluctuation in 22 nm technology node, posing a real chal-
lenge to device stability. We investigate the two cases of doping non-uniformity: first, where
the entire channel (from source to drain) is non-uniformly doped, and second is the case of Halo
implants. The halo implantation process introduces additional traps in the halo regions, which
are activated only in particular bias conditions and therefore, leads to peculiar bias dependency.
Therefore, the noise models based on uniform channel assumption are not valid. This is illus-
trated in Fig. 1(b), which shows the power spectral density of drain current noise (SID ) of a
MOS with lateral erfc doping profile. It can be observed that the very popular unified model
of 1/f noise cannot model typical noise behavior. The insight gained from the analysis (and
modeling) of the first case is utilized to develop a compact model for the second case.
In this thesis, we also present a compact model of threshold voltage (Vth ) within the frame-
work of charge based model. State of the art modeling approaches (surface potential/charge
based modeling) do not endorse threshold voltage based methodologies and, therefore Vth , is
not explicitly available in such models. It is, however, necessary to know Vth of the transistor,
because circuit designers require it to bias the circuit in appropriate region, e.g. analog designer
uses it to bias the transistor in saturation region and digital designer needs it to determine on
current. We develop an analytical model of threshold voltage, which is based on the condition
of Idrif t = Idif f usion and which can be used for operating point information in SPICE engines.
The proposed model is implemented in the BSIM6 MOS model and is available in the public
domain.
The thesis is organized in the following chapters:
Chapter 1 presents the general background of the thesis. Along with the brief overview
of the CMOS technology development, motivation behind the research work undertaken in this
thesis is also discussed.
Chapter 2 serves two main objectives: first, the model to capture the effect of non-uniform
depletion width along the channel (at non zero drain bias) on drain saturation current is devel-
oped. This model is not yet available in the public domain and is under testing for robustness
before final implementation in BSIM6. Second, it draws equivalence between the core model
of the BSIM4 and BSIM6 models. This is very important, as the users are very familiar with
the BSIM4 model, and this will simplify visualization of the BSIM6 model.
 vi

Chapter 3 has analysis of anomalous transconductance behavior of halo implanted MOS-

FET. We demonstrate that gm exhibits peculiar properties not only in the linear, but also in the
saturation region of operation across both the gate and the body biases. The gm characteristics
undergo sharp change of slope in saturation, which cannot be modeled by conventional com-
pact models. The cause of such behavior is identified and explained using TCAD simulations
of the source side halo, the drain side halo, both side halos and uniformly doped transistors.
It is demonstrated that the commonly used approach, where only the drain side halo region is
considered in saturation, is insufficient to model the typical gm behavior. The effect of oxide
thickness (Tox ) variation on gm is also studied that demonstrates a deviation from conventional
gm behavior for halo implanted devices with thicker Tox . An analytical model to explain the
gm behavior is proposed using the concept of equivalent conductance. The proposed model is
a computationally efficient SPICE model which shows excellent matching with the measured
data.
In Chapter 4, flicker noise behavior of lateral non-uniformly doped MOSFET is investi-
gated. The Klaassen Prins (KP) method, which forms the basis of the noise model in MOS-
FETs, is shown to underestimate flicker noise in such devices. We have modeled the physics
behind such behavior, which also explain the trends observed in the real device measurements.
In Chapter 5, we develop a compact and completely analytical model to capture the uncon-
ventional 1/f noise behavior of the Halo implanted devices. The proposed model is based on the
local trap density, inversion charge densities specific to the region that generates the noise, as
well as the length of the region. The proposed model is the first compact model implementation
capturing such effects and it shows distinct improvements over other existing noise models. The
model is validated with measurements from 45 nm low power CMOS technology node.
In Chapter 6, we present an analytical model of the threshold voltage for bulk MOSFET.
The model is derived from the physical charge based core of BSIM6 MOSFET model, taking
into account short channel effects, and is intended to be used in commercial SPICE simulators
for operating point information. The model is validated with measurement data from IBM’s 90
nm technology node using various popular threshold voltage extraction techniques, and good
agreement is obtained.
Finally, the research work carried in the thesis is summarized in Chapter 7.
 Dedicated to
My parents, for their sacrifice and support...
 Acknowledgement

There are lot of peoples without them it was not possible for this thesis to come up. First of all,
I am very much thankful to my supervisor Dr. Yogesh Singh Chauhan. There are no words to
describe his energy and enthusiasm, and it was my pleasure to work with him. His openness for
discussion at any time of the day made it possible to finish this work in stipulated time.
I am deeply indebted to all my teachers, especially Prof. B. Mazhari, Prof. A. Dutta, Prof. S.
S. K. Iyer, Prof. S. Qureshi and Prof. S. Mishra for forming the basis of this work through their
artistic teachings.
I take this opportunity to thank Dr. Sagnik Dey from Texas Instruments, Dallas, USA for be-
ing the industrial liaison partner. I am deeply fond of his willingness to share his experience
and insight of the semiconductor industry. I am also thankful to Wai-Kit Lee and K. Wu Su
from TSMC, Hsinchu, Taiwan for the internship opportunity, which has certainly helped me in
broadening my horizon. I also want to extend my sincere gratitude to Prof. Chenming Hu from
the University of California Berkeley, USA for various technical discussions.
I am thankful to Mr. Johnson Whiteford for his timely support in providing accessibility to
various tools, and the Nanolab group members for creating and maintaining enthusiastic envi-
ronment of the lab. Thanks to Chetan, Sudip, Girish, Avirup, Ravi, Rajat, and all my friends
who made my stay at IIT Kanpur memorable.
I feel privileged to have wonderful parents, who are the true source of inspiration. Special
thanks to my siblings, Ankuri and Esha, for their unconditional support. I am also thankful to
my beloved wife Pragya for coming into my life, and standing by me in thick and thin moments.
I forever owe utmost gratitude to almighty GOD, whose Divine light and blessings provide me
faith and strength to carry on my work.

viii
List of Abbreviations

Abbreviation Description

CMOS Complementary Metal Oxide Semiconductor

MOSFET Metal Oxide Semiconductor Field Effect Transistor
BSIM Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model
SPICE Simulation Program with Integrated Circuit Emphasis
CF Contribution Factor
PSD Power Spectral Density
SH Source Halo
DH Drain Halo
UD Uniformly Doped
NUDC Non Uniformly Doped Channel
TCAD Technology Computer Aided Design
SHE Self Heating Effect

ix
Contents

Certificate i

SYNOPSIS iii

Acknowledgement viii

List of Abbreviations ix

List of Figures xii

1 Introduction 1
1.1 CMOS Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Industry Relevance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 SPICE Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Thesis Goal and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 BSIM6: Advanced Model for Analog and RF Simulations 14

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 BSIM6 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Pinch-Off Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 The Charge Calculation . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.3 Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Modeling the Impact of Halo Implants . . . . . . . . . . . . . . . . . . . . . . 19
2.4 Improvements in BSIM6 over BSIM4 . . . . . . . . . . . . . . . . . . . . . . 20
2.4.1 Symmetry Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Improved Junction Capacitance Model . . . . . . . . . . . . . . . . . . 21
2.4.3 Self Heating Effect (SHE) . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Other Benchmark Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 Similarities Between BSIM4 and BSIM6, and Modeling Bulk Charge Effect . . 27
2.7 Model Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

x
CONTENTS xi

3 Anomalous Transconductance in Halo Implanted MOSFETs 38

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 TCAD Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3 Impact of Halo Implants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.1 Linear Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.2 Saturation Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3.3 Impact of Oxide Thickness Variation . . . . . . . . . . . . . . . . . . 43
3.4 Halo Implanted Devices: Quantitative Analysis . . . . . . . . . . . . . . . . . 46
3.4.1 Strong Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.2 Weak Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4.3 Total Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.5 Compact Modeling and Validation . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5.1 Impact of Gate Length Scaling and Temperature Variation . . . . . . . 54
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4 Flicker Noise in Presence of Doping Non-Uniformity: Analysis and Modeling 60

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2 TCAD Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3 Modeling 1/f Noise in NUDC Devices . . . . . . . . . . . . . . . . . . . . . . 61
4.3.1 Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.2 The Local Noise Source . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.3 Drain Current Model of NUDC Device . . . . . . . . . . . . . . . . . 63
4.3.4 Proposed Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5 Compact Modeling of Flicker Noise in Halo Implanted Devices 76

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2 Flicker Noise Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.3 Model Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.4 The Noise Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.5 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.5.1 Impact of Halo Region Dose and Length . . . . . . . . . . . . . . . . 86
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6 Compact Modeling of Threshold Voltage of MOSFETs 94

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2 Threshold Voltage Extraction Methods . . . . . . . . . . . . . . . . . . . . . . 95
6.2.1 Extrapolation in Linear Region (ELR) Method . . . . . . . . . . . . . 95
6.2.2 gImd Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2.3 Second Derivative (SD) Method . . . . . . . . . . . . . . . . . . . . . 95
6.2.4 Second Derivative Logarithmic Method . . . . . . . . . . . . . . . . . 96
6.2.5 Constant Current (CC) Method . . . . . . . . . . . . . . . . . . . . . . 96
CONTENTS xii

6.3 Threshold Voltage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.3.1 Long Channel Threshold Voltage . . . . . . . . . . . . . . . . . . . . 96
6.3.2 Short Channel Threshold Voltage . . . . . . . . . . . . . . . . . . . . 99
6.4 Model Validation with Experimental Data . . . . . . . . . . . . . . . . . . . . 100
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7 Conclusions and Scope for Future Work 104

7.1 Scope for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

A BSIM6 Core Model 106

A.1 The Pinch-Off Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
A.2 Normalized Charge Density . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

B List of Publications 115

B.1 Journal Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
B.2 Conference Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
List of Figures

1 Impact of doping non-uniformity along the channel (a) Comparison of transcon-

ductance of halo implanted and uniformly doped device. The Halo device ex-
hibits peaky transconductance behavior even when the mobility degradation
models were turned off in TCAD (b) Drain current noise power spectral density
of a gradual channel device. Unified models are based on the assumption of
uniform channel doping and underestimates 1/f noise in weak inversion region. iv

1.1 Moore’s Law: Feature size decreases by 0.7X [1]. Semiconductor industry
is driven by CMOS scaling for many generations. Number of transistors in a
given area increases by 2X every two years, thereby increasing functionality
and reducing overall cost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Illustration of challenges in device scaling [1]. Scaling is thwarted by several
challenges which require new ideas and techniques to circumvent them. . . . . 2
1.3 Intel CMOS process evolution [2]: Various new ways were investigated and
adopted in commercial processes to continue scaling. . . . . . . . . . . . . . . 3
1.4 Most recent planar CMOS based circuits (a) Power amplifier from Toshiba [25]
(b) Transmitter in TSMC 28nm process [26] (c) Band gap reference in Sam-
sumg 350nm process [27] (d) Delta-Sigma Modulator [29]. . . . . . . . . . . 5

2.1 Compact models are composed of core and real-device models. The core mod-
els must be symmetric and accurate for an ideal long channel device [15]. . . . 15
2.2 BSIM6 core model: BSIM6 is a charge based model where all the terminal
quantities, like charges and currents, are expressed as a function of inversion
charge density at the source and drain ends. . . . . . . . . . . . . . . . . . . . 16
2.3 Gummel Symmetry Test: the IX vs VX =VD -VS when VD = -VS (a) VG =0.25V
(weak inversion) (b) VG =1.2V (strong inversion) (c) AC symmetry plot for gate
capacitance. Model shows excellent symmetry properties for several order of
derivatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4 Junction capacitance model : BSIM4 vs BSIM6. Asymmetry issues around
Vds = 0 can be seen in BSIM4. This is removed in BSIM6, which is now
infinitely differentiable at that point. . . . . . . . . . . . . . . . . . . . . . . . 23

xiii
LIST OF FIGURES xiv

2.5 Illustration of the impact of self heating effect. Semiconductor device properties
are very sensitive to the operating temperature. The power dissipated by the
MOSFET raises the local temperature, which in turn affects various parameters
like threshold voltage, mobility, carrier velocity, etc.. . . . . . . . . . . . . . . 24
2.6 Illustration of self heating effect on drain current. Inset figure is the thermal
network. Self heating effect is observed mainly at high power, causing the
drain current to decrease with the drain voltage. Default parameters are used
for this simulations. Vg : 0V, 1V, 2V. L = W = 1µm. Default BSIM6 model
parameters are used for the simulation. . . . . . . . . . . . . . . . . . . . . . . 24
2.7 Self heating model check: (a) Model prediction of temperature and current vari-
ation, as the thermal resistance is sweeped (b) Comparison of drain current from
two approaches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.8 BSIM6 model behavior check (a) Tree Top Test for BSIM6 with default param-
eters and at different body biases (b) Slope Ratio Test for three different temper-
atures : -25, 50 and 100 o C (c) Tree Top Test for BSIM6 with default parameters
C
and at different body biases (d) Normalized Capacitances ( W LC ox
) : Illustration
of quantum mechanical effect and poly depletion effect on gate capacitance.
QME reduces Cgg above threshold and its effect reduces progressively with
gate bias. PDE affects the slope of Cgg in strong inversion. L = W = 1µm. . . 26
2.9 Saturation characteristics at different VSAT: Drain current vs drain voltage sim-
ulation for L=2mm. For the case of long channel devices where the saturation
voltage is not decided by velocity saturation, VSAT is set to a large value. How-
ever, drain current may become insensitive to VSAT beyond some large value.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.10 Behavior of the proposed model: Drain current vs drain voltage at different val-
ues of the parameter A0. A0 provides additional facility to tune drain saturation
voltage and current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.11 (a) Drain current vs drain voltage (b) gm vs gate voltage of long channel length
device. The proposed model shows improvement in imitating saturation region
characteristics over existing model. . . . . . . . . . . . . . . . . . . . . . . . 32

3.1 Measured correlation between ID,sat with Vth,sat of long channel (a) Halo im-
planted (b) Uniformly doped MOSFET. The long channel halo device shows
low correlation, indicating that different mechanisms are controlling the chan-
nel in weak and strong inversion, which cannot be modeled by conventional
MOS models. Measurement data is from the same process in [7, 8]. . . . . . . 39
3.2 TCAD Setup: (a) N-Channel halo doped MOSFET simulated in TCAD (b) Ex-
ample doping profile along the channel with NCH =5X1017 /cm3 , NH =2X1018 /cm3
and Tox =4nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
LIST OF FIGURES xv

3.3 TCAD simulations of UD, SH, DH and Halo devices in linear region at VDS =
50mV . Channel doping is same in all the devices. Although the threshold
voltage of UD is small as compared to other devices, they all carry nearly same
on-current since effective channel resistance in all the cases is same in strong
inversion. L=2µm, W=1µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.4 TCAD simulations of Halo and UD devices in linear region at VDS = 50mV .
Channel doping is same in all the devices, and L=2µm, W=1µm. (a) Drain cur-
rent (b) gm at different doping conditions. In (b), while the threshold voltage is
different, drain current in SI is same for all the cases, causing gm to peak in the
vicinity of weak-strong inversion transition region. Here, we have intentionally
turned off the mobility degradation model at high field in order to demonstrate
that the gm peak in halo devices is not related to mobility degradation at high
field as in conventional UD. Similar trends are also seen in the real device mea-
surements [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5 Comparison of transconductance of SH, DH, Halo and UD devices in the satu-
ration at VDS = 2V . gm of DH is very different from that of SH and Halo, as it
does not undergo change of slope around threshold voltage. Most of the com-
pact models model the saturation characteristics of halo implanted MOSFET by
two transistor equivalent model [10, 11] (proposed in [3]), one representing the
drain side halo region and other representing channel. By neglecting the source
side halo region, gm characteristics can not be modeled accurately. L=2µm,
W=1µm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6 Dependence of gm on Tox in presence of halo implants: gm − VG at VDS =

50mV for Tox =2nm, 3nm and 4nm. Inset figure plots the ratio of maximum gm
to the gm at 0.5V gate overdrive. As Tox increases, Vth,H increases by greater
amount as compared to Vth,CH since γH > γCH . Therefore ∆Vth and hence
gm ratio increases with the Tox as shown in the inset figure. Here, we have
intentionally turned off the mobility degradation model at high vertical field in
order to demonstrate that the gm peak in halo devices is not related to mobility
degradation at high field as in conventional UD. L=2µm, W=1µm. . . . . . . . 45

3.7 Modeling of halo implanted MOSFET: three transistor based modeling. The
drain and source side halo regions are modeled using highly doped transistors
of length=LH [5]. This sub-circuit is analytically solved to obtain equivalent
conductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIST OF FIGURES xvi

3.8 (a) Equivalent conductance of the halo and channel region as a function of gate
voltage. In weak inversion, GH << GCH because of high threshold voltage
of the halo region. In strong inversion, due to the formation of inversion layer,
GH >> GCH since length of channel region is greater than that of halo region.
Asymptotically, GEQ = GH in weak inversion and GEQ = GCH in strong inver-
sion. (b) Comparison of derivative of gds extracted from TCAD at VDS = 0V
vs gate voltage for UD and Halo devices. Derivative of gds shows qualitatively
same behavior as predicted by model in (a). The switching of conductance gives
rise to peaking gm characteristics in Fig. 3.4(a). (c) First derivative of GEQ at
different doping conditions at VDS = 50mV . The model predicts similar trend
as in Fig. 3.4(b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.9 Modeling of halo implanted MOSFET. The source side halo region is mod-
eled using bias dependent resistor. The impact of drain side halo region on
the threshold voltage and output conductance is analytically modeled in BSIM6
through the DITS model [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.10 NMOS- Model validation with experimental data in linear region at VDS =
50mV : (a) ID − VG (b) gm − VG at different body biases. L=2µm, W=2µm. . 51
3.11 NMOS- Model validation with experimental data in saturation region at VDS =
1.21V : (a) ID − VG (b) gm at different body biases. The proposed model
accurately captures gm behavior across body biases. Compact model ignor-
ing source side halo region electrostatic do not capture typical gm behavior.
L=2µm, W=2µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.12 Impact of body bias: (a) gm − VG of long channel PMOS in linear region for
different VB . Peak of gm initially increases and then decreases with VB . Similar
trends are also seen in TCAD simulation in (b). Inset figure in (b) shows that
threshold voltage difference between the halo region and the channel region has
non-monotonous trend which is responsible for such behavior of max. gm with
VB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.13 PMOS- Model validation with experimental data in saturation region: (a) ID −
VG (b) gm at VB = 0, 0.45V . gm and its derivative are accurately modeled by
the proposed model. L=2µm, W=2µm. . . . . . . . . . . . . . . . . . . . . . 54
3.14 Impact of gate length scaling and temperature variation: Measured ID − VG of
NMOS at VDS =50mV (a) for channel length L = 2µm and L = 120nm. Sub-
threshold characteristics are determined by the halo regions, therefore, scaling
has no impact in weak inversion. (b) Short channel ID − VG at two different
temperatures T=27o C and T=150o C. . . . . . . . . . . . . . . . . . . . . . . . 55
3.15 NMOS- Model validation with experimental data for a short channel device in
linear and saturation region: (a) ID − VG (b) gm − VG . L=120nm, W=1µm. . . 55
3.16 Ratio of equivalent conductance of the channel region to the halo region vs gate
length in strong inversion (obtained using 3.24). For short gate lengths, halo
and channel regions merge and the ratio approaches to unity. . . . . . . . . . . 56
LIST OF FIGURES xvii

3.17 Input referred noise prediction: comparison of old and new model in strong
inversion. The models prediction differs by 10-15%, which can be critical for
the analog designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.1 Doping (NA ) profile along the channel of a NUDC device used in this study.
The experimental doping is extracted from [8]. Doping at the source and the
drain ends are 1018 cm−3 and 1016 cm−3 , respectively. L=2µm, W=1µm. . . . . 61
4.2 Drain current vs gate voltage characteristics for the non uniformly channel
doped device at Vds = 50mV. The charge based model specific to NUDC de-
vices in [8] is used to model the drain current, which shows excellent matching
with the TCAD data. L=2µm, W=1µm. . . . . . . . . . . . . . . . . . . . . . 64
4.3 Equivalent representation of MOSFET for flicker noise modeling. . . . . . . . 65
4.4 Drain current flicker noise power spectral density vs gate voltage at VDS =50mV.
KP method, which treats IF as constant independent of channel position and
bias, underestimates flicker noise, especially in weak inversion region. Nu-
merical method simulation are in agreement with the device simulation data
extracted from Sentaurus TCAD. L=2µm, W=1µm. . . . . . . . . . . . . . . . 67
4.5 Inversion charge density (normalized to inversion charge density at the source)
along the channel for Vg = 0.1V (weak inversion) and 0.6V (strong inversion)
at VDS =50mV. Due to the lateral non uniform doping, inversion charge is a
function of channel position, and increases from source to drain as the doping
on the source side is highest. L=2µm, W=1µm. . . . . . . . . . . . . . . . . . 68
4.6 Impedance field (normalized to L1 ) and PSD of local noise source (normalized to
PSD at the source) vs channel position at VDS = 50mV for (a) VG =0.1V, and
(b) VG =0.6V. Both IF and Sδi2n peaks at the source end, making the effective
contribution of the part of the channel near the source towards overall noise
more prominent than rest of the channel. For high gate voltage as in (b), IF is
not only more uniformly distributed along the channel, but also remains close
to 1 i.e. close to IF for uniformly doped MOSFETs, thereby less discrepancy
between KP and numerical simulation is observed in Fig. 4.4. L=2µm, W=1µm. 69
4.7 Impact of different doping profile on flicker noise: (a) Three different doping
profiles (b) Flicker noise power spectral density at VDS = 50mV for VG swept
from 0V to 1V. To achieve the same current level, device 1 needs minimum gate
voltage as its threshold voltage is minimum. Since source side doping is same
for all, device 1 has minimum inversion charge density at the source end (at
same current level) among the three devices, and hence highest PSD of local
noise source (see 4.12) in weak inversion. In strong inversion, all three devices
have similar inversion charge density due to formation of inversion layer, and
hence the noise characteristics is also relatively same. Note that device with
doping profile 1 depicts significant bias dependency, similar to the noise behav-
ior observed in [30, 31]. Inset figure in (b) plots SID in the saturation region.
L=2µm, W=1µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
LIST OF FIGURES xviii

5.1 Drain current flicker noise power spectral density vs drain current at VDS =
0.55V , both normalized to channel width. Measurements are from the same
technology as in [1] and show complex dependency on gate voltage, especially
for long channel device. In weak inversion, there is no impact of length scaling
on 1/f noise. Dotted lines show unified model [3] result for the long channel
device, and it is clearly seen that it cannot model the noise characteristics of the
Halo devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2 Comparison of SID vs drain current of UD and Halo for different doping con-
ditions at VDS = 2V . In weak inversion, SID of the Halo device is significantly
higher than that of UD. In strong inversion, all have same SID . As doping
of the halo region increases, non-monotonicity is observed. Such behavior is
also observed in the real device measurements [9], and therefore establishes
the qualitative correctness of the TCAD simulation environment. L=2µm and
W=1µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3 Comparison of SID vs drain current of UD, SH, DH and Halo at VDS = 2V .
NCH =5X1017 /cm3 and NH =1.3X1018 /cm3 . Since DH does not depicts uncon-
ventional bias dependency, it can be inferred that drain side halo region has little
impact on overall noise behavior of Halo devices. L=2µm and W=1µm. . . . . 78
5.4 Representation of halo implanted MOSFET for noise modeling: (a) Channel
length L can be divided into two parts- the halo region of length Lh with doping
Nh and the channel region of length L-Lh with doping Nch (b) equivalent cir-
cuit representation. Source side electrostatics is captured by the high threshold
voltage transistor of length L = Lh . . . . . . . . . . . . . . . . . . . . . . . . 80
5.5 Small signal analysis of two transistor noise circuit. Principle of superposition
is used to obtain total noise from individual noise contributions (a) Noisy halo
transistor, noiseless channel transistor (b) Noisy channel transistor, noiseless
halo transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.6 Model validation with experimental data of long channel device: SID vs ID at
VDS = 0.55V. SID asymptotically follows halo transistor noise in weak inver-
sion and channel transistor noise in strong inversion. L=1µm. . . . . . . . . . 84
5.7 Contribution factor of the halo and the channel transistor vs drain current. In
weak inversion, CFh >> CFch , and thus SID is dominated by the noise from
the halo region (see (5.8)). On the other hand, CFh falls rapidly in the strong in-
version leading to the negligible contribution from halo region in SID . The role
of CF in this model is similar to that of impedance field [12], which is responsi-
ble for noise propagation from a point in the channel to the drain terminal. Note
that [7] adds halo and channel contribution with equal weights, therefore will
overestimate noise in strong inversion. . . . . . . . . . . . . . . . . . . . . . . 85
5.8 Model validation with experimental data of a short channel device: SID vs IDS
at VDS = 0.55V. L=1µm and 120nm. . . . . . . . . . . . . . . . . . . . . . . 85
LIST OF FIGURES xix

5.9 SID at same doping conditions but different lengths of halo region. As the
length of the halo region increases, the point where SID makes transition shifts
to higher drain current. This is because resistance of the halo region increases
with LH and it therefore requires higher bias to achieve CFh = CFch . The an-
alytical model (see (5.8)) accounts for LH dependency and therefore accurately
models 1/f noise behavior. VDS =2V. L=2µm and W=1µm. . . . . . . . . . . . 87

5.10 Modeling of SID : SID as obtained from (5.8) with different doping of halo
region. The model shows asymptotically correct behavior since unconventional
bias dependency is not seen for NH = NCH and non-monotonicity is observed
at higher NH . VDS =2V. L=2µm and W=1µm. . . . . . . . . . . . . . . . . . . 87

5.11 Model validation with experimental data at VDS = 50mV [9]. Unlike at long
channel lengths, short channel length device does not show significant bias de-
pendency in SID . Short channel length device behaves similar to uniformly
doped device as the halo regions from both the ends merge together. The com-
pact model is able to accurately model SID in linear region as well, both for
long and short channel length devices. VDS =50mV. . . . . . . . . . . . . . . . 88

5.12 1/f noise model results at short gate length. Gate length=30nm, halo region
length=28nm. For such short lengths, transistor behaves like a uniformly doped
device, but have higher trap density throughout the channel due to the halo
implantation process. The old model also gives similar results but one has to
use higher value of the noise parameters. VDS =50mV. . . . . . . . . . . . . . . 89

5.13 Simulated drain current noise spectral density vs drain current for constant gate
voltage and varying VDS from 0.1V to 1.0V for the long channel device: (a)
VGS = 1.0V (b) VGS = 0.25V . In (a), high gate voltage strongly inverts both
the halo and channel regions. However, resistance of the channel region is
larger as its length is large compared to the halo region, as a result total noise is
dominated by the channel region noise. In (b), halo region offers much higher
resistance than the channel part due to its high threshold voltage and hence the
total noise is determined by the noise of the halo transistor. . . . . . . . . . . . 90

6.1 BSIM6: Solution of the Core Model [15]. Here, we adapt approach Idrif t =
Idif f as it can lead to explicit solution for threshold voltage. . . . . . . . . . . . 97

6.2 Comparison of ψp,th (pinch-off potential at qs =0.5) with numerical solution.

The source voltage is swept from -0.5V to 1V. The error resulting from approx-
imation in (6.16) is less than 1%, leading to compact, yet accurate expression
of pinch-off potential at threshold condition. . . . . . . . . . . . . . . . . . . 99
LIST OF FIGURES 1

6.3 Threshold voltage model validation (a) threshold voltage vs channel length in
linear region at Vds = 50mV and Vb = 0V . Channel length is varied from 2µm
to 70nm. The threshold voltage from the model is in close agreement with the
extraction methods. It is also important to note that the model is able to cap-
ture the threshold voltage roll-up characteristics, typical to the halo implanted
devices. Measured threshold voltage is extracted using CC method, for which
I0 = 350nA is used. Inset figure shows the threshold voltage vs body bias in
linear region at Vds = 50mV for L=2µm (b) Vth vs L in saturation region (c)
Vth vs body bias in linear and saturation region. The model accurately models
threshold voltage across length and drain and body biases. . . . . . . . . . . . 101
Chapter 1

Introduction

1.1 CMOS Scaling

Classical CMOS transistors have been driving the semiconductor industry for more than 4
decades. Large part of such tremendous success is attributed to the scaling abilities, which
makes the device smaller (10µm in 1970 to 20nm in planar and 14nm in non-planar process
in 2016). Shrinking the transistor size enables a chip to accommodate billions of transistors,
thereby increasing functionality at overall reduced cost. The ability to improve performance
consistently while decreasing power consumption has made CMOS architecture the dominant
technology for integrated circuits [3]. Transistor delay times have decreased by more than 30%
for each technology generation, resulting in doubling of microprocessor performance every two
years [4–15], as shown in the Fig. 1.1.
Scaling, in general, has never been straightforward, and it was realized that various physi-
cal limitations will soon end the golden era of CMOS scaling. As the channel length is scaled
down, gate gradually loses its control over the channel to the source and drain. This causes se-
vere “short channel effects (SCE)”, primarily manifested as threshold voltage (Vth ) roll-off (with
channel length) and drain induced barrier lowering (Vth reduction at high drain bias). Poor gate
control also leads to degraded sub-threshold slope and increased off state current. Moreover,
oxide thickness cannot be scaled indefinitely since thin oxide assist in quantum mechanical tun-
nelling, thereby further increasing off-current. Some of these challenges are highlighted in the
Fig. 1.2. In order to maintain rapid performance improvements and circumvent SCE, several

1
1.1 CMOS Scaling 2

Figure 1.1: Moore’s Law: Feature size decreases by 0.7X [1]. Semiconductor industry is driven by
CMOS scaling for many generations. Number of transistors in a given area increases by 2X every two
years, thereby increasing functionality and reducing overall cost.

Figure 1.2: Illustration of challenges in device scaling [1]. Scaling is thwarted by several challenges
which require new ideas and techniques to circumvent them.
1.2 Industry Relevance 3

Figure 1.3: Intel CMOS process evolution [2]: Various new ways were investigated and adopted in
commercial processes to continue scaling.

new ways were investigated, for e.g., retrograde (and inverse retrograde) doping, halo/pocket
implants [16, 17], increasing mobility through strain [8], high-K metal gate in place of conven-
tional SiO2 [10], etc. to name a few. Fig. 1.3 shows the process advancement in production
level devices from Intel.
However, in spite of all such efforts, planar bulk device was able to scale only till 20nm
gate pitch [18]. Beyond that, in a first of its kind move, Intel moved from planar bulk device
to non-planar tri-gate FinFET in 2012 when they announced 22nm FinFET process [14]. Other
major fab houses like TSMC (16 nm FinFET [19] and FinFET Plus process [20]) and Samsung
[21] also shifted to FinFET. Apple A9 chips are fabricated by TSMC and Samsung in 16nm
and 14nm technology node, respectively. At this point of writing, Apple has announced latest
iPhone 7, which houses more powerful A10 chips.

1.2 Industry Relevance

Although FinFET has replaced planar bulk devices for the logic applications, they, however,
face major challenge from them for analog applications. Analog designers prefer to have various
1.3 SPICE Modeling 4

knobs to achieve target specifications, and channel width is one of the important one. In FinFET,
this freedom is virtually lost because of fixed fin width [22]. The current strength is enhanced
by using multiple fins, and this leads to fin quantization [23]. This also have adverse effect on
SRAM designs, since optimizing the β ratio of a bit-cell becomes more difficult [24]. Although
FinFETs are slowly gaining momentum for the analog circuits as well, owing to their excellent
immunity against SCE, nearly ideal sub-threshold slope, lower output conductance and high
gain, nevertheless, planar device is expected to dominate this area in near future. This includes
analog switches, precision operation amplifiers, switch capacitor circuits, gain stages, filters,
sampled data circuits, power management integrated circuits (PMIC) and many more [25–29].
Fig. 1.4 shows some of the recently reported designs in planar processes.
Many analog circuits are sensitive to noise and mismatch. Mismatch consideration limits the
minimum gate area since it increases with √ 1 [30–33]. Therefore, transistor in these analog
W ∗L

circuits (e.g. current mirrors [34], current steering DAC [35]) typically have a large area, from
tens to thousands of square microns [36]. Long gate length devices further help in not only
reducing 1/f noise, but it also eliminates any random noise event due to discrete number of
traps in the short length devices [33]. Therefore, they are very commonly used as an input
stage amplifier. Furthermore, since the analog blocks are monolithically integrated with the
mainstream logic devices with shorter gate lengths, it becomes very important to accurately
model both the long and short length devices simultaneously.

1.3 SPICE Modeling

A compact model is needed to simulate devices and circuits before the real fabrication. For ana-
log applications, model must accurately capture all the real device effects, and should emulate
device characteristics over a wide range of operating conditions of biases, geometry and fre-
quencies. The key figure of merit for analog devices includes transconductance (gm ), transcon-
gm
ductance to current ratio (gm /ID ), output conductance (gds ), gain (≈ gds
), noise figure, etc [37].
The performance boosting techniques previously discussed (Fig. 1.3 and subsequent discussion)
have strong impact on these figure of merits. For e.g., in sub-micron devices, non-uniform dop-
1.3 SPICE Modeling 5

(a) (b)

(c) (d)

Figure 1.4: Most recent planar CMOS based circuits (a) Power amplifier from Toshiba [25] (b) Transmit-
ter in TSMC 28nm process [26] (c) Band gap reference in Samsumg 350nm process [27] (d) Delta-Sigma
Modulator [29].

ing (intentional as well as unintentional) is commonly seen in pocket implanted devices [38],
LDMOS transistor [39, 40], and even in the vertical nanowire transistors [41]. In the presence of
doping non-uniformity, threshold voltage becomes a function of channel position and has qual-
itative and quantitative impact on various aspects of the device performance. For e.g., transcon-
ductance (gm ) characteristics are significantly different in halo implanted devices as compared
to uniformly doped devices [42, 43]. In the linear region of operation, even though gm char-
acteristics is not visually distinguishable from that of uniformly doped devices, but it carries a
signature effect which is popularly known as mobility artefact [44, 45]. Furthermore, devices
with halo implants depict very significant bias dependency in 1/f noise characteristics [46, 47].
1.4 Thesis Goal and Organization 6

Most of the industrial compact models are either based on the assumption of uniformly doped
channel, or neglect the contibution of source side halo region [48–51] and, therefore, cannot
imitate atypical behavior of the nano scaled devices.

1.4 Thesis Goal and Organization

In this thesis, we attempt to investigate and model the impact of non-uniform doping on MOS
transistor performance. We demonstrate that device characteristics are strong function of the
channel doping profile, and conventional modeling approaches are not sufficient to capture the
overall device behavior. The proposed models are developed within the framework of industry
standard BSIM6 MOS model, and are either already available in public domain, or are under
testing by the companies under the aegis of Compact Model Coalition (CMC) and Semiconduc-
tor Research Corporation (SRC). The thesis is organized as follows:
Chapter 2 discusses two topics: first, a model to capture the effect of non-uniform depletion
width along the channel (at non zero drain bias) on drain saturation current is developed. This
model is not yet available in public domain and is under testing for robustness before final
implementation in BSIM6. Second, it draws equivalence between the core model of the BSIM4
and BSIM6 models. This is very important, as the users are very familiar with the BSIM4
model, and this will simplify visualization of the BSIM6 model.
Chapter 3 reports analysis of anomalous transconductance behavior of halo implanted
MOSFET. We demonstrate that gm exhibits peculiar properties not only in the linear, but also
in the saturation region of operation across both the gate and the body biases. The gm charac-
teristics undergo sharp change of slope in saturation, which cannot be modeled by conventional
compact models. The cause of such behavior is identified and explained using TCAD simula-
tions of the source side halo, the drain side halo, both side halos and uniformly doped transistors.
It is demonstrated that the commonly used approach, where only the drain side halo region is
considered in saturation, is insufficient to model the typical gm behavior. The effect of oxide
thickness (Tox ) variation on gm is also studied that demonstrates a deviation from conventional
gm behavior for halo implanted devices with thicker Tox . An analytical model to explain the
1.4 Thesis Goal and Organization 7

gm behavior is proposed using the concept of equivalent conductance. The proposed model is
a computationally efficient SPICE model which shows excellent matching with the measured
data.
In Chapter 4, flicker noise behavior of lateral non-uniformly doped MOSFET is investi-
gated. The Klaassen Prins (KP) method, which forms the basis of the noise model in MOS-
FETs, is shown to underestimate flicker noise in such devices. We have modeled the physics
behind such behavior, which also explain the trends observed in the real device measurements.
In Chapter 5, we develop a compact and completely analytical model to capture the uncon-
ventional 1/f noise behavior of the Halo implanted devices. The proposed model is based on the
local trap density, inversion charge densities specific to the region that generates the noise, as
well as the length of the region. The proposed model is the first compact model implementation
capturing such effects and it shows distinct improvements over other existing noise models. The
model is validated with measurements from 45nm low power CMOS technology node.
In Chapter 6, we present an analytical model of the threshold voltage for bulk MOSFET.
The model is derived using the physical charge based core of BSIM6 MOSFET model, taking
into account short channel effects, and this modelis intended to be used in commercial SPICE
simulators for operating point information. The model is validated with measurement data from
IBM’s 90nm technology node using various popular threshold voltage extraction techniques,
and good agreement is obtained.
Finally, the research work presented in this thesis is summarized in Chapter 7.
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Chapter 2

BSIM6: Advanced Model for Analog and

RF Simulations

2.1 Introduction
Compact models are an important part of the Process Design Kit (commonly known as PDK),
which is the interface between circuit designers and foundries. A good compact model has to
accurately capture all the real device effects, and at the same time it should produce them in a
form suitable for maintaining high computational efficiency. Inaccurate but fast, or accurate but
slow models are not acceptable in the industries and a proper balance between the two is a must
have feature of a good model.
BSIM3 was selected as the industry-standard bulk MOSFET model in 1996 followed by
BSIM4 release in 2000 [1]. These models excelled in accuracy through many generations of
technology from 350nm to 20nm [2]. While BSIM3 and BSIM4 are the threshold voltage based
models, there also exist different class of models based on surface potential [3, 4] and charge
based [5] approach.
A compact model is made of a core model, which describes the behavior of an ideal simple
long-channel MOSFET, and may represent about 20% of the model code, both in terms of exe-
cution time as well as number of lines in the code. The other 80% of the model code comprises
multiple models that describe the numerous “real device effects”, which are responsible for the
accuracy of a compact model. Without them, the inaccuracy could be huge, depending on the
device size [6]. Overview of a compact model is illustrated in Fig. 2.1. BSIM introduced orig-
inal models for various device phenomena, such as short channel effects, output conductance,
quantum mechanical effects, non-uniform doping effects, gate leakage current, band-to-band
tunneling, unified flicker noise, intrinsic input resistance, strain effect, etc. [7–13]. Because of
the amount of flexibility and accuracy, along with high simulation speed offered by the BSIM

14
2.1 Introduction 15

Figure 2.1: Compact models are composed of core and real-device models. The core models must be
symmetric and accurate for an ideal long channel device [15].

models, they have been adopted by most of the IC companies worldwide. However, analog
and RF designers have complained about a subtle but important issue of asymmetry around
Vds = 0 [14], whose origin lies at several places such as BSIM’s threshold voltage-based core,
implementation of the bias dependent terms, etc. [6]. At the same time, users are so familiar
with and fond of the real-device effects model of BSIM, that they want that part intact as much
as possible. To address this problem, the BSIM group started BSIM6 development in late 2010
with a goal to introduce a new core model which solves the asymmetry issue, while maintaining
BSIM4’s accuracy, speed and above all, excellent user experience.
BSIM6 has been declared industry standard by Compact Model Coalition (formerly Com-
pact Model Council) [16]. It builds upon a physical charged based core, derived from the Pois-
son’s solution for long channel MOSFET. The real device effects are modeled similar to BSIM4
with same parameter names, thus allowing smooth transition from BSIM4 to BSIM6. Although
most of the real device models are inherited from BSIM4, however it has been ensured that it
remains symmetric around Vds = 0, thus paving way for the RF implementation.
BSIM4 is a very popular model which has enjoyed industrial preference for more than a
decade. As a result, people are very familiar with its threshold voltage based core model.
However, IC companies are gradually shifting from BSIM4 to BSIM6, owing to its better high
frequency modeling abilities. In this chapter, we will briefly discuss the BSIM6 core model and
draw equivalence between BSIM4 and BSIM6 core models to establish a connection between
the two models. This will also acquaint the reader with the basic terminology of the BSIM6
2.2 BSIM6 Model 16

Solve for
φb Pinch-off vg , vf b
Potential ψp

Solve for
vs vd
qs and qd

Determine
Drain
Current IDS

Figure 2.2: BSIM6 core model: BSIM6 is a charge based model where all the terminal quantities, like
charges and currents, are expressed as a function of inversion charge density at the source and drain ends.

model, which will be helpful in following the subsequent chapters.

2.2 BSIM6 Model

BSIM6 builds upon a physical charge based core. All the currents and charges are expressed
in terms of normalized inversion charge densities at the source and drain ends of the device.
The normalization factor for various quantities is shown in the Table 2.1. Fig. 2.2 illustrates the
core model of BSIM6 [17]. There are two important equations on which BSIM6 core model
is based upon: first one relating pinch-off potential with the gate voltage and the other which
relates the inversion charge density with the pinch-off potential. We will briefly look at these
two fundamental quantities.

2.2.1 Pinch-Off Potential

Under charge sheet approximation, inversion charge density in MOSFET can be written as [18]

0
p
Qi = −Cox (VG − VF B − ψS − γ ψS ) (2.1)

where Cox is the oxide capacitance per unit area, VG , VF B and ψS represents gate voltage, flat
band voltage and surface potential, respectively. γ ‘ is the body factor. For a given gate voltage,
2.2 BSIM6 Model 17

Table 2.1: Description of Normalization Process

Quantity Normalization Factor Normalized Quantity

CGG COX = Cox W L cgg = CGG /COX

IDS Ispec = 2nq βVt2 ids = IDS /Ispec
QI Qspec = −2nq .Cox W LVt qI = QI /Qspec
Gm Gspec = Ispec /Vt gm = G√ m /Gspec
0
γ γ = γ 0 / Vt
All Voltages, V v = VVt

where:
Cox the oxide capacitance per unit area,
β = µCox W/L the transfer parameter,
µ the mobility of the carriers,
Vt = kT /q the thermodynamic voltage

if surface potential is increased (say, by increasing the drain voltage), inversion charge density
reduces. For some value of surface potential, it will become zero. This value of the surface
potential is called pinch-off potential [5]. At pinch off, ψS = ψP and Qi = 0. It can be shown
that the above equation takes the following normalized form (see Table 2.1 for the normalization
factor) [1],
q
vg − vf b = ψp + γ · e−ψp + ψp − 1 (2.2)

This is an implicit equation which is analytically solved in the BSIM6 model. The details of the
solution is given in the Appendix. The final expression of the pinch-off potential reads as,
 2
√
q
−ψ γ 2 γ


1 + e vg − vf b − 1 + e−ψp0 + − if φb + γ φb ≥ vg − vf b ≥ 0

 p0
2 2
ψp =   2 
vg −vf b −ψp0
− ln 1 − ψp0 + if vg − vf b < 0


γ

(2.3)

here φb represents the normalized bulk potential.

2.2 BSIM6 Model 18

2.2.2 The Charge Calculation

It can be shown that normalized inversion charge density can be expressed in terms of ψp as
follows [5],
 
2nq 2nq p
ln (qi ) + ln (qi + 2 ψp − 2qi ) + 2qi = ψp − 2φb − vch (2.4)
γ γ

ln (qi ) + 2qi = vp − vch (2.5)

where nq is the slope factor and, vch is the normalized channel potential potential. Once ψp is
known from (2.3), it is used to obtain inversion charge by solving (2.4). This is again an implicit
equation which can not be directly solved for qi . In BSIM6, analytical method is employed to
solve this equation which is elaborated in the Appendix.

2.2.3 Drain Current

The drain to source current under drift-diffusion formalism is expressed as,

IDS =Idrif t + Idif f (2.6)

dψs dQi
IDS = − W.Qi · µ + W · µ · Vt (2.7)
dx dx
here µ represents the effective mobility and W is the channel width. Ignoring the velocity
saturation effect, drain current for the ideal long channel MOSFET comes out to be [1],

W 1
IDS = 2.nq .µ Cox Vt2 · (qs − qd )(qs + qd + 1) (2.8)
L 2

qs and qd in the above equation are the normalized charge density at the source and the drain
ends obtained by substituting vch = vs and vch = vd in (2.4), respectively. The drain current
model in (2.8) does not include any of the short channel effects. Short channel effects are
accounted for by appropriately shifting threshold voltage, similar to BSIM4. Since threshold
voltage is not available in BSIM6 [19], these shifts are incorporated by defining effective gate
voltage [1]

vgf b = vg − vf b − Vth,shif t (2.9)

2.3 Modeling the Impact of Halo Implants 19

(2.3), (2.4) and (2.8) forms the core of the BSIM6 model, as far as transport is concerned. We
will not discuss capacitance model in this work, whose details can be found in [1].

2.3 Modeling the Impact of Halo Implants

Halo implants are known to affect various aspects of the device, e.g., Drain Induced Threshold
Shift (DITS) [20], Rout degradation [7], Reverse Short Channel Effects (RSCE) [21]. We will
briefly see how these effects are modeled in standard BSIM6 model. In halo implanted devices,
it is commonly seen that the threshold voltage is a function of drain bias even for the long
channel devices. This effect is popularly called as DITS. BSIM6 and BSIM4 have similar DITS
model which is given as [7, 9],
 
KT L
∆Vth,DIT S =− · ln (2.10)
q L + DV T P 0 · (1 + exp(−DV T P 1 · Vds )
 
DV T P 2
− DV T P 5 + DV T P 3 · tanh (DV T P 4 · Vds ) (2.11)
L
(2.12)

where ∆Vth,DIT S represents the threshold voltage shift, which is added to the effective gate
voltage in the core model. DVTP0, DVTP1, DVTP2, DVTP3, DVTP4, DVTP5 are the model
parameters. In halo implanted devices, threshold voltage increases as the gate length is scaled
down as the average doping in the channel increases (RSCE). In BSIM6, the effective doping
of the channel region is a function of gate length as shows below [1]

" #
1 1
N DEP [L] = N DEP · 1 + N DEP L1 · + N DEP L2 ·
LN DEP LEXP 1 LN DEP LEXP 2
(2.13)

where NDEPL1, NDEPL2, NDEPLEXP1 and NDEPLEXP2 are the parameters to accurately
capture length dependence of NDEP. This model has been able to capture threshold voltage
behavior for different lengths [19]. Another important effect observed in the Halo implanted
devices is the output conductance degradation. The major cause of this is identified as the
lowering of the drain side barrier with the drain bias [7]. It was also demonstrated that the
barrier lowering is a function of relative doping of the halo and channel region, as well as the
2.4 Improvements in BSIM6 over BSIM4 20

length of the each region [20]. In BSIM6 model, it is modeled as

1
VADIT S = · F · [1 + (1 + P DIT SL · Lef f ) exp(P DIT SD · Vds )] (2.14)
P DIT S √
 
Vds − Vdsef f 1 F P ROU T. L
MDIT S = 1+ ; =1+ (2.15)
VADIT S F qia + 2Vt
IDS = IDS ∗ MDIT S (2.16)

where VADIT S represents early voltage due to DITS effect, and, PDITS, PDITSL, PDITSD,
FPROUT are the model parameters. Vt and qia are the thermal voltage and normalized average
inversion charge density. In addition, there were reports which highlight other physical phe-
nomenons that can affect the transistor behavior, for e.g. dependence of drain saturation voltage
on halo region properties [22], 1/f noise degradation [23, 24], thermal noise properties [25], mo-
bility artifact [26, 27], impact on current and transconductance [28]. The models for DITS and
output conductance degradation shown above may not be sufficient to capture all these effects
as we will see in the subsequent chapters.

2.4 Improvements in BSIM6 over BSIM4

The main objective of the BSIM6 MOS model development is to overcome asymmetry issue in
BSIM4. Apart from that, there are several other improvements /enhancements in BSIM6 over
BSIM4. We will discuss some of them in the following section.

2.4.1 Symmetry Properties

Bulk MOSFET behaves identical if the source and drain terminals are interchanged, i.e., source
and drain terminals are indistinguishable and it is the external voltage which determines the
terminal name. Compact model sometimes becomes too complicated that they do not reflect
this symmetry property. One of the major reasons for asymmetry in higher order derivatives
in BSIM4 is due to the interpolation function used for Vds to Vdssat (drain-source saturation
voltage) transition [6]. In BSIM6, it is changed as follows, which is the best known method for
smooth transition from Vds to Vdssat [6, 29],

Vds
Vdsef f =   1
 DELTA DELTA (2.17)
Vds
1+ Vdssat

where DELTA is a model parameter. The good thing about this function is that not only it pro-
2.4 Improvements in BSIM6 over BSIM4 21

vides symmetry around Vds = 0, but also makes sure that Vdsef f is exactly zero in implementation
when Vds = 0 without getting affected by accuracy of simulation, precision of compiler, and so
on. In order to validate symmetry of the BSIM6 model, well-known DC Gummel symmetry
test [30] is performed, both in weak and strong inversion region in Fig. 2.3(a) and Fig. 2.3(b).
It can be observed that the derivatives are continuous around Vds = 0, showing the symmetric
nature of the model. The order of derivatives over which this continuity prevails depends on
the parameter DELTA used in (2.17), whose proper choice allows to achieve desired degree of
continuity. The maximum value of DELTA has been limited to 1/2 to ensure that third derivative
is always continuous in the BSIM6 model. Symmetry of the charge model is verified by AC
symmetry test in Fig. 2.3(c), which shows the test results for the gate capacitance, where it can
be seen that capacitance δCg is an odd function of voltage VX and derivative is continuous at
Vds = 0.

2.4.2 Improved Junction Capacitance Model

The diode junction capacitance model of BSIM4 shows asymmetry in second derivative (around
Vbs = 0) and therefore had issues with the AC symmetry test [6]. In BSIM6, the model is
updated so that it is infinitely differentiable and symmetric around Vds = 0. The drain-to-body
(D/B) junction capacitance is modeled as [1, 31],

Cbd = Adrain .Cjbd + Pdrain .Cjbdsw + Wcj · N F · Cjbdswg

where Cjbd is

Vbd −M JD Vbd
CJD(1 −
 ) if ≤ x0
P BD P BD
Cjbd = (2.18)
 Vbd

−1 Vbd
 (1−xCJD

0)
M JD 1 + M JD 1 + P BD
1−x0
if P BD
> x0

here Cjbd is the unit area bottom D/B junction capacitance, Cjbdsw and Cjbdswg are the unit
length D/B junction sidewall capacitance along the isolation edge and gate edge, respectively.
The parameter CJD corresponds to unit-area bottom junction capacitance at zero bias, PBD
is the corresponding built-in potential, MJD is the grading coefficient and x0 is 0.9. BSIM4
junction capacitance model is the special case of this BSIM6 model, with the later reducing to
former for x0 = 0. The sidewall junction capacitance along isolation edge, Cjbdsw and along
the gate edge, Cjbdswg , are also calculated using similar expressions.
Fig. 2.4 shows the junction capacitance derivative comparison between BSIM4 and BSIM6
[17]. The third derivative of charge (second derivative of the capacitance) will produce a kink
2.4 Improvements in BSIM6 over BSIM4 22

4
1.0 1.0

X
1.0

, d I /dV
4

X
Weak Inversion Strong Inversion
1.002

, d I /dV
2

X
I , dI /dV , d I /dV

X
0.5 0.5

4
0.5

dI /dV
dI /dV

X
X X

4
X

X
X
, d I /dV
2

0.0 0.0

3
0.0

X
I

X
d I /dV
X

3
dI /dV X 0.996
X X

-0.5 -0.5
2 2

X
2
d I /dV
2
-0.5 d I /dV

2
X X
X

X
X X

3
3 3 3 3

I , d I /dV
d I /dV d I /dV
X X X X

4 4 4 4
d I /dV d I /dV
-1.0 -1.0

X
X

-1.0
X X X X

2
-0.30 -0.15 0.00 0.15 0.30 -0.30 -0.15 0.00 0.15 0.30
V (V) V (V)

X
X X

(a) (b)

-0.4
0.2

-0.6
d C /dV
Cg

0.0
g

-0.8
x

-0.2
-1.0
-0.4 -0.2 0.0 0.2 0.4

Vx
(c)

Figure 2.3: Gummel Symmetry Test: the IX vs VX =VD -VS when VD = -VS (a) VG =0.25V (weak inver-
sion) (b) VG =1.2V (strong inversion) (c) AC symmetry plot for gate capacitance. Model shows excellent
symmetry properties for several order of derivatives.
2.4 Improvements in BSIM6 over BSIM4 23

-1
10
BSIM6

BSIM4
2

j
d Q /dV

-2
10
j
2

-3
10

-0.5 0.0 0.5 1.0 1.5

V (V)
j

Figure 2.4: Junction capacitance model : BSIM4 vs BSIM6. Asymmetry issues around Vds = 0 can be
seen in BSIM4. This is removed in BSIM6, which is now infinitely differentiable at that point.

around Vj = 0 for BSIM4. However in BSIM6, this point has been shifted away from Vj = 0
(to large Vj ), so that the derivatives remains continuous for all practical applications.

2.4.3 Self Heating Effect (SHE)

Semiconductor device properties are very sensitive to operating temperature. As the device
dissipates power, device operating temperature changes (due to fluctuation in instantaneous
temperature) and affects various parameters like mobility, band gap, etc., which finally propa-
gates to the terminal current. This is illustrated in Fig. 2.5. For devices with very high power
dissipation, SHE can have significant impact on overall performance. BSIM6 models SHE by
employing a thermal network, consisting of the thermal resistance (Rth ) and capacitance (Cth ),
and driving it by current equal in magnitude to total power dissipation of the device [32], as
shown in the inset of Fig. 2.6. The voltage at thermal node T gives the rise in temperature,
which is then added with the effective temperature of the device. In this model, Rth is a model
parameter which can be extracted from gds [33–35]. Fig. 2.6 also shows the effect of self heat-
ing on ID − VD characteristics, where the decrease in the drain current is observed as VD is
increased [17] (this leads to negative gds , which is a signature of SHE). In current version of
the BSIM6 model, Rth in not a function of channel length, although, in our recent study, we
have developed a compact model to account for both the channel length and width dependence
2.4 Improvements in BSIM6 over BSIM4 24

Figure 2.5: Illustration of the impact of self heating effect. Semiconductor device properties are very sen-
sitive to the operating temperature. The power dissipated by the MOSFET raises the local temperature,
which in turn affects various parameters like threshold voltage, mobility, carrier velocity, etc..

4
Drain Current (mA)

C
th
I V

3
D D

R
th

Without Self Heating

2 With Self Heating

0
0 1 2 3 4 5
Drain Voltage (V)

Figure 2.6: Illustration of self heating effect on drain current. Inset figure is the thermal network. Self
heating effect is observed mainly at high power, causing the drain current to decrease with the drain
voltage. Default parameters are used for this simulations. Vg : 0V, 1V, 2V. L = W = 1µm. Default
BSIM6 model parameters are used for the simulation.

in Rth for the fully depleted devices [36].

For testing the self heating model [37], NMOS is biased in strong inversion region and Rth
is swept. The device temperature prediction by the self heating model and the drain current
are observed. Fig. 2.7(a) shows the effect of Rth on temperature and current. It is observed
that temperature increases as the thermal resistance is increased, and correspondingly the drain
2.5 Other Benchmark Tests 25

(a) (b)

Figure 2.7: Self heating model check: (a) Model prediction of temperature and current variation, as the
thermal resistance is sweeped (b) Comparison of drain current from two approaches.

current falls. It is to be noted that the temperature in this figure is the total temperature of the
device including the effect of self heating. Now the self heating mode is switched off, and
device is simulated for temperature range obtained from self heating effect. Fig. 2.7(b) shows
the drain current obtained from these two approaches, and it can be seen that both the curves
overlap each other, establishing the correctness of the model.

2.5 Other Benchmark Tests

Tree-Top Test [37]: Most of the designers use gm /ID methodology for analog design, and
therefore it is important to check its smooth transition from weak to strong inversion region. The
tree-top test checks the physical correctness of modeling the gm /ID ratio. Fig. 2.8(a) shows the
gm /ID variation with the gate bias for different body voltages, where the smooth dependence
on bias is observed. Slope Ratio Test [37]: Fig. 2.8(b) shows the temperature invariant slope
ratio test result, carried for three different temperatures: 100o C, 50o C and -25o C. The slope
ratio (SR ) is defined as

(ID1 + ID2 ) · (Vdb2 − Vdb1 )

SR = (2.19)
(ID2 − ID1 ) · (Vdb2 + Vdb1 )

where ID1 and ID2 are the drain current at drain voltages Vdb1 and Vdb2 , respectively. For tem-
2.5 Other Benchmark Tests 26

20 1.3

R
0

15

Slope Ratio, S
100 C
V =-1V
bs 0
50 C
V
bs
=-0.6V 1.2 0
)

-25 C
-1

V =-0.2V

10
bs
(V

V =0.2V
bs
d

1.1
g /I

5
m

0 1.0

0 1 2 3 0.0 0.2 0.4 0.6 0.8 1.0 1.2

V (V) V (V)
GB GB

(a) (b)

-100
Pout

-200

fundamental
nd
2 harmonic

-300 3
rd
harmonic
th
4 harmonic
th
5 harmonic

-60 -40 -20 0

P
in

(c) (d)

Figure 2.8: BSIM6 model behavior check (a) Tree Top Test for BSIM6 with default parameters and at
different body biases (b) Slope Ratio Test for three different temperatures : -25, 50 and 100 o C (c) Tree
Top Test for BSIM6 with default parameters and at different body biases (d) Normalized Capacitances
C
( W LCox
) : Illustration of quantum mechanical effect and poly depletion effect on gate capacitance. QME
reduces Cgg above threshold and its effect reduces progressively with gate bias. PDE affects the slope of
Cgg in strong inversion. L = W = 1µm.
2.6 Similarities Between BSIM4 and BSIM6, and Modeling Bulk Charge Effect 27

perature independent SR , the drain voltages are chosen such that

Vt 0 Vt 0
Vdb1 = − V and Vdb2 = +V (2.20)
2 2

0
with V << Vt . Theoretically, SR should monotonically reduce from about 1.3 to 1 going
from weak to strong inversion, which is true as seen in Fig. 2.8(b). Harmonic Balance Test:
Symmetry and continuity of higher order derivatives can also be confirmed from single tone
harmonic balance test. In this test, the harmonic content of the drain current as a function of the
amplitude of the single tone excitation is plotted. The slope of the nth harmonic should be n
times the slope of the fundamental frequency. BSIM6 predicts the correct slope of harmonics,
as seen in Fig. 2.8(c) (shown up to the 5th order here) [6].
Fig. 2.8(d) shows the capacitances normalized to W LCox for a long channel n-MOSFET,
where impact of poly depletion (PD) effect and Quantum Mechanical Effects (QME) are demon-
strated separately, as well as combined effect on the gate capacitance [6]. Both PD and QME
affect the capacitance behavior in strong inversion region, while the effect of QME vanishes at
higher gate biases.

2.6 Similarities Between BSIM4 and BSIM6, and Modeling

Bulk Charge Effect

If one looks at the final drain current expression in BSIM4 (or threshold voltage based models
in general) and BSIM6 models, they appear very different from each other. Here we will see
that in alternative representations, it is possible to express BSIM6 model in terms of BSIM4.
During this exercise, we will highlight an important and subtle difference of bulk charge effect
model between the two models.
In threshold voltage based model, inversion charge density at the source and the drain ends
in strong inversion is expressed as [38]

Qs = Cox (Vgs − Vth ) (2.21)

Qd = Cox (Vgs − Vth − mVds ) = Qs − mVds .Cox (2.22)
2.6 Similarities Between BSIM4 and BSIM6, and Modeling Bulk Charge Effect 28

This gives,
!
1 Vds
Qs + Qd = Cox (Vgs − Vth − m ) and Qs − Qd = mVds Cox (2.23)
2 2

C
where Vth represents the threshold voltage. m = 1 + Cdepox
[39], and it accounts for the threshold
voltage variation due to non uniform depletion width from source to drain at non-zero Vds . It is
simple to show that the drain current in linear region can be expressed as [18]

W Vds
IDS = µ · Cox · (VGS − Vth − m )Vds (2.24)
L 2
W Qs Vds
= µ · Cox · ( −m )Vds (2.25)
L Cox 2

Now consider the BSIM6 drain current under strong inversion and small drain voltage con-
dition. In strong inversion, log term in (2.5) can be neglected. This gives 2qi ≈ vp − vch . From
(2.8),

W
IDS = 2.nq .µ Cox Vt2 · (qs − qd )(qs + qd + 1) (2.26)
L
W vds vds
= 2.nq .µ Cox Vt2 (1 + 2qs − ) (2.27)
L 2 2
W Qs Vds
≈µ· · Cox Vds ( − nq . ) (2.28)
L Cox 2

Now consider the model behavior in the saturation region. Drain current in case of BSIM4 can
be expressed as [39]

W VGS − Vth
IDS = µ · Cox · (VGS − Vth )2 , Vd,sat = (2.29)
2·m·L m
!2
W QS
= µ · Cox · · (2.30)
2 · m · L Cox

here Vd,sat represents the drain saturation voltage. In BSIM6, the saturation region model can
be arrived at by letting qd = 0 in (2.8).

W
IDS = 2nq · µ · · Cox · Vt2 qs (1 + qs ) (2.31)
L
W
≈ 2nq · µ · · Cox · Vt2 qs2 (2.32)
L
2.7 Model Implementation 29

W Qs
IDS = 2nq · µ · · Cox · Vt2 ( )2 (2.33)
L −2nq Cox Vt
!2
W QS
= µ · Cox · · (2.34)
2 · nq · L Cox

Comparing (2.25) with (2.28) and (2.30) with (2.34), one can easily notice the similarities
between the two models. The role of m in BSIM4 is played by nq in BSIM6. There is, however,
C
an important difference as well. Although m = 1 + Cdep ox
in principle, but it is modeled as
following for improving the flexibility in tuning drain saturation voltage and current at long
channel lengths [9],
" !2 !#
A0 · L L 1
m = 1 + Fdoping p 1 − AGS · VGSt,ef f p ·
L + 2 Xj .Xdep L + 2 Xj .Xdep KET A · VBS
(2.35)

However, in the BSIM6 model, nq actually corresponds to sub-threshold slope, and is extracted
in weak inversion. It can not be tuned for saturation region characteristics. Since drain satura-
tion current has strong dependence on m and nq (see (2.30) and (2.34)), therefore users has one
knob less to tune long channel drain saturation current and voltage in the BSIM6. BSIM4 beau-
tifully decouples it from the sub-threshold slope, thanks to its region wise modeling approach.
With all such analysis in mind, we will now discuss a method to model bulk charge effect
in the BSIM6 model.

2.7 Model Implementation

To illustrate the importance of the above discussion, consider Fig. 2.9. The figure shows the
ID − VD simulation with default parameters at different VSAT. VSAT is a parameter signifying
saturation velocity, which controls the drain saturation voltage. Higher the VSAT, higher should
be the Vd,sat . In BSIM6, VD,sat is modeled by tuning VSAT. For the case of long channel devices
where the saturation voltage is not decided by velocity saturation, VSAT is set to a large value
(100s of MEGA). In this figure, we see that if VSAT is increased beyond 100MEG, there is only
marginal increment in drain current. In this case, user has no way to modulate drain saturation
current. To understand such VSAT behavior, consider that BSIM6 uses it to evaluate saturation
drain charge (qd,sat ), which is then used to obtain VD,sat . If VSAT is increased, qd,sat reduces
and current increases. For some VSAT, it reduces to such a small value that it does not cause
2.7 Model Implementation 30

Drain Current (mA)

L=2 m

W=1 m

2 VSAT=2MEG, 1MEG, 500k

300k, 200k

1
Impact of the parameter VSAT

0
0 1 2 3
Drain Voltage (V)

Figure 2.9: Saturation characteristics at different VSAT: Drain current vs drain voltage simulation for
L=2mm. For the case of long channel devices where the saturation voltage is not decided by velocity
saturation, VSAT is set to a large value. However, drain current may become insensitive to VSAT beyond
some large value.

any significant impact on drains saturation current. This is also evident from (2.34), where we
see that for negligible qd,sat , the saturation current is only a function of qs . In (2.30), saturation
current is additionally a function of m, whose parameter can be tuned to achieve desired current
level.

We propose a simple modification to the drain current model of BSIM6 to bring BSIM4 like
flexibility. The new equations read as

ln (qs ) + 2qs = vp − vs at source end (2.36)

ln (qd ) + 2qd = vp − vs − m.vds at drain end (2.37)
IDS VDsat
IDS,new = ; VDsat,new = (2.38)
m m

here m is defined as (2.35). We will now briefly look at the model behavior in different region
of operations.

Linear region: In strong inversion, from (2.36) and (2.37) we can write 2qd = 2qs − m.vds .
2.7 Model Implementation 31

Model Behavior

Drain Current (mA)

0.2

Intact I
D,lin

flexibility in I
D,sat

0.1

A0=-0.06 A0=0.06

A0=0.1 A0=0

AGS=0
0.0
0 1 2 3

Drain Voltage (V)

Figure 2.10: Behavior of the proposed model: Drain current vs drain voltage at different values of the
parameter A0. A0 provides additional facility to tune drain saturation voltage and current.

From (2.27),

W m
IDS = nq · µ · · Cox · Vt2 m.vds (1 + 2qs − vds ) (2.39)
L 2
W Qs Vds
≈µ· · Cox mVds ( − nq .m. ) (2.40)
L Cox 2
IDS W Qs Vds
IDS,new = =µ· · Cox Vds ( − mef f . ) (2.41)
m L Cox 2

Thus the current has same functional form as in BSIM4.

Saturation region: For saturation characteristics governed by pinch-off, new drain current
is simply given as IDS
m
, where IDS is given by (2.34),
!2
IDS W QS
IDS,new = = µ · Cox · · (2.42)
m 2 · nq · mL Cox
!2
W QS
= µ · Cox · · (2.43)
2 · mef f L Cox

From (2.41) and (2.43), we can easily observe that with the proposed modification, drain cur-
rent model of BSIM6 takes the form of BSIM4 model, and provides additional facility to tune
2.8 Summary 32

0.2
Drain Current

Symbols: Exp. Data

Dotted Lines: Old Model 0.2

Solid Lines: New Model

m
0.1

g
Symbols: Exp. Data
0.1
Dotted Lines: Old Model

Solid Lines: New Model

0.0
0 1 2 3
0.0
Drain Voltage 0 1 2 3
Gate Voltage
(a) (b)

Figure 2.11: (a) Drain current vs drain voltage (b) gm vs gate voltage of long channel length device. The
proposed model shows improvement in imitating saturation region characteristics over existing model.

saturation region characteristics. The effective m in this new formulation is mef f = m.nq .
Fig. 2.10 shows the model results at different values of A0 (see (2.35)). We can see that the
drain saturation voltage and current are very sensitive to A0. It is also important to note that
linear region characteristics are not affected by A0. InFig. 2.11, this new model is tested on
experimental data of a long channel device received from TI. Both ID − VD in Fig. 2.11(a) and
gm,sat in Fig. 2.11(b) shows improved fitting results as compared to the conventional model.
The proposed model is currently under testing by the BSIM group, and is not yet available in
the public domain.

2.8 Summary
Scaling has always been the driving force behind the semiconductor industries. However, every
time device is scaled, it brings unpredicted challenges to the model developer. Industry standard
requires model to be physical and computationally efficient at the same time, and thus requires
thorough understanding of device physics. In continuation of series of its compact models,
BSIM group developed BSIM6 for the bulk MOSFET. We have seen that BSIM6 is symmetric
around Vds = 0, passes benchmark test, and incorporates various new features as compared to
its predecessor BSIM4. Special attempts has been made to ensure that model remains physical
and symmetric, and for this junction capacitance model and effective Vds models of BSIM4 are
adopted in modified form, thus allowing BSIM6 to pass AC and DC symmetry test successfully.
2.8 Summary 33

We report a model to improve bulk charge effect on drain saturation voltage and current. The
proposed model shows significant improvement in imitating saturation region characteristics.
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Chapter 3

Anomalous Transconductance in Halo

Implanted MOSFETs

3.1 Introduction
Halo implants are crucial in sub-micron technology as they limit the encroachment of S/D de-
pletion width in the channel and enable scaling. However, they also have significant impact on
various performance parameters, like output conductance, drain induced threshold shift (DITS),
low frequency noise etc. [1–3]. While output conductance degradation and DITS effects are
well understood in the literature, the impact on transconductance (gm ) behavior needs more un-
derstanding. Halo devices carry high current in strong inversion, as compared to the uniformly
doped (UD) devices with same threshold voltage, since the former has low on resistance due to
lower channel doping [4]. If one measures gm in the linear region, it comes out that the peak
gm of the halo device is higher than that of the UD. Since gm is as an indicator of mobility,
this directly leads to the conclusion that carrier mobility in the halo devices is higher as com-
pared to UD devices [5]. This is against the intuition, since highly doped pocket regions should
either decrease effective mobility or at best, they should not have any impact because of their
short length. This is indeed true, thanks to mobility extracted from split CV measurements [4].
This is also manifested as enhanced transconductance (gm ) and commonly referred as mobility
artefact [5]. Halo doping not only impact the linear region behavior, but also the saturation
characteristics. To the best of our knowledge, no detailed investigation on the saturation region
transconductance (gm,sat ) behavior is available in the literature [6]. We demonstrate through
experimental data as well as TCAD simulations that the gm,sat also has idiosyncratic behavior
as it undergoes slope change in gm -Vg characteristics. In this chapter, we also report and inves-
tigate atypical dependence of gm on body bias, and the impact of oxide thickness variation on
gm characteristics.

38
3.1 Introduction 39
DS,sat

DS,sat
1.02
1.02 Experimental Data Experimental Data
Normalized I

Normalized I
NMOS

0.99 1.00
NMOS

0.96 Long L Halo (Corr: 0.3259) Long L UD (Corr: 0.8575)

0.98

-20 0 20 40 -8 -4 0 4 8

Normalized V Normalized V
th,sat th,sat

(a) (b)

Figure 3.1: Measured correlation between ID,sat with Vth,sat of long channel (a) Halo implanted (b)
Uniformly doped MOSFET. The long channel halo device shows low correlation, indicating that different
mechanisms are controlling the channel in weak and strong inversion, which cannot be modeled by
conventional MOS models. Measurement data is from the same process in [7, 8].
Doping Cons. (Abs)

20 Source Example Doping Profile

10
Drain

L=2 m

19
10
18 3
N =2X10 /cm
H

18
10

17 3
N =5X10 /cm
Ch
17
10
-1 0 1

Position Along the Channel

(a) (b)

Figure 3.2: TCAD Setup: (a) N-Channel halo doped MOSFET simulated in TCAD (b) Example doping
profile along the channel with NCH =5X1017 /cm3 , NH =2X1018 /cm3 and Tox =4nm.
3.2 TCAD Setup 40

Fig. 3.1 compares correlation of the drain current with threshold voltage in saturation (ID,sat
and Vth,sat ) for long channel device with and without halo. For the long channel halo device,
ID,sat and Vth,sat show small correlation coefficient. This clearly contradicts conventional theory
and model for long channel devices which states that ID,sat is proportional to (VGS −Vth,sat )2 and
therefore expected to be fully correlated as seen for the UD devices in Fig. 3.1(b). The measured
data indicates that the drain current in weak inversion and strong inversion is controlled by
different physical mechanisms, leading to uncorrelated ID,sat and Vth,sat . To understand this
and study the overall impact of the halo implants, TCAD simulations were performed on the
bulk device.

3.2 TCAD Setup

We analyzed the physical cause of anomalous gm behavior using TCAD simulation of the fol-
lowing configurations- source side halo (SH), drain side halo (DH), both side halos, and uni-
formly doped (UD) devices at different doping and Tox conditions. Fig. 3.2(a) illustrates the
device simulated in Sentaurus TCAD [9] and Fig. 3.2(b) shows the example doping profile
along the channel with Tox =4nm, L=2µm, W=1µm, NCH =5X1017 /cm3 and NH =2X1018 /cm3 .
Tox , NCH and NH represents oxide thickness, doping of the channel region and halo regions, re-
spectively. Simulations were performed for various conditions of doping and Tox . In the TCAD
simulations, mobility degradation models at high field have been intentionally turned off in or-
der to demonstrate that gm peak in the halo devices is not related to mobility degradation at high
field like in the conventional UD devices. Furthermore, TCAD simulation shows similar trends
as in measurement data reported in this work, as well as in the literature [4, 5].

3.3 Impact of Halo Implants

3.3.1 Linear Region
Fig. 3.3 shows ID − VG of UD, SH, DH and Halo devices at VDS = 50mV . Halo, SH and DH
have nearly same threshold voltage, while the threshold voltage of UD is much smaller than rest
of the devices. This is intuitively expected based on the understanding that the highly doped
halo region increases the barrier height, leading to higher threshold voltage. Interestingly, the
strong inversion current is of similar magnitude in all the devices [5]. This can be explained
as follows: in strong inversion (SI) and at small drain voltages, MOSFET essentially behaves
like a resistor, whose effective resistance is the sum of the resistances of halo regions (Rh )
and channel region (Rch ). In SI, both the halo and channel regions are strongly inverted and,
3.3 Impact of Halo Implants 41

2
10 50

A)
NMOS

A)
TCAD Data
40
(

(
Drain Current

Drain Current
-1 V = 50mV
10 DS

30
L = 2 m

W = 1 m
20
-4
10 SH

DH
10
UD

Halo
-7
10 0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

Figure 3.3: TCAD simulations of UD, SH, DH and Halo devices in linear region at VDS = 50mV .
Channel doping is same in all the devices. Although the threshold voltage of UD is small as compared
to other devices, they all carry nearly same on-current since effective channel resistance in all the cases
is same in strong inversion. L=2µm, W=1µm.

therefore, their effective resistances are determined by the respective lengths and doping of the
regions. For long channel devices, since length of the channel region is much larger than the
halo region length, effective resistance of the overall device is determined by the resistance of
channel region. Furthermore, all the devices in Fig. 3.3 have same channel length and doping,
and hence similar Rch and on-current.
The impact of different halo region doping at fixed channel doping is shown in Fig. 3.4.
Threshold voltage increases with NH as seen in Fig. 3.4(a) due to the increased barrier height.
However, on-current remains nearly same since Rch is similar in all the cases. Note that for the
device with the highest threshold voltage (highest halo doping), although the ID remains low till
a higher gate voltage, yet it still attains the same ID as the UD device with the lowest threshold
voltage at VGS = VDD . Therefore, there is a region in ID − VG characteristics where current
sharply increases to the current level of UD. Higher the halo doping, sharper is this increase.
This leads to peak in the derivative gm , which increases with the halo doping as shown in
Fig. 3.4(b). For the TCAD simulations, we intentionally turned off the mobility degradation
model at high field. This is done in order to demonstrate that the gm peak in halo devices is a
result of the above-mentioned artifact and not related to mobility degradation at high field as in
conventional UD. Note that the UD device, as expected, does not show a peak in gm . Similar
3.3 Impact of Halo Implants 42

A)
V = 50 mV 45

A)
1
10
DS

17

NMOS N = 8 x10

(
36
Halo

(
Drain Current
18
to 2 x10

Drain Current
-2
10 N = 5 x10
17
27
CH
L = 2 m

W = 1 m
18
-5
10
dotted line: UD
9
solid lines: Halo

-8
10 0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(a)

E mobility model disabled in TCAD

vertical

60

V = 50mV
A/V)

DS
dotted line: UD

40 L = 2 m solid lines: Halo

W = 1 m
(

17
m

N = 5 x10
20 CH
g

NMOS 17
Halo doping: 8 x10 to
18
2 x10

0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(b)

Figure 3.4: TCAD simulations of Halo and UD devices in linear region at VDS = 50mV . Channel
doping is same in all the devices, and L=2µm, W=1µm. (a) Drain current (b) gm at different doping
conditions. In (b), while the threshold voltage is different, drain current in SI is same for all the cases,
causing gm to peak in the vicinity of weak-strong inversion transition region. Here, we have intentionally
turned off the mobility degradation model at high field in order to demonstrate that the gm peak in halo
devices is not related to mobility degradation at high field as in conventional UD. Similar trends are also
seen in the real device measurements [4].
3.3 Impact of Halo Implants 43

trends are also seen in the real device measurements [4]. The quantitative analysis based on
equivalent conductance of halo and channel region is presented in the next section.

3.3.2 Saturation Region

Fig. 3.5 show characteristics of UD, SH, DH and Halo devices at VD = 2V . Threshold voltage
of DH is significantly smaller than that of SH and Halo as seen in Fig. 3.5(a). This is because
the former experiences barrier lowering at the drain side, which essentially brings DH at the
same threshold level as that of UD (UD and DH has similar Vth,sat ). It is important to note
that Halo also undergoes barrier lowering at the drain side, but high barrier at the source side
prevents significant threshold voltage drop.
Fig. 3.5(b) shows gm of all the four devices. In case of SH and Halo, gm has very distinct
behavior as it initially increases, then decreases and then again increases with the gate voltage.
At smaller gate voltages, channel region is strongly inverted while halo regions still in weak
inversion. This makes the effective length of the device same as the length of the halo regions
[12]. Since gm ∝ ( L1 ), it continue to rise sharply till the halo regions also gets inverted. Once the
halo regions are inverted, the control of conduction is taken over by the channel and gm behaves
more conventionally. In Fig. 3.5(b), it is also seen that in strong inversion, gm of the UD and
SH device are same, while gm of DH and Halo device asymptomatically follows gm of UD with
an offset. This can be explained as follows: in case of pinch-off, gm ∝ (VGS − Vth,sat |D ), where
Vth,sat |D represents the threshold voltage of the drain region [13]. Since SH and UD do not
have drain side halo implants, therefore their Vth,sat |D is same, and hence same gm (and Ion ).
Similarly, DH and Halo has same Vth,sat |D as both have drain side halo implants. Also, since
Vth,sat |D for Halo (and DH) > Vth,sat |D for UD (and SH), their gm in SI as well as Ion is smaller
(gm ∝ (VGS − Vth,sat |D )). Note that threshold voltage of DH is smaller than that of SH (see
Fig. 3.5(a)) but it carries smaller Ion due to the same reason. It can, therefore, be inferred that
Ion and threshold voltage are not correlated in the long channel halo devices and hence poor
correlation is observed in real device measurements in Fig. 3.1.

3.3.3 Impact of Oxide Thickness Variation

Fig. 3.6 shows gm − VG for three different Tox : 2nm, 3nm and 4nm obtained from the TCAD
simulations. As Tox reduces, overall threshold voltage reduces and gm curve shifts left. The
device with Tox =4nm shows more peaky behavior as compared to thinner Tox device. It is
important to note that since mobility degradation with vertical gate field models have been
turned off, this peaks are only due to the halo regions. Inset figure shows the ratio of max. gm to
3.3 Impact of Halo Implants 44

4
10 I > I

A)
ON,SH ON,DH

A)
V > V 300
TH,SH TH,DH

( 1
10

(
Drain Current
TCAD Data

Drain Current
200
-2
10 SH
V = 2V
DH DS

UD
L = 2 m 100
-5
10 Halo
W = 1 m

NMOS

-8
10 0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(a)

400
V = 2V
DS
NMOS
TCAD Data
300
A/V)

slope change

200 DH

Halo
(

SH
m

100 UD
g

L = 2 m

W = 1 m

0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(b)

Figure 3.5: Comparison of transconductance of SH, DH, Halo and UD devices in the saturation at VDS =
2V . gm of DH is very different from that of SH and Halo, as it does not undergo change of slope around
threshold voltage. Most of the compact models model the saturation characteristics of halo implanted
MOSFET by two transistor equivalent model [10, 11] (proposed in [3]), one representing the drain side
halo region and other representing channel. By neglecting the source side halo region, gm characteristics
can not be modeled accurately. L=2µm, W=1µm
3.3 Impact of Halo Implants 45

TCAD Simulation V =50mV

1.4
90 DS

Ratio
L=2 m
1.2
g m Ratio gm
A/V)
max .

m
W=1 m
g m VGS Vth
_

g
@ 0.5

60 1.0
2 3 4
T = 2nm T (nm)
ox ox
(
m
g

30

T = 3nm
ox

T = 4nm
ox

0
0.0 0.5 1.0 1.5

Gate Voltage (V)

Figure 3.6: Dependence of gm on Tox in presence of halo implants: gm − VG at VDS = 50mV for
Tox =2nm, 3nm and 4nm. Inset figure plots the ratio of maximum gm to the gm at 0.5V gate overdrive.
As Tox increases, Vth,H increases by greater amount as compared to Vth,CH since γH > γCH . Therefore
∆Vth and hence gm ratio increases with the Tox as shown in the inset figure. Here, we have intentionally
turned off the mobility degradation model at high vertical field in order to demonstrate that the gm peak in
halo devices is not related to mobility degradation at high field as in conventional UD. L=2µm, W=1µm.

the gm at VGS − Vth = 0.5V which reduces as Tox is scaled down. To understand this, consider
threshold voltage of the halo and channel regions which can be written as [14]
p
Vth,H ∝ γH 2φf + VSB (3.1)
p
Vth,CH ∝ γCH 2φf + VSB (3.2)
√
γ represent the body factor which is ∝ Tox . doping. As Tox increases, both Vth,CH and Vth,H
increases. However, Vth,H increases by larger amount as compared to Vth,CH since γH > γCH
(NH > NCH ). For a given VB ,
p p
∆Vth = VT H,H − VT H,CH ∝ Tox · ( NH − NCH ) (3.3)

For given doping levels, ∆Vth increases with Tox and therefore for a given length of halo region,
gm ratio also increases with Tox .
3.4 Halo Implanted Devices: Quantitative Analysis 46

3.4 Halo Implanted Devices: Quantitative Analysis

Halo implanted MOSFET can be accurately modeled using a three transistor sub-circuit shown
in Fig. 3.7 [5]. Here we will develop a compact model of effective conductance of the halo
devices by analytically solving the sub-circuit. Following formulation is presented within the
framework of BSIM6 MOS model where the basic charge voltage relationship is given by (2.5)
[15] which is repeated below,

2q + ln(q) = vp − vch (3.4)

where q is the normalized inversion charge density (=qs at source end, qd at drain end), vp =
ψp − 2φf , and ψp and vch are the normalized pinch off and channel potential respectively. This
equation is analytically solved for q in BSIM6 (see Appendix A for more details).

3.4.1 Strong Inversion

In strong inversion, the term 2q dominates log term in (3.4) giving 2q ≈ vp − vch . Subsequently,
the drain current (normalized) is expressed as [10],

(vd − vs )
ids = (qs − qd )(1 + qs + qd ) = (1 + qs + qd ) (3.5)
2
W
Ids = 2nq Cox Vt2 µids = Geq Vds (3.6)
L
where
1 + 2qs
Geq ≈ ζ , ζ = µnq Cox Vt W (3.7)
L

The drain current normalization factor is 2nq Cox Vt2 W L

(see Table 1 in Chapter 2). From the
three transistor equivalent sub-circuit in Fig. 3.7 [16],

I1 = Geq1 (V1 − VS ), I2 = Geq2 (V2 − V1 ) (3.8)

I3 = Geq3 (VD − V2 ), I = I1 = I2 = I3 (3.9)
3.4 Halo Implanted Devices: Quantitative Analysis 47

Figure 3.7: Modeling of halo implanted MOSFET: three transistor based modeling. The drain and
source side halo regions are modeled using highly doped transistors of length=LH [5]. This sub-circuit
is analytically solved to obtain equivalent conductance.

from above equations,

I = GEQ,SI .(VD − VS ) (3.10)

" #−1
1 1 1
GEQ,SI = + + (3.11)
Geq1 Geq2 Geq3

using Geqi = ζ 1+2q

Li
i
from (3.7),
" #
1 1 2Lh Lch
= + (3.12)
GEQ,SI ζ 1 + 2qs,h 1 + 2qs,ch
" #
1 2Lh Lch
≈ + (3.13)
2ζ qs,h qs,ch

3.4.2 Weak Inversion

In weak inversion, ln(q) dominates 2q term in (3.4) leading to q ≈ exp(vp − vch ) << 1
(threshold condition defined by Idrif t = Idif f corresponds to q = 0.5 [17]). The drain current
can be approximated as,

ids = (qs − qd )(1 + qs + qd ) ≈ (qs − qd ) (3.14)

= e(vp −vs ) − e(vp −vd ) = evp (e−vs − e−vd ) (3.15)
W
Ids = 2nq Cox Vt2 µids = Geq Vt (e−vs − e−vd ) (3.16)
L
3.4 Halo Implanted Devices: Quantitative Analysis 48

where Geq = 2µnq Cox Vt W

L
evp ≈ 2ζ Lq

I1 = Geq1 Vt (e−vs − e−v1 ), I2 = Geq2 Vt (e−v1 − e−v2 ) (3.17)

I3 = Geq3 Vt (e−v2 − e−vd ), I = I1 = I2 = I3 (3.18)

from above equations,

I = GEQ,W I Vt (e−vs − e−vd ) (3.19)

" #
1 1 1 1
= + + (3.20)
GEQ,W I Geq1 Geq2 Geq3
" #
1 2Lh Lch
= + (3.21)
2ζ qs,h qs,ch

3.4.3 Total Current

From (3.13) and (3.21), the effective conductance in weak inversion and strong inversion is
same i.e. GEQ = GEQ,SI = GEQ,W I . The overall drain current is summarized as

IDS = GEQ .VDS Strong Inversion (3.22)

= GEQ .Vt (e−vs − e−vd ) Weak Inversion (3.23)
" #
1 1 2Lh Lch 1 1
= + = + (3.24)
GEQ 2ζ qs,h qs,ch GH GCH

Here GH and GCH represents the conductance of the halo region and channel region, respec-
tively. Fig. 3.8(a) shows GEQ , GCH and GH as a function of gate voltage at VDS = 50mV
and VB = 0V . Asymptotically, GEQ = GH in weak inversion and GEQ = GCH in strong in-
version. Threshold voltage of the halo regions is higher than that of the channel region due to
high doping. Therefore at small gate voltages, the conductance of halo region is much smaller as
compared to that of the channel region, and hence effective conductance of the device is the con-
ductance of the halo region. In strong inversion, both the channel and halo regions are inverted
and effective conductance is now decided by the length of each region. Since LCH >> LH ,
GCH << GH and hence GEQ = GCH in strong inversion. This switching of the conductance
0
leads to hump in first derivative of the GEQ (GEQ ) as seen in the figure and is responsible for
the observed peakiness (mobility artefact) in gm characteristics of the halo implanted devices.
To validate this approach, first derivative of gds at VDS = VB = 0V , as obtained from TCAD,
is plotted as a function of gate voltage in Fig. 3.8(b) for UD and Halo device. While gds of
3.4 Halo Implanted Devices: Quantitative Analysis 49
A/V)

5 Model Results 0.6 -4 TCAD

750
10 10

= 0
W = 1 m

2
L = 2 m

(mA/V
L = 30nm L = 2 m
Eq. Conductance (

DS
-6

g
V =50mV
DS 0.4 10 500

@ V

/dV
1 18 3

10 N =10 /cm Halo

g
H

/dV
N =10
17
/cm
3
UD

ds
CH
-8
10

ds

dg
EQ
G G'
0.2 250

g
EQ EQ
-3
10

dG
G V = 0
EQ,CH
DS
-10
G
EQ,H 10

0.0 0
0.0 0.5 1.0 1.5 2.0 0.0 0.4 0.8 1.2 1.6

Gate Voltage (V) Gate Voltage (V)

(a) (b)

1.5
V = 50 mV L = 2 m
DS
(mA/V )

W = 1 m
2

NMOS
L = 30nm
h
1.0 17 3
N = 5 x 10 /cm
CH
EQ
G'

0.5 17 18 3
N =8 x10 to 2 x10 /cm
H

0.0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(c)

Figure 3.8: (a) Equivalent conductance of the halo and channel region as a function of gate voltage. In
weak inversion, GH << GCH because of high threshold voltage of the halo region. In strong inversion,
due to the formation of inversion layer, GH >> GCH since length of channel region is greater than that
of halo region. Asymptotically, GEQ = GH in weak inversion and GEQ = GCH in strong inversion. (b)
Comparison of derivative of gds extracted from TCAD at VDS = 0V vs gate voltage for UD and Halo
devices. Derivative of gds shows qualitatively same behavior as predicted by model in (a). The switching
of conductance gives rise to peaking gm characteristics in Fig. 3.4(a). (c) First derivative of GEQ at
different doping conditions at VDS = 50mV . The model predicts similar trend as in Fig. 3.4(b).
3.5 Compact Modeling and Validation 50

Figure 3.9: Modeling of halo implanted MOSFET. The source side halo region is modeled using bias
dependent resistor. The impact of drain side halo region on the threshold voltage and output conductance
is analytically modeled in BSIM6 through the DITS model [3].

UD stays constant is strong inversion, it rises to a peak value before decreasing to the level of
UD in case of Halo device. This is similar to our model prediction in Fig. 3.8(a). Fig. 3.8(c)
0
shows GEQ at fixed NCH (=5X1017 /cm3 ) and different NH . We have seen that increasing NH
causes increase in peak of gm in Fig. 3.4(b) (and in [4]), and the proposed model also predicts
the similar trend.

3.5 Compact Modeling and Validation

Saturation characteristics of the Halo implanted devices are traditionally modeled by two tran-
sistor equivalent sub-circuit: one representing drain side halo and other representing channel
region [3, 13]. This, however, is insufficient to capture peculiar attributes of gm in saturation
region. As seen in Fig. 3.5(b), unlike SH, DH does not show unconventional gm behavior in
saturation and it can be inferred that source side electrostatics is responsible for strange gm
characteristics. This can be explained as follows: in DH, drain side barrier is reduced at higher
drain bias in saturation. This brings halo and channel regions at nearly same threshold volt-
age for all the bias range. This is also seen in Fig. 3.5(a) where UD and DH has nearly same
threshold voltage in saturation. Thus, no slope change in gm is observed. Since two transistor
model ignores source side halo region in saturation, it cannot reproduce such gm behavior. Halo
device, therefore, can be modeled by representing the two halo regions by transistor with length
L=LH . In [3], analytical model is derived from the two transistor (drain end halo and channel)
model for DITS. This model is incorporated in the BSIM6 MOS model. We propose two el-
ement sub-circuit model as shown in Fig. 3.9, where BSIM6 is used for modeling drain side
halo and channel region, and other bias dependent element for source side halo region which is
characterized as,
3.5 Compact Modeling and Validation 51

1 NMOS 20
A)

A)
10 20 NMOS L=2 m W=2 m

L=2 m W=2 m Symbols : Data

(

(
V =50mV

A/V)
15 Lines : Model DS
Drain Current

Drain Current
V =50mV 15
-1 DS

10

10

(
10

m
g
-3 V =0,-275m,-550m,
10 B

-1.1V 5 5
V =0,-275m,-550m,
B
Solid Lines : Model
-1.1V
-5 Symbols : Exp. Data
10 0 0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0

Gate Voltage (V) Gate Voltage (V)

(a) (b)

Figure 3.10: NMOS- Model validation with experimental data in linear region at VDS = 50mV : (a)
ID − VG (b) gm − VG at different body biases. L=2µm, W=2µm.

W
IRH = U 0H.Cox .Vs s,ef f .Vgstef f (3.25)
LH i

where
" #
−V T H
2NH Vt .ln 1 + exp( VGS
2NH Vt
)
Vgstef f = −VT H
(3.26)
1 + 2NH .exp(− VGS 2NH Vt
)
V si s
Vsi s,ef f =" ! DELT 1 #DELT AH (3.27)
AH
Vsi s
1+ Vdsat,H

Vdsat,H = Vgstef f + 2Vt (3.28)

Here U0H, LH, VTH and NH are the model parameters representing mobility, length, threshold
voltage, sub-threshold slope of the halo region. DELTAH is the smoothing parameter. It is
important to note that the halo device can also be modeled by using transistor for both source
side halo region and channel region, however it will increase computational time.
Model validation with NMOS: The model is validated with low power 45nm CMOS tech-
nology node measurements [7, 8]. Fig. 3.10 (a) and Fig. 3.10 (b) show ID and gm vs VG for
3.5 Compact Modeling and Validation 52

(mA)
(mA)
NMOS

-2 V =1.21V
10 DS
0.2

Drain Current
Drain Current

V =0,-275m,-550m
B
-5
10
Solid Lines : Model

Symbols : Data
0.1
-8
10
L=2 m W=2 m

-11
10 0.0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(a)

Solid Lines : Model NMOS 0.6

0.2
Symbols : Data

)
2
(mA/V)

L=2 m
(mA/V
W=2 m

V =0, -275m, -550mV

B
0.3
0.1
m

gm' data
m

V =1.21V
DS
g'
g

old model

this work

0.0
0.0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(b)

Figure 3.11: NMOS- Model validation with experimental data in saturation region at VDS = 1.21V : (a)
ID − VG (b) gm at different body biases. The proposed model accurately captures gm behavior across
body biases. Compact model ignoring source side halo region electrostatic do not capture typical gm
behavior. L=2µm, W=2µm.
3.5 Compact Modeling and Validation 53

6 TCAD Simulations
PMOS
15
|V |=50mV V : 1 to 0 V
DS b

|V |=50mV

A/V)
A/V)

DS

4
10 L=2 m
L=2 m
16.2 0.26 W=1 m

V
(

th,Halo
W=2 m
16.0
m

m
m

Max. g
0.25
g

-V
Lines : Model
2 15.8
5

th,UD
Symbols : Exp. Data 15.6 0.24

(V)
15.4
0.23
0.0 0.5 1.0
V =0, 0.45, 0.9 V
B
V (V)
0
b

0
-2.0 -1.5 -1.0 -0.5 0.0 -2.0 -1.5 -1.0 -0.5 0.0
Gate Voltage (V) Gate Voltage (V)
(a) (b)

Figure 3.12: Impact of body bias: (a) gm − VG of long channel PMOS in linear region for different
VB . Peak of gm initially increases and then decreases with VB . Similar trends are also seen in TCAD
simulation in (b). Inset figure in (b) shows that threshold voltage difference between the halo region and
the channel region has non-monotonous trend which is responsible for such behavior of max. gm with
VB .

different body bias conditions, respectively at VDS = 50mV . Fig. 3.11 shows ID and gm in
saturation region VDS = 1.21V . Compact model ignoring source side halo region can not
0
model gm,sat as evident from Fig. 3.11(b) which also compares gm,sat fitting result as obtained
from proposed model and conventional model. The proposed model accurately capture peculiar
gm,sat trends across different body biases.
Model validation with PMOS: Fig. 3.12(a) shows the model-data overlay for a p channel
transistor with L = W = 2µm at |VDS | = 50mV and VB = 0, 0.45, 0.9V . It is interesting to
note that peak value of gm in Fig. 3.12(a) initially increases and then decreases with VB . It is
known that peak gm of UD devices decrease with VB due to increase in scattering. To the best
of our knowledge, such gm behavior is reported for the first time [6]. To understand this, TCAD
simulations with NCH =5X1017 /cm3 and NH =1.2X1018 /cm3 at different body bias is done and
gm result is shown in Fig. 3.12(b). The TCAD result also shows non-monotonous trend of max.
gm with body bias as shown in the inset figure. The maximum gm is the strong function of the
relative threshold voltage difference between the channel and halo region (∆Vth ). As body bias
is swept, from (3.1) and (3.2), one would expect halo region to experience higher increase in
threshold voltage as compared to channel region since γH > γCH (NH >NCH ). This is indeed
true, and therefore initially ∆Vth increases with VB as seen in the inset of the Fig. 3.12(b).
3.5 Compact Modeling and Validation 54

Solid Lines : Model

A)
100 2
100
A)

L=2 m |V |=1.98V
10 Symbols : Experimental Data DS

W=2 m
0.2

)
(

V =0, 0.45V

2
Drain Current

(mA/V)
B
|V |=1.98V
Drain Current

(mA/V
DS
75
0
V =0, 0.45 V
10 L=2 m
B
gm' data W=2 m
50 50 this work
0.1

m
m
old model

g'
g
-2
PMOS
10
25
Solid Lines : Model

Symbols : Exp. Data PMOS

-4
0 10 0 0.0
-2.0 -1.5 -1.0 -0.5 0.0 -2.0 -1.5 -1.0 -0.5 0.0

Gate Voltage (V) Gate Voltage (V)

(a) (b)

Figure 3.13: PMOS- Model validation with experimental data in saturation region: (a) ID − VG (b) gm at
VB = 0, 0.45V . gm and its derivative are accurately modeled by the proposed model. L=2µm, W=2µm.

At larger VB , the depletion width in the halo region increases and for some VB , it reaches the
boundary between the halo and the well region. If VB is increased beyond this, the additional
depletion charges are obtained by uncovering of the lightly doped substrate region, and thus γH
approaches γCH [18, 19]. As a result, ∆Vth and hence max. gm reduces at higher VB . Such VB
dependency on Vth,H is modeled as-

2
Vth,H (Vb ) = Vth,H (Vb = 0) + K1.VBS + K2.VBS (3.29)

here K1 and K2 are the model parameters. The model accurately captures the peak of gm as
shown in the Fig. 3.12(b). Fig. 3.13 reports pmos characteristics in saturation region. The
proposed model has good agreement with the measurement data over wide range of biases.

3.5.1 Impact of Gate Length Scaling and Temperature Variation

Fig. 3.14(a) compares measured ID −VG of the NMOS for L=2µm and L=120nm at VDS =50mV.
From the figure, it can be observed that gate length scaling has no/little impact in the weak in-
version, since in weak inversion the characteristics are determined by the halo regions which do
not scale with gate length. In fact, such control on the sub-threshold behavior of the short chan-
nel device is the advantage of pocket implants. Fig. 3.14(b) compares ID − VG of a L=120nm
NMOS device at two temperatures: 27o C and 150o C. At higher temperature, two competing
3.5 Compact Modeling and Validation 55

Measured Data for different temperatures

A)
A)
1
10 120

(
(
NMOS

Drain Current
o

Drain Current
T=27 C
o
T=150 C
-2
10 80

V =50mV
DS

-5
10 L=120nm 40
W=2 m

-8
10 0
0.0 0.5 1.0 1.5 2.0

Gate Voltage (V)

(a) (b)

Figure 3.14: Impact of gate length scaling and temperature variation: Measured ID − VG of NMOS at
VDS =50mV (a) for channel length L = 2µm and L = 120nm. Sub-threshold characteristics are determined
by the halo regions, therefore, scaling has no impact in weak inversion. (b) Short channel ID − VG at
two different temperatures T=27o C and T=150o C.

(a) (b)

Figure 3.15: NMOS- Model validation with experimental data for a short channel device in linear and
saturation region: (a) ID − VG (b) gm − VG . L=120nm, W=1µm.

effects come into play. First, the average thermal energy of the carrier increases, and thus more
carriers can surmount the barriers and participate in current conduction. On the other hand, car-
rier mobility decreases due to increase in lattice vibrations (phonon scattering). As a result, the
sub-threshold current increases and strong inversion current reduces due to mobility reduction
with temperature [14].
3.5 Compact Modeling and Validation 56

1
1.00
10 Solid Lines :Model 0
NMOS
1.2

(mA)
T=150 C

(mA)
V =50mV
DS Symbols :Exp Data

17 3
N = 4*10 /cm L =30nm
CH H
0.75

Drain Current
H

17 3

Drain Current
N = 4*10 /cm L =40nm -2
/G

CH H
10 0.8
CH

0.50
Ratio G

Model Results Red: V =1.21V

-5 DS

10 0.4
Black: V =50mV
DS
0.25
Strong Inversion
18 3
N =10 /cm L=120nm W=2 m
H

-8
0.00 10 0.0
2 3 0.0 0.5 1.0 1.5 2.0
10 10
Gate Length (nm) Gate Voltage (V)
(a) (b)

Figure 3.16: Ratio of equivalent conductance of the channel region to the halo region vs gate length in
strong inversion (obtained using 3.24). For short gate lengths, halo and channel regions merge and the
ratio approaches to unity.

Fig. 3.15 shows the model-data overlay for the short channel device. From the figure, it can
be noticed that the short channel device does not show distinctive hump in the gm , which is
expected since as the channel length decreases, the two halo regions merge and the device
behaves like a uniformly doped device. To further illustrate this, ratio of the conductance of
channel region to the halo region in strong inversion as obtained from (3.24) is plotted as a
function of gate length in Fig. 3.16(a). At longer channel lengths, we have already seen that
GCH << GH (refer to Fig. 3.8 for the discussion) and, therefore, the ratio in the Fig. 3.16 is
very small. As gate length scales down, effective length of the lightly doped channel region
reduces and the ratio gradually increases. For short gate lengths, the ratio approaches to unity,
indicating that the device starts to behave like a uniformly doped device. Fig. 3.16(a) also
shows conductance ratio for two different LH . For a given NH and NCH i.e. fixed threshold
voltage of channel and halo regions, if the length of the halo regions is increased from 30nm
to 40nm, the ratio in the figure increases rather rapidly as the gate length is scaled down. This
indicates that the gate length at which the device starts to behave like uniformly doped device
is smaller at LH =40nm than LH =30nm. It is important to note that these results are produced
from the model in (3.24), which is very simple way to look at the halo devices. Real devices
generally have complex doping profile both in the halo region (Gaussian doping) as well as in
the channel (retrograde/inverse retrograde) channel. Further, the model can also capture the
temperature effect as seen from the Fig. 3.16(b) which shows model results for short channel
device at T=150o C.
3.6 Summary 57

Figure 3.17: Input referred noise prediction: comparison of old and new model in strong inversion. The
models prediction differs by 10-15%, which can be critical for the analog designs.

Accurate modeling of current and derivatives for wide bias range is very important for the
analog devices. In Fig. 3.17, input referred noise is plotted as a function of gate voltage using
BSIM6 model with and without new gm model at 1 KHz operating frequency. Default noise
parameters are used for the simulation. It can be seen that the model predictions differ by 10-
15% in strong inversion region. The difference could vary with pocket/channel region doping
and length. These results, may not reflect the real scenario, nevertheless, it certainly point that
the results from the two model can be different, which is critical for the analog applications.

3.6 Summary
In this chapter, we reported that gm in halo devices is different as compared to uniformly doped
devices both in linear and saturation regions. The impact of halo implants on gm is investigated
using extensive TCAD simulations. It is common practice in compact modeling community to
neglect source side halo region, which is actually important for accurate modeling of the halo
devices. The impact of halo regions on gm is found to be more prominent for thicker oxides.
A physical reasoning to explain gm behavior is presented along with a SPICE model to model
such gm characteristics across different biases. The proposed model is implemented within the
framework of the BSIM6 MOS model, and is validated with measurement data both for the n
and p channel MOSFETs.
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Chapter 4

Flicker Noise in Presence of Doping

Non-Uniformity: Analysis and Modeling

4.1 Introduction

Low frequency noise has been critical in sub-micron technology, both for the analog and digital
designs [1–3]. Random Telegraphic Noise (RTN), which originates from trapping-detrapping of
the carriers, has been escalating with scaling, and results in reduced noise margins. It has been
shown that the equivalent threshold voltage variation due to RTN exceeds threshold voltage
variation due to random dopant fluctuation in 22nm technology node, posing a real challenge
to the device stability [4, 5]. Furthermore, the phase noise which is the key figure in wireless
communication design has been dominated by up conversion of the flicker noise [6].
Lateral asymmetry is seen at several places, and non-uniform doping is one such case (ob-
served in pocket implanted devices [7], LDMOS transistor [8, 9], and even in vertical nanowire
transistors [10]). Lateral asymmetry may also be caused by hot carrier degradation and inter-
esting analysis on this effect is presented in [11]. It has been reported that the low frequency
noise (1/f) behavior of these devices is significantly different from that of uniformly doped de-
vices [12–15], especially at low gate voltages. Since flicker noise is increasingly important for
nano scale devices and circuits, it is important to study the flicker noise behavior of a non-
uniformly doped channel (NUDC) devices.
Our study shows that Klaassen Prins (KP) method, which forms the basis of the noise model in
MOSFETs, underestimates flicker noise in NUDC devices. The same KP method overestimates
thermal noise by 2-3 orders of magnitude in NUDC devices as demonstrated in [16]. Here
we will discuss the physics behind such atypical 1/f noise behavior in NUDC MOSFETs, and
reason of apparent opposite trend in 1/f and thermal noise characteristics.

60
4.2 TCAD Setup 61

2
10

A_min
Source

N (x)/N
1
10
A

Numerical Doping

Experimental Doping Drain

0
10
0.0 0.5 1.0

x/L

Figure 4.1: Doping (NA ) profile along the channel of a NUDC device used in this study. The experimen-
tal doping is extracted from [8]. Doping at the source and the drain ends are 1018 cm−3 and 1016 cm−3 ,
respectively. L=2µm, W=1µm.

4.2 TCAD Setup

The impact of doping non-uniformity on 1/f noise is studied using Sentaurus TCAD [17] sim-
ulations. Device used in this study has erfc doping profile, as shown in the Fig. 4.1. Substrate
doping is 1018 cm−3 at the source and 1016 cm−3 at the drain end. Gate oxide SiO2 is 2.5nm
thick, and the channel is 2µm long and 1µm wide. In the TCAD simulations, flicker noise is
obtained using Green’s function approach [17]. The effect of vertical electric field and impurity
concentration on mobility are modeled using Lombardi and Phumob model, respectively [17].

4.3 Modeling 1/f Noise in NUDC Devices

4.3.1 Noise Model
Drain current under the standard drift-diffusion formalism is expressed as [18],

Id =Idrif t + Idif f (4.1)

dV dV
Id (x) =W Qi (x, V )µ(x, ) (4.2)
dx dx
dV dV
Id (x) =g(x, V, ) (4.3)
dx dx
where Qi represents the inversion charge density along the channel (x direction), µ is the mo-
bility, V is the channel potential and g represents the channel conductance. Due to non uniform
4.3 Modeling 1/f Noise in NUDC Devices 62

channel doping, inversion charge density is a function of channel position even at zero drain
bias, leading to explicit dependency of inversion charge on channel position. Similarly, mobil-
ity is also a function of channel position along with lateral and vertical electric field. The total
current in the channel is the sum of transport current and noise current. In the presence of noise,
channel potential and hence transport component of the current will be altered. Therefore, noise
current δid at any position x in the channel can be expressed as [16],

δid = Itotal − Itransport (no perturbation) (4.4)

" #
d(V0 + v) d(V0 + v) dV0 dV0
= g(x, V0 + v, ) + δin (x) − g(x, V0 , ) (4.5)
dx dx dx dx

here V0 and v are the unperturbed and perturbation in the channel potential respectively, and
δin (x) is the Langevin noise source [19]. It can be shown that after mathematical simplification,
total noise current comes out as [20]

L
RL
f (x)δin (x)dx
Z
0
∆id = δid dx = RL (4.6)
0 0
f (x)dx

giving drain current flicker noise power spectral density,

Z L
Si2d = |∆Ad |2 Sδi2n dx (4.7)
0

where
f (x) g0 R(x)
∆Ad (x) = R L , f (x) = ∂g0
(4.8)
f (x)dx
0
g0 + ∂E 0
E0
Z x !
1 g0 ∂g0
R(x) = exp − · ∂g0
dx (4.9)
0 g0 g0 + ∂E0 E0 ∂x

Here g0 is the unperturbed channel conductance and E0 = dV dx

0
. Sδi2n in the above equation
is power spectral density of the local noise source. From (4.7), it is evident that ∆Ad (vector
impedance field (IF)) is responsible for noise propagation from channel to the drain terminal.
In case of uniform channel doping, ∂g∂x
0
= 0. Further, neglecting the impact of mobility degra-
dation, (4.8) and (4.9) gives [18],

1 1
f (x) = R(x) = 1; ∆Ad (x) = R L = (4.10)
dx L
0
4.3 Modeling 1/f Noise in NUDC Devices 63

Thus, unlike for the case of NUDC device, IF is bias and position independent for uniformly
doped MOSFETs. This is the key difference between the two cases.

4.3.2 The Local Noise Source

Flicker noise in MOSFETs is attributed to the mobility and/or carrier number fluctuation [21–
23]. There exist popular models which unify the two approaches [24–26]. We have used the
unified model presented in [25] for modeling local noise source, which has been widely used
in the industry standard bulk MOSFET models [27–29]. In this model, the fractional change in
the local drain current (δId ) due to fluctuation in oxide trap charges is given as,
" #
δId 1 δ∆N 1 δµ
= ± δ∆Nt (4.11)
Id ∆N δ∆Nt µ δ∆Nt

where ∆N and ∆Nt are the number of carriers and number of traps in channel area W ∆x. It
can be shown that for uniform spatial distribution of traps near the interface, and assuming that
probability of an electron penetrating into the oxide decreases exponentially with the distance
from the interface, the local noise source power spectral density (PSD) can be approximated
as [14, 24]
" #2
kT Id2 1
Sδi2n = Nt (Ef n ) ± αµ (4.12)
γf W N

where k, T , γ, Nt and α are the Boltzman’s constant, temperature, attenuation coefficient,

occupied trap density and scattering coefficient respectively, and Qi = q.N .

4.3.3 Drain Current Model of NUDC Device

Local noise source in (4.12) requires drain current to be known in the device. For NUDC
devices, conventional compact model based on the assumption of uniform channel doping are
not valid. In this work, the compact model presented in [8] is used to model transport in the
presence of doping non-uniformity. In this model, the drain current is expressed in terms of
normalized inversion charge densities at the source and the drain ends as follows,
ids
" !#
2ids qd − ρv ∆ψp
∆ψp = ψp,s − ψp,d = 2(qs − qd ) + (1 + )· ln ids (4.13)
ρv ∆ψp qs − ρv ∆ψp

here ∆ψp = ψp,d −ψp,s where ψp is the normalized pinch-off potential and subscript s/d denotes
4.3 Modeling 1/f Noise in NUDC Devices 64

A)
1

A)
10 V
DS
=50mV

10

(
(

Drain Current
NMOS
Drain Current
0
10
L=2 m

W=1 m

-1
5
10

Solid Lines : Model

-2 Symbols : TCAD Data

10
0
0.0 0.5 1.0

Gate Voltage (V)

Figure 4.2: Drain current vs gate voltage characteristics for the non uniformly channel doped device at
Vds = 50mV. The charge based model specific to NUDC devices in [8] is used to model the drain current,
which shows excellent matching with the TCAD data. L=2µm, W=1µm.

source/drain ends. ids represents the normalized drain current, and ρv accounts for the mobility
degradation due to vertical field. qs and qd are the normalized inversion charge densities at the
source and the drain ends, which are obtained by analytically solving

2q + ln(q) = ψp − 2φf − vch (4.14)

where vch is the channel potential and φf is the bulk potential normalized to thermal voltage.
Pinch off potential is the surface potential at which inversion charge density in the channel is
zero, and is related to the gate voltage as [9]
q
−ψP
VG − VF B = ψP + sign(ψP )Γ UT e UT + ψP − UT (4.15)

Note that in above equation, ψP is de-normalized and is a function of channel doping through
√
body factor Γ = 2qNCox
A
and is known at every point in the channel. UT and VF B are the thermal
voltage and flat band voltage, respectively. Drain current for different gate voltages is obtained
from (4.13) and (4.15). Fig. 4.2 shows the drain current predicted by the model overlay with
the TCAD data at VDS = 50mV . The model shows excellent matching with the TCAD data.
4.3 Modeling 1/f Noise in NUDC Devices 65

Figure 4.3: Equivalent representation of MOSFET for flicker noise modeling.

4.3.4 Proposed Methodology

Calculation of flicker noise from (4.7) and (4.12) requires inversion charge density and channel
potential to be known at every point in the channel. For that, the channel of length L is divided
into large number of smaller segments. The NUDC device can be viewed as composure of
series connected N transistors (still NUDC) as shown in Fig. 4.3. N is chosen sufficiently large
so that it do not affect simulation results.
Current continuity is used to obtain inversion charge density at different position in the channel.
Since inversion charge density at the source end is known from (5.12), (4.13) is used to deter-
mine inversion charge density at the drain end of the first sub-transistor in the channel, qi,1 (i.e.
qi at x = x1 ),
" ids,1 !#
2ids,1 qi,1 − ρv ∆ψ p,1
∆ψp,1 = 2(qs − qi,1 ) + (1 + ) ln ids,1 (4.16)
ρv ∆ψp,1 qs − ρv ∆ψp,1

where ∆ψp,1 = ψx1 − ψp (p, s). ψp,s and ψp (x1 ) both are known from (4.15). In this equation,
normalized drain current
IDS
ids,1 = W
(4.17)
2nq x1 −x0 Cox UT

Once qi,1 is obtained, it is used again in (4.13) with ∆ψp = ψp (x2 ) − ψp (x1 ) to calculate qi,2 .
Inversion charge density at all the points in the channel is, thus obtained in similar way. Next,
4.4 Results and Discussion 66

channel potential (vch ) along the channel is obtained using 5.12 which gives,

vch = ψp − 2φf − 2qi − ln(qi ) (4.18)

In this work, we have neglected the mobility degradation effect to delineate the impact of doping
non-uniformity, which from (4.8) and (4.9) leads to,
!
Z x
1 ∂g0
f (x) = R(x) = exp − dx (4.19)
0 g0 ∂x

∂g0
where ∂x
can be represented as

∂g0 ∂Qi ∂qi

= Wµ = −2W µnq Cox UT (4.20)
∂x ∂x ∂x

It is important to note that the term ∂q

∂x
i
which is zero for the uniformly doped MOSFETs, has
the finite contribution in the non-uniformly doped channel device, and we will see that it is
mainly responsible for deviation from classical KP based methods. ∂q ∂x
i
is obtained as follows-

dqi ∂qi ∂qi dvch

= + (4.21)
dx ∂x ∂vch dx

which gives,

∂qi dqi ∂qi dvch

= − (4.22)
∂x dx ∂vch dx

from (4.18),

∂qi qi
=− (4.23)
∂vch 2qi + 1

Since dqdx
i
and dvdxch are already known (qi and vch are known at all the N points in the channel),
∂qi
∂x
is obtained from (4.22) and (4.23) and IF by substituting (4.19) in (4.8), which is then used
with local noise source in (4.12) to give overall flicker noise from (4.7).

4.4 Results and Discussion

Fig. 4.4 shows the drain current flicker noise power spectral density (SID ) vs gate voltage for
a non uniformly doped channel MOSFET at VDS = 50mV , obtained from KP (red line) and
4.4 Results and Discussion 67

-20
10
NMOS

/Hz)
-22
10
2
(A
ID

TCAD
S

-24 This Work

10
L=2 m KP Method

W=1 m

-26
10
0.0 0.5 1.0

Gate Voltage (V)

Figure 4.4: Drain current flicker noise power spectral density vs gate voltage at VDS =50mV. KP method,
which treats IF as constant independent of channel position and bias, underestimates flicker noise, espe-
cially in weak inversion region. Numerical method simulation are in agreement with the device simula-
tion data extracted from Sentaurus TCAD. L=2µm, W=1µm.

numerical simulations (blue line). It is evident from Fig. 4.4 that KP based method underesti-
mates the flicker noise by more than an order of magnitude, especially in weak inversion region.
Furthermore, this behavior of flicker noise is contrary to that of thermal noise in laterally non
uniform channel MOSFETs, where KP based methods overestimates thermal noise, as reported
in [16].
Total flicker noise at the drain terminal is the sum of local noise source weighted by the
impedance field (see (4.7)). Consider the behavior of flicker noise Sδi2n in (4.12), which has
striking dissimilarity with the thermal noise Sδi2n given 4qW Qi Dn , where Dn is the noise dif-
fusivity [16]. Unlike in (4.12), where Sδi2n varies inversely with qi , for thermal noise Sδi2n is
directly proportional to qi . Since doping is highest at the source end (see Fig. 4.1), threshold
voltage decreases and hence inversion charge increases along the channel from source to drain,
as shown in Fig. 4.5 for two gate voltages Vg = 0.1V and 0.6V . Therefore, while Sδi2n for flicker
noise peaks at the source end and decays towards the drain (see Fig. 4.6), Sδi2n for thermal noise
will have opposite behavior, peaking at the drain end. Note that Fig. 4.5 plots inversion charge
normalized to inversion charge at the source end. Inversion charge is an exponential and liner
function of the threshold voltage in weak inversion and strong inversion, respectively. There-
fore, the ratio is higher in weak inversion as compared to strong inversion, as seen in the figure.
4.4 Results and Discussion 68

Normalized Inv. Charge

Normalized Inv. Charge
q (x) / q (x=0) at V = 0.1V 2.4
i i G

q (x) / q (x=0) at V = 0.6V

180 i i G

2.0

120

1.6

60

1.2

0
0.0 0.5 1.0

x/L

Figure 4.5: Inversion charge density (normalized to inversion charge density at the source) along the
channel for Vg = 0.1V (weak inversion) and 0.6V (strong inversion) at VDS =50mV. Due to the lateral
non uniform doping, inversion charge is a function of channel position, and increases from source to
drain as the doping on the source side is highest. L=2µm, W=1µm.

Now consider the fact that KP method treats impedance field at every point in the channel
to be a constant (= L1 ), independent of bias and position, which is certainly not true for non
uniform channel devices. Fig. 4.6 shows the variation of the IF (normalized to channel length L)
and PSD of local noise source at VDS = 50mV and two gate voltages Vg =0.1V and Vg =0.6V
along the channel. It is clearly seen that the IF also peaks at the source, and decreases towards
the drain. Therefore, not only the part of the channel near the source will actually contribute
towards the overall noise, but its contribution is higher than what is predicted by classical KP
method since normalized IF is higher than 1 as shown in Fig. 4.6. Thus KP method wrongly
deflate the contribution of the source side region, thereby underestimating overall 1/f noise.
In case of thermal noise, Sδi2n peaks near the drain end where IF is negligible, making their
effective product frivolous. However, assigning IF (norm)=1 by the KP method only leads to
overestimation of the thermal noise. It is evident from Fig. 4.4 that the underestimation of noise
by KP method is more severe at low gate voltages. This could also be explained from the profile
of normalized IF and Sδi2n in Fig. 4.6. While in Fig. 4.6(a), normalized IF is much higher than 1,
it is not only more uniformly distributed along the channel, but also remains close to 1 i.e. close
to the value of IF for the uniform channel case in Fig. 4.6(b), and hence discrepancy between
the KP and numerical method is more in weak inversion than in strong inversion.
4.4 Results and Discussion 69

1.0 150

n
i
Weak Inversion

Normalized IF
Normalized S 0.8
Normalized Impedance Field

Normalized PSD of LNS

100
0.6

V = 0.1V
G
0.4
50

0.2

0.0 0
0.0 0.5 1.0

x/L
(a)
2

n
i

Normalized IF
Strong Inversion
1.0 3
Normalized S

Normalized Impedance Field

Normalized PSD of LNS

0.8
2
V = 0.6V
G

0.6
1

0.4

0
0.0 0.5 1.0

x/L
(b)

Figure 4.6: Impedance field (normalized to L1 ) and PSD of local noise source (normalized to PSD at
the source) vs channel position at VDS = 50mV for (a) VG =0.1V, and (b) VG =0.6V. Both IF and
Sδi2n peaks at the source end, making the effective contribution of the part of the channel near the source
towards overall noise more prominent than rest of the channel. For high gate voltage as in (b), IF is
not only more uniformly distributed along the channel, but also remains close to 1 i.e. close to IF for
uniformly doped MOSFETs, thereby less discrepancy between KP and numerical simulation is observed
in Fig. 4.4. L=2µm, W=1µm.
4.4 Results and Discussion 70

18
10

)
-3
Doping (cm

17
10
Doping Profile 3

Doping Profile 2

Doping Profile 1

16
10
0.0 0.5 1.0

x/L
(a)

-21 Doping Profile 3

10
Doping Profile 2

Doping Profile 1
(A /Hz)

-22
10
2

-19
-23 10 V =1V
10
(A /Hz)

DS

-21
10
ID

ID
S

-23
S

10
-24
10 -25
10 -3 -2 -1 0 1 2 3
10 10 10 10 10 10 10
V =50mV
DS Drain Current ( A)

-25
10
-2 -1 0 1
10 10 10 10

Drain Current ( A)
(b)

Figure 4.7: Impact of different doping profile on flicker noise: (a) Three different doping profiles (b)
Flicker noise power spectral density at VDS = 50mV for VG swept from 0V to 1V. To achieve the same
current level, device 1 needs minimum gate voltage as its threshold voltage is minimum. Since source
side doping is same for all, device 1 has minimum inversion charge density at the source end (at same
current level) among the three devices, and hence highest PSD of local noise source (see 4.12) in weak
inversion. In strong inversion, all three devices have similar inversion charge density due to formation of
inversion layer, and hence the noise characteristics is also relatively same. Note that device with doping
profile 1 depicts significant bias dependency, similar to the noise behavior observed in [30, 31]. Inset
figure in (b) plots SID in the saturation region. L=2µm, W=1µm.
4.5 Summary 71

We have also studied the impact of channel doping profile on the noise. Three doping pro-
file were simulated with source doping of 1018 cm−3 and different drain side doping as shown
in the Fig. 4.7(a). The device with doping profile 1 (device 1) has the highest non uniformity
compared to the other two. Since threshold voltage of these devices is different, we have plotted
noise spectral density vs drain current instead of gate voltage in Fig. 4.7(b). It can be observed
that in weak inversion, device 1 has highest noise. This can be explained as follows: in weak in-
version the overall noise is dominated by the noise in the region of channel close to the source.
Among the three devices, device 1 has the lowest threshold voltage as the average doping is
minimum. Now, since the source side doping is same, the inversion charge density at the source
end would be same if the equal gate voltages are applied. Fig. 4.7(b) compares the noise at same
current level, which is achieved at lower gate voltage for device 1, and higher gate voltage for
device 3. Thus, inversion charge density at source end in device 1 is minimum among the three
devices, leading to higher PSD of local noise source (see (4.12)) and hence higher total noise in
Fig. 4.7(b). In strong inversion, inversion charge density is almost same in all the devices due to
the formation of the inversion layer, and hence the noise curves are closer in strong inversion.
It is to be noted that the device 1 shows very different bias dependency in Fig. 4.7(b) which is
not typically observed in uniformly doped devices. Such behavior is also observed in real de-
vices with halo implants [30, 31]. Inset of Fig. 4.7(b) shows noise spectral density in saturation
region. Flicker noise in saturation is much higher than that in linear region as it is proportional
to the square of the drain current.

This study of flicker noise in NUDC device can be linked to the observed degradation of
low frequency noise in halo implanted MOSFETs in [14, 30, 31]. Furthermore, in [13], it was
shown that the noise in weak inversion is severely underestimated by the unified flicker noise
model, which is similar to the trend we have observed in this study.

4.5 Summary
In this chapter, flicker noise behavior of a non-uniformly doped channel MOSFET is studied,
and it is demonstrated that classical KP method underestimates flicker noise in NUDC devices.
The same KP method has been shown in literature to overestimate thermal noise. The reason
for such difference in flicker and thermal noise trend lies in the fact that the PSD of local noise
source for thermal noise peaks at drain side, while for flicker, it peaks at source side. The
observed discrepancy between KP method and numerical simulation is significant at low gate
voltages, which is consistent with the noise degradation observed in the real device measure-
ments reported in the literature. In the next chapter, we will utilize this observation that the
4.5 Summary 72

source side contribution is significant in weak inversion, to develop a compact model of 1/f
noise for the halo implanted devices.
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Chapter 5

Compact Modeling of Flicker Noise in

Halo Implanted Devices

5.1 Introduction
Fig. 5.1 shows the measured median drain current (ID ) flicker (1/f) noise power spectral density
(SID ) normalized to channel width for long and short channel devices in 45nm low power
CMOS technology node [1]. Each point in this plot is the median of 21 samples (same device
from different dies) to take care of statistical variation across dies. Several observation can be
drawn from the figure: (a) the strong pocket devices show no impact of channel length scaling
for 1/f noise in the subthreshold or near-threshold-voltage region. This is an important factor
that needs to be understood since analog designs are targeting low power regions of operation (b)
as the drain current is increased by increasing the gate voltage, the long channel device further
show anomalous bias dependence through a sudden decrease in slope. The short channel device
does not show this characteristic. Such behavior is specific to the devices with doping non-
uniformity, and cannot be captured by existing noise models based on uniformly doped channel
devices [2]. To illustrate this, unified compact model presented in [3], which has been widely
used in commercial industry standard bulk MOSFET models [4–6]), is used to simulate 1/f
noise for the long channel length device and result are shown by the dotted lines in the Fig. 5.1.
Although, a noise model specific to the halo devices was earlier proposed by Wu et. al. [7]
based on a non-uniform threshold voltage distribution using the unified noise model, it adds the
noise contributions from the different regions with equal proportions. Such formulation might
lead, in certain cases, to excess contribution of noise from the pocket part in strong inversion,
or excess contribution from channel part for lower bias. Also it does not account for higher
trap densities (in halo regions) on noise typical to pocket implant process, and is valid only in
strong inversion. Here, we will discuss the physical mechanisms behind the bias dependence

76
5.2 Flicker Noise Behavior 77

-16

S /W (A /Hz/ m)
10

-18
10
2

-20
10
ID

-22
10 Measurement Short L

Measurement Long L

K. K. Hung Model
-24
10
-2 -1 0 1 2 3
10 10 10 10 10 10

I /W ( A/ m)
D

Figure 5.1: Drain current flicker noise power spectral density vs drain current at VDS = 0.55V , both
normalized to channel width. Measurements are from the same technology as in [1] and show complex
dependency on gate voltage, especially for long channel device. In weak inversion, there is no impact of
length scaling on 1/f noise. Dotted lines show unified model [3] result for the long channel device, and
it is clearly seen that it cannot model the noise characteristics of the Halo devices.

for halo implanted devices and present an analytical model, valid from weak inversion (WI) to
strong inversion (SI), that can capture the 1/f noise behavior considering the impact of both non-
uniform threshold voltage and higher trap density. The model is compatible with the BSIM6
MOS model, which is the latest industry standard compact model of bulk MOSFET.

5.2 Flicker Noise Behavior

We study 1/f noise in the presence of halo implants using Sentaurus TCAD [8]. The device used
in this study has gate oxide thickness Tox = 4nm, channel doping NCH =5X1017 /cm3 , channel
length L=2µm and width W=1µm. The device is simulated with different doping levels and
length of the halo region (NH and LH , respectively). Four kind of devices are explored- source
side halo (SH), drain side halo (DH), both side halo (Halo) and uniformly doped device (UD).
Fig. 5.2 compares SID vs ID of the Halo and the UD device for various doping conditions at
VDS =2V. Halo device shows significant departure from the conventional UD behavior at small
current levels (typically for VGS < VT H ), however in strong inversion it asymptotically follows
UD. Furthermore, at higher doping levels of the halo region, SID has non-monotonic trend as
5.2 Flicker Noise Behavior 78

Solid Lines : Halo

V =0 to 2V
GS
Dotted Line : UD
-19 V =2V
10

/Hz)
DS

18 18 3
N =10 - 2X10 /cm
H
NMOS
2

-22
(A

10
ID

17 3
UD: N =5X10 /cm
S

CH

-25
10 Halo: N
CH
=5X10
17
/cm
3

18 18 3
N =10 - 2X10 /cm
H

L=2 m W=1 m
-28
10
-12 -10 -8 -6 -4
10 10 10 10 10

Drain Current (A)

Figure 5.2: Comparison of SID vs drain current of UD and Halo for different doping conditions at VDS =
2V . In weak inversion, SID of the Halo device is significantly higher than that of UD. In strong inversion,
all have same SID . As doping of the halo region increases, non-monotonicity is observed. Such behavior
is also observed in the real device measurements [9], and therefore establishes the qualitative correctness
of the TCAD simulation environment. L=2µm and W=1µm.

V =2V
TCAD Simulations V =0 to 2V DS
GS

-19
10
/Hz)

L=2 m W=1 m
2

-22
(A

UD
10
SH
ID

Halo
NMOS
S

DH
-25
10 17 3
N = 5X10 /cm
CH

18 3
N = 1.3X10 /cm
H

-28
10
-12 -10 -8 -6 -4 -2
10 10 10 10 10 10

Drain Current (A)

Figure 5.3: Comparison of SID vs drain current of UD, SH, DH and Halo at VDS = 2V .
NCH =5X1017 /cm3 and NH =1.3X1018 /cm3 . Since DH does not depicts unconventional bias dependency,
it can be inferred that drain side halo region has little impact on overall noise behavior of Halo devices.
L=2µm and W=1µm.
5.3 Model Formulation 79

it initially increases, then decreases and again increases with ID . These TCAD results are in
qualitative agreement with the real device measurements reported in [9]. To investigate the in-
dividual effect of source and drain side halo regions, SID vs ID of SH, DH, Halo and UD at
VDS = 2V are plotted in Fig. 5.3. At a given current level, SID of the Halo and SH is signif-
icantly higher than that of UD in weak inversion. Characteristics of SH and Halo are similar
and interestingly, DH does not show the unconventional bias dependency. From these results, it
can be inferred that the anomalous behavior observed in Halo devices is due to the source side
halo region and drain side halo region has little role to play in saturation. This is a key feature
to understand, since traditionally source side halo region is overlooked while modeling Halo
devices. We offer our understanding of this effect, which is as follows: equivalent conductance
of the MOSFET with halo implants can be expressed as [10],

1 1 1 1
= + + (5.1)
Geq Geq |SH Geq |CH Geq |DH

Geq |SH , Geq |DH and Geq |CH represent equivalent conductances of the source side halo, drain
side halo, and channel region, respectively, and is proportional to the ratio of inversion charge
density and length of the region. In saturation, drain side barrier (between lightly doped chan-
nel and drain side pocket region) is lowered due to high drain voltage, which increases effective
conductance (as it has exponential dependence on surface potential in weak inversion) of the
drain side halo region. For Lch >> Lh , Geq ≈ Geq |SH from (5.1), and thus overall conduc-
tion in the device is limited by the source side halo region. Since overall noise is a function of
equivalent conductance (or resistance) of each region [11], the drain side halo region does not
contribute significantly in overall noise performance. At low VDS operations, Geq |DH ≈ Geq |SH
and one can write Geq |SH,ef f ≈ 0.5 ∗ Geq |SH . Therefore, by parametrizing Geq |SH and neglect-
ing Geq |DH (thereby reducing computational time), it is possible to accurately model noise
behavior both in linear and saturation region of operation.

5.3 Model Formulation

Starting with the earlier Langevin method for noise modeling, there exist other approaches like
equivalent circuit method, impedance field method, Klaassen Prin (KP) approach, etc. [12–14].
The presented formulation is based on small signal approach, which is similar to the impedance
field method. Halo doped devices, in principle, can be modeled by three transistor equivalent
sub-circuit, each representing source/drain halo region and channel region. This creates two
extra nodes in the circuit, which increases matrix size thereby increasing computer simulation
5.3 Model Formulation 80

(a) (b)

Figure 5.4: Representation of halo implanted MOSFET for noise modeling: (a) Channel length L can
be divided into two parts- the halo region of length Lh with doping Nh and the channel region of length
L-Lh with doping Nch (b) equivalent circuit representation. Source side electrostatics is captured by the
high threshold voltage transistor of length L = Lh .

time. This can be detrimental since convergence time may be even larger for multi transistor
simulations. To arrive at analytical solution, consider that the drain side halo region does not
contribute significantly in the overall noise properties. Similar observations are also drawn
from the NUDC device 1/f noise characteristics discussed in the previous chapter. Therefore,
we propose to use equivalent representation as shown in Fig. 5.4 for 1/f noise modeling (not
IV and CV). Here the total length L is segmented into two parts: a region of higher doping
of length Lh with equivalent resistance Rh , noise PSD SID,h and another low doped region of
length L-Lh with resistance Rch and noise PSD SID,ch . Fig. 5.4(b) shows the equivalent circuit
representation of the Fig. 5.4(a). We will shortly see that this allows us to develop closed form
model of 1/f noise.

Firstly, the I-V parameters of the family of devices under test are extracted. For the noise
modeling, it is now assumed that the transistor is composed of two transistors, channel transistor
of length L-Lh and halo transistor of length Lh connected in series and carries same current
as in single transistor configuration. The individual contribution of the halo and the channel
transistors to overall noise is obtained using small signal analysis and principle of superposition
as shown in Fig. 5.5. From Fig. 5.5(a), the drain current noise PSD due to halo transistor is
obtained by assuming channel transistor to be noiseless. Using small signal analysis,
5.3 Model Formulation 81

(a) (b)

Figure 5.5: Small signal analysis of two transistor noise circuit. Principle of superposition is used to ob-
tain total noise from individual noise contributions (a) Noisy halo transistor, noiseless channel transistor
(b) Noisy channel transistor, noiseless halo transistor.

gm,ch + gd,ch
In1 ' In,h (5.2)
gm,ch + gd,ch + gd,h
" #2
gm,ch + gd,ch
SID,1 = SID,h (5.3)
gm,ch + gd,ch + gd,h

where gm,ch , gd,ch are the transconductance and output conductance of the channel transistor
and gd,h is the transconductance of the halo transistor. Similarly from Fig. 5.5(b), the noise PSD
due to the channel transistor is expressed as,
gd,h
In2 ' In,ch (5.4)
gm,ch + gd,ch + gd,h
" #2
gd,h
SID,2 = SID,ch (5.5)
gm,ch + gd,ch + gd,h

Total drain current noise PSD becomes,

SID = SID,1 + SID,2 (5.6)

" #2 " #2
gm,ch + gd,ch gd,h
= SID,h + SID,ch (5.7)
gm,ch + gd,ch + gd,h gm,ch + gd,ch + gd,h
5.3 Model Formulation 82

SID = SID,h .CFh + SID,ch .CFch (5.8)

We refer to the multiplying factors to SID,h and SID,ch in (5.7) as contribution factors (CF).
From [15],

W
gd,ch = 2nq µCox Vt qd,ch (5.9)
L − Lh
W
gd,h = 2nq µCox Vt qd,h (5.10)
Lh
W
gm,ch = 2µCox Vt (qs,ch − qd,ch ) (5.11)
L − Lh

where nq , µ, Cox , and Vt are the slope factor, effective mobility, oxide capacitance per unit
area and thermal voltage respectively. Note that all these quantities are already extracted during
CV and IV extraction. qs,ch , qd,ch , qs,h and qd,h are the normalized inversion charge densities
at the source and drain ends of the channel and the halo transistor, respectively. qsh and qd,ch
are obtained from analytical solution of the BSIM6 [16] charge equation given by (5.12), where
pinch-off potential (ψp , normalized to the thermal voltage Vt ) is given by (5.13) and is calculated
independently for the two transistors using source potential vch = vs and vch = vd , respectively.

 
2nq 2nq p
ln (qi ) + ln (qi + 2 ψp − 2qi ) + 2qi = ψp − 2φf − vch (5.12)
γ γ
   2 
vg −vf b −ψp0
− ln 1 − ψp0 + if vg − vf b < 0


γ
ψp =  q
2
 2 (5.13)
1 − e−ψp0 + vg − vf b − 1 + e−ψp0 + γ2 − γ2 otherwise



Here vg , vf b , φf and γ are the normalized gate voltage, flat band voltage, bulk potential and
body factor, respectively and ψp0 is approximation of the pinch-off potential when it is close to
zero.
Now it is remaining to calculate qd,h and qs,ch . For this, current continuity between the two
transistors in the sub-circuit is used. In BSIM6, drain current can be expressed as a function of
inversion charge densities at the source and the drain ends which gives,

IDS 2 2
ih = = (qs,h + qs,h ) − (qd,h + qd,h ) (5.14)
2nq µCox LWh Vt2
IDS 2 2
ich = W 2
= (qs,ch + qs,ch ) − (qd,ch + qd,ch ) (5.15)
2nq µCox L−L V
h t
5.4 The Noise Source 83

where ih and ich are the normalized drain current of halo and channel transistor respectively.
Since drain current is already known from the DC fitting, one can write,

1 1q 2
qd,h = − + 1 + 4(qs,h + qs,h − ih ) (5.16)
2 2
1 1q 2
qs,ch = − + 1 + 4(qd,ch + qd,ch + ich ) (5.17)
2 2
Thus, the inversion charge densities at the end point of the halo and channel region are explicitly
known.

5.4 The Noise Source

The source of flicker noise in MOSFETs is attributed to mobility fluctuation and/or carrier
number fluctuation [17–19]. There exist popular models which unify the two approaches [2,
3, 20]. Here we have used the unified model presented in [3] (which has been widely used
in industry standard bulk MOSFET models [4–6]) for halo and channel transistors separately,
where SID is expressed as

2 Z Lh ∗
kT IDS Nt,h (EFn )
SID,h = dx (5.18)
γf W L2h 0 Nh2
2 Z L ∗
kT IDS Nt,ch (EFn )
SID,ch = 2 2
dx (5.19)
γf W (L − Lh ) Lh Nch

∗ 2
where apparent trap density Nt,ch(h) (EFn ) = Ach(h) + Bch(h) Nch(h) + Cch(h) Nch(h) , A, B, C are
the noise parameters, γ is the tunneling parameter, k is the Boltzmann constant and T is the
temperature. It is important to note that SID,h and SID,ch are in explicit form since (5.18) and
(5.19) can be expressed as a function of qs,h , qd,h and qs,ch and qd,ch respectively [21].
Also note that SID in the halo region might be locally higher than in the channel region due
to increased trap density which is captured by the noise parameters of the halo transistor. Hence
formulation of SID is based on the local trap density, inversion charge densities specific to the
region that generates the noise as well as the length of the region. Using (5.18) and (5.19), and
substituting (5.16), (5.17), qs,h , qd,ch in (5.7) gives the overall PSD.

5.5 Results and Discussion

The model is validated with the experimental data of the devices in 45nm CMOS technology.
Fig. 5.6 shows long channel noise PSD along with the halo and channel transistor PSD. Due to
5.5 Results and Discussion 84

-16

S /W (A /Hz/ m)
10 Proposed Model: Long Channel Noise Behavior

-18
2
10 V
DS
=0.55V

-20
10

Measurement
ID

-22
10 Total Noise

Halo Transistor Noise

Channel Transistor Noise

-24
10
-1 0 1 2
10 10 10 10

I /W ( A/ m)
D

Figure 5.6: Model validation with experimental data of long channel device: SID vs ID at VDS = 0.55V.
SID asymptotically follows halo transistor noise in weak inversion and channel transistor noise in strong
inversion. L=1µm.

higher doping, halo transistor has higher threshold voltage than the channel counterpart, which
leads to significantly lower inversion charge density especially at low gate voltages. For a given
current, SID varies inversely with the inversion charge density, and therefore halo transistor has
much higher SID compared to the channel transistor. Furthermore, in WI gd,h << gm,ch (as
qs,ch >> gd,h since halo transistor has higher threshold voltage) leading to

gm,ch + gd,ch gd,h

CFh = '1 CFch = '0 (5.20)
gm,ch + gd,ch + gd,h gm,ch + gd,ch + gd,h

Since the contributed noise is the product of CF and SID , overall noise is dominated by the halo
transistor noise in WI (from (5.8),

SID ' SID,h weak inversion (5.21)

Fig. 5.7 shows CF of the halo and the channel transistor as a function of ID . CFh (CFch ) falls
(rises) rapidly as the region of operation moves from WI to SI, and as a result, the channel tran-
sistor noise becomes the dominant component of the total noise in SI. Consider the behavior of
Impedance Field (IF) in Fig. 4.6 in chapter 4. In Fig. 4.6(a), which shows weak inversion plot,
IF in the source side halo region is much higher than that in the channel region. In Fig. 4.6(b),
IF ≈1, which implies that non-uniform doping has diminishing impact on overall noise as one
5.5 Results and Discussion 85

1.0

Contribution Factor
V =0.55V
DS

CF
0.8 ch

CF
h

0.6

In strong Inversion
0.4
g m ch g d ch
CFh , ,

g m ch g d ch g d h
0

, , ,

0.2 gd h
CFch ,

g m ch g d ch g d h
1

, , ,

0.0
-1 0 1 2
10 10 10 10

I /W ( A/ m)
D

Figure 5.7: Contribution factor of the halo and the channel transistor vs drain current. In weak inversion,
CFh >> CFch , and thus SID is dominated by the noise from the halo region (see (5.8)). On the other
hand, CFh falls rapidly in the strong inversion leading to the negligible contribution from halo region
in SID . The role of CF in this model is similar to that of impedance field [12], which is responsible for
noise propagation from a point in the channel to the drain terminal. Note that [7] adds halo and channel
contribution with equal weights, therefore will overestimate noise in strong inversion.

-16
S /W (A /Hz/ m)

10
Lines: Proposed Model

-18
10
2

-20
10
ID

-22
10 Measurement Short L

Measurement Long L

-24
10
-1 0 1 2 3
10 10 10 10 10

I /W ( A/ m)
D

Figure 5.8: Model validation with experimental data of a short channel device: SID vs IDS at VDS =
0.55V. L=1µm and 120nm.
5.5 Results and Discussion 86

moves from WI to SI. Similar qualitative results are obtained by contribution factors in the pre-
sented model. Fig. 5.8 shows the SID vs drain current for short channel device. It is interesting
to observe that short channel device does not show the bias dependency like the long channel
device. This can be explained by the fact that the length of the halo transistor is comparable with
the length of channel transistor for short channel device, making the transition smoother from
halo dominated region to channel dominated region. The proposed model accurately captures
noise behavior over wide range of biases.

5.5.1 Impact of Halo Region Dose and Length

The noise characteristics of the Halo devices depend strongly on the halo region properties [9,
22, 23], e.g., it is demonstrated in [9] that more the halo dose, higher is the SID . To understand
this behavior, consider CF which can be written in simplified form as

qs,ch qdh
L−LH LH
CFh ≈ qs,ch qdh CFch ≈ qs,ch qdh (5.22)
L−LH
+ LH L−LH
+ LH

L
As resistance of the semiconductor region ∝ qinv , from (5.22) it can be said that CF repre-
sents ratio of the resistance of channel and halo regions and therefore it qualitatively represents
impedance field [12]. Thus CF is a strong function of doping and length of the halo region as
they are closely related with the resistance of the halo region. Intuitively, increasing NH or LH
should have same qualitative impact on SID as both increase resistance of the halo region. This
is indeed correct. Fig. 5.9 shows SID of Halo device for same doping conditions but different
length of the halo regions. Along with Fig. 5.2, it is observed that as the doping or length of the
halo region increases (a) SID in weak inversion increases (b) point where SID makes transition
shifts to higher drain current.
To understand such dependence of transition point on doping and length of the halo region,
consider that as NH or LH increases, resistance of the halo region increases (qd,h reduces)
which translates into higher CFh and lower CFch . The transition occurs when CFh ≈ CFch i.e.
qdh qsch
LH
≈ L−L H
. Assume that the condition CFh = CFch is satisfied at some ID = I0 for a given
NH and LH . Now if NH or LH is increased and correspondingly gate voltage has to be raised to
achieve ID = I0 . This reduces resistance of the channel region as the inversion charge density
in the channel is increased due to high gate voltage. At the same time, resistance of the halo
region is high because of high NH or large LH . This makes CFh > CFch at ID = I0 and thus
requires more gate voltage (and hence ID > I0 ) to achieve CFh = CFch . Hence, the transition
occurs at higher drain current level. The analytical model (see (5.8)) accurately captures the
5.5 Results and Discussion 87

-17
10
Symbols : TCAD Data NMOS
Lines : Model

/Hz) L=2 m W=1 m

-20
10
2

L =LH1
(A

LH1 > LH2

ID

L =LH2
S

H
-23
10
17 3
N =5X10 /cm V =2V
CH DS

18 3
N =10 /cm V =0 to 2V
GS
H

-26
10 -12 -10 -8 -6 -4
10 10 10 10 10

Drain Current (A)

Figure 5.9: SID at same doping conditions but different lengths of halo region. As the length of the halo
region increases, the point where SID makes transition shifts to higher drain current. This is because
resistance of the halo region increases with LH and it therefore requires higher bias to achieve CFh =
CFch . The analytical model (see (5.8)) accounts for LH dependency and therefore accurately models 1/f
noise behavior. VDS =2V. L=2µm and W=1µm.

V =0 to 2V
NMOS GS

-18 V =2V
10 DS
/Hz)

increasing N
H
-22
10
2

18 3 Model Results
N =10 /cm
(A

-26
ID

10 All parameters except N

H
S

kept same
-30
10 N =5X10
17
/cm
3

17 3 CH
N =5X10 /cm
H

L=2 m W=1 m
-34
10
-12 -10 -8 -6 -4
10 10 10 10 10

Drain Current (A)

Figure 5.10: Modeling of SID : SID as obtained from (5.8) with different doping of halo region. The
model shows asymptotically correct behavior since unconventional bias dependency is not seen for
NH = NCH and non-monotonicity is observed at higher NH . VDS =2V. L=2µm and W=1µm.
5.5 Results and Discussion 88

V =50mV L= 0.12 m
DS
-17
10 W= 10 m

/Hz)
High pocket dose
2

-19
10
(A
ID
S

-21
10 L= 1 m Low pocket dose

Symbols : Experimental Data [9]

Line : Model
-23
10
-7 -6 -5 -4 -3
10 10 10 10 10
Drain Current (A)

Figure 5.11: Model validation with experimental data at VDS = 50mV [9]. Unlike at long channel
lengths, short channel length device does not show significant bias dependency in SID . Short channel
length device behaves similar to uniformly doped device as the halo regions from both the ends merge
together. The compact model is able to accurately model SID in linear region as well, both for long and
short channel length devices. VDS =50mV.

halo region electrostatics and therefore excellent matching with the TCAD data is obtained at
different LH in Fig. 5.9. The model also shows asymptotically correct behavior for different
NH in Fig. 5.10. The proposed model is also successfully validated with the experimental data
at different conditions of halo dose and channel lengths [9] in Fig. 5.11. It can be noticed that
like in Fig. 5.8, data in Fig. 5.11, which is from [9], do not show peculiar bias dependence for
the short length devices. This behavior can be further understood well from the Fig. 5.12 which
shows the model noise simulation results for gate length=30nm and halo region length=28nm.
The new model result is represented by the open symbols. The figure also shows old model
result for two different values of the noise parameter NOIA. In general, NOIA<NOIA2 (since
traps without halo implantation are lesser than traps with halo), which is shown by the red line.
For the case of NOIA=NOIA2, the new and old model overlaps. From this, it can be inferred
that at very short gate lengths, the new model behaves like old model, which is correct in the
sense that the device is uniformly doped. Important point to note here is that in order to achieve
same result as that of new model, the value of the noise parameter NOIA has to be increased.
This is due to the fact that although the device is behaving like a uniform device, but it has
higher trap density
5.6 Summary 89

New 1/f model

-15 Old model with NOIA<NOIA2
10
Old model with NOIA=NOIA2

/Hz) -21
10 Model Simulation Results
2
(A
ID

-27
10
S

V =50mV, V is swept
DS g

-33
10 Gate Length = 30nm

Halo Region Length=28nm

-11 -7 -3 1
10 10 10 10
I ( A)
D

Figure 5.12: 1/f noise model results at short gate length. Gate length=30nm, halo region length=28nm.
For such short lengths, transistor behaves like a uniformly doped device, but have higher trap density
throughout the channel due to the halo implantation process. The old model also gives similar results but
one has to use higher value of the noise parameters. VDS =50mV.

The model behaviour with different drain voltage is also studied. Fig. 5.13 shows the drain
current noise PSD vs drain current for two gate voltages, VGS = 1V (strong inversion) in
Fig. 5.13(a) and VGS = 0.25V (weak inversion) in Fig. 5.13(b), and varying drain voltage. For
the entire drain bias range (0.1V to 1.0V), total noise is mainly due to the channel transistor
noise in Fig. 5.13(a). This could be understood as follows: high gate voltage strongly inverts
both channel and halo regions, however channel region offers higher resistance due to its larger
length (as compared to halo region length) leading to CFch >> CFh and hence SID,ch >>
SID,h from (5.8). Similarly for the low gate voltages, total noise is dominated by the noise of
the halo region as seen in Fig. 5.13(b), since resistance of the halo region is much higher than
the resistance of the channel region due to its high threshold voltage. The compact model is
able to accurately model SID in linear region as well, both for long and short channel length
devices.

5.6 Summary
Flicker noise behavior of a non uniformly doped channel MOSFET is studied, and it is demon-
strated that classical KP method underestimates flicker noise in NUD devices. The same KP
5.6 Summary 90

-20
10

m)
V = 0.25V
GS
/W (A /Hz/
Weak Inversion V : 0.1V to 1.0V
DS

-21
10
2

Halo Transistor Noise

Channel Transistor Noise

Total Noise
ID

-22
S

10

250 260 270 280

I (nA/ m)
D

(a)

-16
m)

10 Strong Inversion
/W (A /Hz/

V = 1.0V
-17 GS

10 V : 0.1V to 1.0V
DS
2

-18 Halo Transistor Noise

10 Channel Transistor Noise

Total Noise

-19
10
ID
S

-20
10
20 30 40 50 60 70 80 90
I /W ( A/ m)
D

(b)

Figure 5.13: Simulated drain current noise spectral density vs drain current for constant gate voltage and
varying VDS from 0.1V to 1.0V for the long channel device: (a) VGS = 1.0V (b) VGS = 0.25V . In (a),
high gate voltage strongly inverts both the halo and channel regions. However, resistance of the channel
region is larger as its length is large compared to the halo region, as a result total noise is dominated by
the channel region noise. In (b), halo region offers much higher resistance than the channel part due to
its high threshold voltage and hence the total noise is determined by the noise of the halo transistor.
5.6 Summary 91

method has been shown in literature to overestimate thermal noise. The reason for such dif-
ference in flicker and thermal noise trend lies in the fact that the local noise source PSD for
thermal noise peaks at drain side while for flicker it peaks at source side. The observed discrep-
ancy between KP method and numerical simulation is significant at low gate voltages, which
is consistent with the noise degradation observed in the measurements data of halo implanted
MOSFETs available in the literature.
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C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad, and C. Hu, “Recent en-
hancements in BSIM6 bulk MOSFET model,” in Simulation of Semiconductor Processes
and Devices (SISPAD), International Conference on, Sept 2013.

[17] A. L. McWhorter, “1/f Noise and Germanium Durface Properties,” Semiconductor Surface
Physics, 1957.

[18] F. N. Hooge, “1/f Noise is No Surface Effect,” Phys. Lett., vol. 29A, no. 3, pp. 139–140,
1969.

[19] R. Jindal, “Compact Noise Models for MOSFETs,” IEEE Transactions on Electron De-
vices, vol. 53, no. 9, pp. 2051–2061, 2006.

[20] R. Jayaraman and C. Sodini, “A 1/f Noise Technique to Extract the Oxide Trap Density
Near the Conduction Band Edge of Silicon,” IEEE Transactions on Electron Devices,
vol. 36, no. 9, pp. 1773–1782, 1989.

[21] H. Agarwal, C. Gupta, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, S. Salahuddin, and

C. Hu, “BSIM6 Technical Manual,” 2015. [Online]. Available: http://bsim.berkeley.edu/
models/bsimbulk/

[22] A. K. M. Ahsan and S. Ahmed, “Degradation of 1/f Noise in Short Channel MOSFETs
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[23] K. Narasimhulu, I. V. Setty, and V. R. Rao, “The Effect of Single-Halo Doping on the
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Chapter 6

Compact Modeling of Threshold Voltage

of MOSFETs

6.1 Introduction

Threshold voltage is an important device parameter from modeling and circuit point of view,
considering the fact that low power technologies are targeting the sub-threshold design. It is
generally regarded as the signature of the technology, and governs transition from weak inver-
sion to strong inversion. Earlier generation MOSFET models, like BSIM3, BSIM4 etc., were
based on the concept of threshold voltage. Although the state of the art modeling approaches
(surface potential/charge based modeling) [1–4] do not endorse threshold voltage based method-
ologies, the fundamental physics essentially remains the same and still threshold voltage char-
acterizes the technology. Classically, the threshold voltage is defined as the gate voltage at
which the surface potential is 2φf , where φf is the bulk fermi potential [5]. However, one can-
not measure the surface potential to calculate threshold voltage, but it has to be extracted. There
are several methods proposed in literature to extract threshold voltage [6–10].
In this chapter, we develop an analytical model of threshold voltage for BSIM6 bulk MOSFET
model, which can be used for operating point information in SPICE engines. Being a charge
based model, BSIM6 does not use threshold voltage formulation. However, it is necessary to
know threshold voltage of the transistor because circuit design designers require it to bias the
circuit in appropriate region of operation, e.g. analog designer use it to bias the transistor in
saturation region and digital designer needs it to determine on current. We also briefly review
some of the threshold voltage extraction techniques, and validate the proposed model with them.

94
6.2 Threshold Voltage Extraction Methods 95

6.2 Threshold Voltage Extraction Methods

6.2.1 Extrapolation in Linear Region (ELR) Method

This is the popular and widely used method of MOSFET characterization [6]. Drain current at
small VDS can be expressed in the following form

W
IDS = µCox VDS (VGS − VT ) (6.1)
L
For a given VDS , (6.1) predicts constant gm . However due to subthreshold conduction and
mobility degradation, gm of a real device exhibits a peak and decreases at higher vertical field.
The ID -VG curve is linearly extrapolated from the point of maximum gm , and threshold voltage
is given by its VG intercept. For the saturation region, threshold voltage is extracted from the
√
VG intercept of linearly extrapolated ID -VG curve, and the method is called as extrapolation
in saturation region (ESR).

gm
6.2.2 Id Method
This method defines threshold voltage as the gate voltage at which drift and diffusion compo-
nents of the drain current are equal. Transconductance to current ratio in charge based formal-
ism is given as [11]

gm 1 1 gm 1
= = |max (6.2)
Id nq Vt 1 + qs + qd Id 1 + qs + qd

Here qs and qd are the normalized inversion charge density at source and drain ends, respectively
and nq is the charge linearization factor (or slope factor). We will see in next section that the
condition of equal drift and diffusion current leads to qs = 0.5. In linear region, qd = qs =
0.5, giving gImd = 0.5 gImd |max . Threshold voltage is thus extracted from gImd vs gate voltage
characteristics as a gate voltage corresponding to gImd = 0.5 gImd |max [7].

6.2.3 Second Derivative (SD) Method

Also known as Transconductance Change (TC) method, it defines threshold voltage as the gate
voltage corresponding to maximum slope of gm -VG characteristics i.e. maximum of second
2
derivative ddVI2d [8]. It could be understood as follows : drain current varies exponentially with
g
2
gate bias in weak inversion, while it is linear in strong inversion region leading ddVI2d to maximize
g
at threshold voltage. Threshold voltage in the saturation region is obtained from maximum slope
6.3 Threshold Voltage Model 96
√
d2 Id
of dVg2
.

6.2.4 Second Derivative Logarithmic Method

In this method, threshold voltage is defined as the gate voltage where the double derivative of
the logarithm of the drain current w.r.t. VG is minimum [12].

6.2.5 Constant Current (CC) Method

Owing to its simplicity, it is one of the most popular methods of threshold voltage extraction.
In this method, gate voltage corresponding to an arbitrary drain current given by ICC = W .I
L 0
is defined as the threshold voltage. Here L, W are the effective channel length and width,
respectively and I0 is a constant current level chosen arbitrarily [10].

6.3 Threshold Voltage Model

6.3.1 Long Channel Threshold Voltage

The drain current under the standard drift-diffusion formalism can be represented as [13],

Ids =Idrif t + Idif f (6.3)

dψs dQi
Ids = − W.Qi · µ + W · µ · Vt (6.4)
dx dx
where W , µ, Qi and ψs represents channel width, mobility, inversion charge density and surface
potential respectively. Defining threshold voltage as the gate voltage at which the drift and
diffusion component of the drain current are equal (proposed by [14]),

Idrif t = Idif f (6.5)

From (6.4) and (6.5),

dψs dQi
−W.Qi · µ = W · µ · Vt . (6.6)
dx dx
W.Qi · µ dQi dQi
− = W · µ · Vt . (6.7)
nq .Cox dx dx
6.3 Threshold Voltage Model 97

Solve for
φb Pinch-off vg , vf b
Potential ψp

Solve for
vs vd
qs and qd

Nodal Drain
Charges Current

Figure 6.1: BSIM6: Solution of the Core Model [15]. Here, we adapt approach Idrif t = Idif f as it can
lead to explicit solution for threshold voltage.

where charge linearization [4],

Qi
ψs = ψp + (6.8)
nq .Cox

has been used in deriving (6.7) from (6.6). ψp and nq in above equation are pinch-off potential
and charge linearization factor. Normalizing the inversion charge density to −2nq Cox Vt leads
to,

1
qi = (6.9)
2
Since inversion charge density varies along the channel from source to drain, depending on
channel potential, it is necessary to choose a point in the channel with reference to which
threshold voltage can be defined. Here, we define threshold voltage as the gate voltage at which
normalized inversion charge density at the source is given by

1
qs = (6.10)
2

In BSIM6, pinch-off potential is first calculated from gate voltage, followed by inversion
charge densities at source and drain ends as shown in Fig. 6.1. Since qs is known at threshold
voltage, the steps of Fig. 6.1 are followed in reverse order. First of all, pinch-off potential
corresponding to qs = 12 , ψp,th , is calculated using the general relationship among qi , pinch off
6.3 Threshold Voltage Model 98

potential (ψp ) and channel potential (vch ), which is given as [4]

 
2nq 2nq p
ln (qi ) + ln (qi + 2 ψp − 2qi ) +2qi = ψp − 2φf − vch (6.11)
γ0 γ0

where the terms have their usual meanings. At the source side, the above equation becomes-
 
2nq 2nq p
ln (qs ) + ln (qs + 2 ψp − 2qs ) +2qs = ψp − 2φf − vs (6.12)
γ0 γ0

Using (6.10) in (6.12),

" #  
2nq nq p
ψp,th = ln (0.5) + 1 + ln ( + 2 ψp,th − 1) + 2φf + vs (6.13)
γ0 γ0

To obtain ψp,th in explicit form, we make a simplifying assumption that at threshold voltage,

ψp,th − 1 = 2φf + vs (6.14)

The reason behind this assumption can be understand as follows. Classically, at threshold,
ψS = 2φf + Vs and Qi = 0. Since pinch-off potential is nothing but surface potential at Qi = 0,
(6.14) can be used to approximate pinch-off potential at threshold. The other bias dependent
term nq is also approximated by
γ
nq = 1 + p (6.15)
2 2φf + vs

This gives,
" #  
2nq nq p
ψp,th = ln (0.5) + 1 + ln ( + 2 2φf + vs ) + 2φf + vs (6.16)
γ0 γ0

Fig. 6.2 shows comparison of pinch-off potential at qs = 12 obtained numerically from

(6.13) and ψp,th (obtained from (6.16)). The source voltage is swept from 0.5V to -1V. The
error in ψp,th remains less than 1% for the given body bias range which is fairly good in terms
of accuracy. After ψp,th is obtained, next step is to calculate threshold voltage. The potential
balance equation in conjunction with Poisson’s equation and Gauss’s law for the MOSFET is
6.3 Threshold Voltage Model 99

80 0.6

Numerical Method
70
Pinch-off Potential p,th

60 error 0.4

error(%)
50

40
0.2

30

20
0.0
-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

V (V)
s

Figure 6.2: Comparison of ψp,th (pinch-off potential at qs =0.5) with numerical solution. The source
voltage is swept from -0.5V to 1V. The error resulting from approximation in (6.16) is less than 1%,
leading to compact, yet accurate expression of pinch-off potential at threshold condition.
given as [13],

Qin + Qdep
VG = VF B + ψS − (6.17)
Cox

where VF B is the flat band voltage. At pinch-off, ψS = ψP , and Qin = 0 [11], which gives
p
VG = VF B + ψP + γ ψP (6.18)

Thus we get final expression for long channel threshold voltage as

p
Vth,long = VF B + ψp,th .Vt − γ ψp,th .Vt (6.19)

6.3.2 Short Channel Threshold Voltage

Threshold voltage in short channel devices is affected by drain voltage, popularly known as
drain induced barrier lowering (DIBL). Apart from DIBL, vertical non uniform doping (VNUD),
Drain Induced Threshold Shift (DITS) also change threshold voltage. The compact models for
threshold voltage shift were originally developed for BSIM3 and BSIM4 [16–18], and had
gained popularity and wide acceptance in the device community. BSIM6 makes use of these
models, with modification required for charge based formalism [11]. The effective threshold
6.4 Model Validation with Experimental Data 100

voltage for short channel devices is obtained as follows-

Vth = Vth,long − ∆Vth,DIBL − ∆Vth,V N U D − ∆Vth,DIT S (6.20)

6.4 Model Validation with Experimental Data

The threshold voltage model is validated with IBM 90nm CMOS technology measurements
for channel length varying from 2µm to 70nm. We first extract DC modelcard for the set of
devices under test, thereby fixing the parameter values in (6.20). Drain voltage for linear region
operation is 50mV and for saturation region is VDD , which is greater than 1V. To validate the
model capability to capture threshold voltage across lengths, Fig. 6.3(a) shows the threshold
voltage vs channel length, where channel length is varied from 2µm to 70nm at Vds = 50mV
and Vb = 0V . Inset figure in Fig. 6.3(a) shows the threshold voltage vs body bias in linear
region (Vds = 50mV ) for the long channel device (L=2µm). The model is able to reproduce
experimentally observed threshold voltage roll-up in Fig. 6.3(a), and is in agreement with the
threshold voltage extracted from different extraction methods, especially with the popularly
used constant current method.
Fig. 6.3(b) shows threshold voltage extracted in saturation region vs channel length at Vds =
VDD and Vb = 0V . Fig. 6.3(c) shows threshold voltage vs body bias for the short channel device
(L = 70nm) biased in linear and saturation regions. The model accurately captures the drain
and body bias effect on threshold voltage for short channel transistors. Fig. 6.3 also compares
threshold voltage extracted from classical method (Qi = 0) obtained using ψs = 2φf + vs . As
observed in the Fig. 6.3, threshold voltage thus obtained is typically 50mV-100mV (2-4Vt at
room temperature) below the threshold voltage extracted from other techniques. The proposed
model, which is based on physical charge based core of BSIM6, allows to model threshold
voltage in analytical form and its results are in close agreement with the extracted threshold
voltage from different methods.

6.5 Summary
A new formulation of threshold voltage in BSIM6 model is presented. The model accounts
for real device effects and utilizes charge based core of BSIM6 compact model. The model
captures threshold voltage across lengths, drain and body biases, and shows excellent matching
with the experimental data.
6.5 Summary 101

Measured Data 300 Measured

Our Model V =50mV 280
400 gm/Id
DS V
DS
=V
DD Our Model
SD
(mV) SD
SDL 200
ELR

CC
240 SDL
th

ESR
V

300
2 +V
100
f sb

L=2 m
200
CC

V (mV)
V (mV)

-1.00 -0.75 -0.50 -0.25 0.00 0.25 2 +V

f sb
V (V)
b

200 160
th

th
120
100 V = 50mV
DS 80
0 500 1000 1500 2000 0 500 1000 1500 2000
L(nm) L(nm)
(a) (b)

(c)

Figure 6.3: Threshold voltage model validation (a) threshold voltage vs channel length in linear region
at Vds = 50mV and Vb = 0V . Channel length is varied from 2µm to 70nm. The threshold voltage
from the model is in close agreement with the extraction methods. It is also important to note that
the model is able to capture the threshold voltage roll-up characteristics, typical to the halo implanted
devices. Measured threshold voltage is extracted using CC method, for which I0 = 350nA is used. Inset
figure shows the threshold voltage vs body bias in linear region at Vds = 50mV for L=2µm (b) Vth vs
L in saturation region (c) Vth vs body bias in linear and saturation region. The model accurately models
threshold voltage across length and drain and body biases.
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[9] K. Aoyama, “A method for extracting the threshold voltage of MOSFET based on current
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[10] A. Ortiz-Conde, F. G. Sanchez, M. Bucher, J. Liou, A. Cerdeira, M. Estrada, and Y. Yue,

“A review of recent MOSFET threshold voltage extraction methods,” Solid-State Elec-
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[11] H. Agarwal, C. Gupta, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, S. Salahuddin, and

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Chapter 7

Conclusions and Scope for Future Work

Doping non-uniformity is inevitably present in state of the art devices, sometimes intentionally,
sometimes unintentionally. In this work, we have attempted to investigate and model the impact
of doping non-uniformity on device performance. The models presented in the thesis are aimed
at inclusion in the industry standard BSIM6 MOS model so that they can be used for accurate
modeling of the planar bulk devices in advance technology nodes.
Initial part of this thesis focuses on drain current and transconductance modeling of the halo im-
planted devices. Most of the industry standard compact models account only for the drain side
halo region which cannot model the atypical characteristics of halo implanted devices. Through
TCAD simulations, we show that transconductance of the halo implanted devices in linear re-
gion evince peaky characteristics even when mobility degradation models were turned off. We
develop a compact model to show that effective conductance of the halo devices is governed
by the halo region in the weak inversion and by the channel region in strong inversion. This
switching of the conductance is responsible for the peakiness in transconductance. We also re-
port that transconductance in the saturation region undergoes sharp slope change in the vicinity
of weak-strong inversion region, which is uncommon in uniformly doped devices. Furthermore,
we also report for the first time that peak transconductance in the linear region exhibits peculiar
body bias dependence, as the peak initially increases and then decreases with the body bias. A
compact model is developed which accurately models the characteristics of the halo implanted
devices over wide range of biases.
In the next part of the thesis, the effect of doping non-uniformity on flicker (1/f) noise is sys-
tematically investigated. We show that the conventional approach underestimates 1/f noise by
several orders of magnitude, especially in the weak inversion region of operation. We develop a
model based on current continuity to imitate and explain 1/f noise behavior in such devices. The
model results surmise that impedance field (IF), which is responsible for the noise propagation
from a point in the channel to the drain terminal, near the source end is much higher than that in

104
7.1 Scope for Future Work 105

the rest of the channel in weak inversion. This IF behavior is identified as one of the potential
reasons for aberrant 1/f noise characteristics.
The insight gained in the analysis (and modeling) of the effect of doping non-uniformity on
1/f noise is utilized to develop completely analytical model for the halo implanted devices. We
develop a compact model which accounts for the threshold voltage difference between the halo
and the channel region, takes into consideration the effect of halo region length and doping, and
any extra trap states generated due to the halo implantation process. The proposed model shows
excellent results with the experimental data of halo devices fabricated with different fabs.
In this thesis, we also develop a compact model to calculate threshold voltage in the BSIM6
MOS model. BSIM6 is the charge based model, where currents and charges are expressed in
terms of inversion charge densities (not threshold voltage). Therefore, threshold voltage is not
explicitly available. However, it is important to model threshold voltage, since circuit designer
needs it to bias the circuit in the appropriate region. The proposed compact model is success-
fully validated with the real device measurements from IBM 90nm Technology. We also report a
new compact model to capture bulk charge effect on the drain saturation current. The presented
model is a BSIM4 based phenomenological model, which shows significant improvement in
matching drain current and transconductance characteristics in the saturation region.
In this work, we have also drawn equivalence between the core model of the BSIM4 and
BSIM6 MOS model. This is important in the sense that IC companies are gradually shifting
from BSIM4 to BSIM6, owing to its better RF modeling abilities. Since BSIM4 is a very
celebrated model which has enjoyed industry preference for more than a decade, people are very
familiar with its threshold voltage based core model. Therefore, this will simplify visualization
of the BSIM6 model.

7.1 Scope for Future Work

There are lot of opportunities to extend and improve this study. For the faithful circuit simu-
lations, accurate modeling of CV is equally important. Capacitance behavior of the halo im-
planted devices is significantly different from the conventional devices, as the threshold voltage
from CV is lower than that from IV. This is mainly because of the low doped channel region
turns on early and support gate charge at lower gate voltages. Another very interesting study
could be the investigation of the impact of inaccurate gm and noise models on various analog
circuits. From the modeling prospective, gm model can be further optimized by making the
threshold voltage a function of gate bias. This, however, may not be straight forward in unified
models like BSIM6.
Appendix A

BSIM6 Core Model

 
N DEP
φb = ln ; NDEP: Channel Doping Concentration (A.1)
ni
√
2 · q · si · N DEP
γ0 = √ (A.2)
Cox nVt
√
2 · q · si · N GAT E
γg = √ ; NGATE: GATE Doping Concentration (A.3)
Cox nVt
0 p
γ = γ0 · nVt (A.4)
0 p
γg = γg · nVt (A.5)
N DEP
δP D = (A.6)
N GAT√E
!2 2·q·si√ ·N DEP !2
γ0 C nVt N DEP
= √ ox = = δP D (A.7)
γg 2·q· ·N
si √ GAT E N GAT E
Cox nVt
γ0
γ= (A.8)
1 + δP D

A.1 The Pinch-Off Potential

In accumulation and inversion under depletion approximation, the bulk charge is given as [1]
q
0 − ψs
Qb = −sign(ψs ) · γ · Cox · Vt .(e Vt − 1) + ψs (A.9)

106
A.1 The Pinch-Off Potential 107

From potential balance equation including poly depletion,

!2
Qi + Qb Qi + Qb
VG = VF B + ψS − + (A.10)
Cox γg0 .Cox

At pinch off,ψS = ψP and Qi = 0. Substituting in (A.9) and (A.10),

q 0
!
0 −
ψP
γ −
ψP
VG − VF B = ψP + γ · Vt .(e Vt − 1) + ψP + ( 0 )2 Vt .(e Vt − 1) + ψP (A.11)
γg
q !
ψ ψ
0 − VP − VP
= ψP + γ · Vt .(e t − 1) + ψP + δP D Vt .(e t − 1) + ψP (A.12)

Normalizing it,

q !
−ψ
vg − vf b = ψp + γ0 · e−ψp + ψp − 1 + δP D e p − 1 + ψp (A.13)

Explicit expression for ψp can be derived from above relation in the asymptotic form by inspecting the
behavior in three different regions. First consider the depletion and inversion region of operation where
ψp >> 0 so that e−ψp is very small. Let ζ1 = e−ψp
!
p
vg − vf b = ψp + γ0 · ψp + ζ1 − 1 + δP D ζ1 − 1 + ψp (A.14)

Let

p
ψp + ζ1 − 1 = x (A.15)

or

ψp = x2 + 1 − ζ1 (A.16)

Thus

vg − vf b = x2 + 1 − ζ1 + γ0 .x + δP D .x2 (A.17)
A.1 The Pinch-Off Potential 108

or

γ0 1 − ζ1 vg − vf b
x2 + ·x+ − =0 (A.18)
1 + δP D 1 + δP D 1 + δP D

This gives

"v
u !2 #
u v g − v − 1 + ζ1 γ0 γ0
fb
x= t + − (A.19)
1 + δP D 2 · (1 + δP D ) 2 · (1 + δP D )

"v
u !2 #2
u v g − v − 1 + ζ1 γ0 γ0
2 fb
ψp = x + 1 − ζ1 = t + − + 1 − ζ1
1 + δP D 2 · (1 + δP D ) 2 · (1 + δP D )

(A.20)
"v
u !2 #2
u v g − v − 1 + ζ1 γ γ
fb
= t + − + 1 − ζ1 (A.21)
1 + δP D 2 2

γ0
where γ = 1+δP D

Similarly,
when ψp is close to 0

" # v" #2
u
vg − vf b γ u vg − v
fb γ
ψp0 = − 3(1 + √ ) + t − 3(1 + √ ) + 6(vg − vf b ) (A.22)
2 2 2 2

and in accumulation where ψp << 0 (ζ2 = ψp ),

" !2 #
vg − vf b − ζ2
ψp = − ln 1 − ζ2 + (A.23)
γ

Thus the pinch off potential is expressed as

   
vg −vf b −ψp0 2

− ln 1 − ψp0 + if vg − vf b < 0


γ
ψp = q 2 (A.24)
1 − e−ψp0 + γ
2 γ
vg − vf b − 1 + e−ψp0 + −


2 2 otherwise

Note : Derivatives of ψp are continuous in all regions.

A.2 Normalized Charge Density 109

A.2 Normalized Charge Density

Inversion Charge [2] : Charge sheet model approximates inversion charge density as
"r r #
ψS −2.φF −Vch
0p ψS ψS
Qi = −γ .Cox . Vt +e Vt − (A.25)
Vt Vt

Using inversion charge linearization [2],

Qi = nq .Cox · (ψS − ψP ) (A.26)

or
Qi
ψS = ψP + (A.27)
nq .Cox

Substituting ψS from (A.27) in (A.25),

"s Qi ψP +
Qi
−2.φF −Vch
s
Qi #
Qi ψP + nq .Cox
nq .Cox ψP + nq .Cox
− 0 √ = +e Vt − (A.28)
γ .Cox . Vt Vt Vt

rearranging,

" s
Qi #2 "s Qi ψP +
Qi
−2.φF −Vch
#2
Qi ψP + nq .Cox ψP + nq .Cox
nq .Cox
− 0 √ + = +e Vt (A.29)
γ .Cox . Vt Vt Vt
ψP +
Qi
−2.φF −Vch
!2 ! s Qi
nq .Cox
Qi Qi ψP + nq .Cox
e Vt = − √ − 2. √ · (A.30)
γ 0 .Cox . Vt γ.Cox . Vt Vt

This reduces to

Qi " !2 ! s Qi #
ψP + nq .Cox − 2.φF − Vch Qi Qi ψP + nq .Cox
= ln − 0 √ − 2. 0 √ ·
Vt γ .Cox . Vt γ .Cox . Vt Vt
(A.31)
s
" Qi !#
Qi Qi ψP + nq .Cox
= ln − 0 √ − 0 √ +2· (A.32)
γ .Cox . Vt γ .Cox . Vt Vt
A.2 Normalized Charge Density 110

Normalizing inversion charge to −2Vt .nq .Cox , all voltages to Vt ,

" !#
2nq .qi 2.nq .qi p
ψp −2.qi − 2.φf − vch = ln + 2 · ψp − 2qi (A.33)
γ0 γ0

which gives
 
2nq 2nq p
ln (qi ) + ln (qi + 2 ψp − 2qi ) + 2qi = ψp − 2φf − vch (A.34)
γ0 γ0

This is a general equation which can be solved to give normalized inversion charge density. The pro-
cedure of obtaining initial guess for the solution of above equation for weak inversion is described be-
low [3]. Note that to generalized the process, subscript “i” is dropped from the term qi
√
4nq ψp
Let v = ψp − 2φf − vch − ln( γ ) = ln q + 2q

v = ln q + 2q (A.35)

= ln q + 2eln q (A.36)
1
= ln q + (A.37)
F (ln q)

Here in second term q has been used as ln(eq ). The function F is defined as

1
F = (A.38)
2eln q
1
= (A.39)
2e( ln q + ln qt − ln qt )
1
= ln q (A.40)
2qt e qt
1 −∆
= e (A.41)
2qt

Where ∆ = ln qqt . Expanding (A.41) around ∆ = 0 using Taylor series expansion (as |2q| << | ln q| ),

1
F = .[1 − e−0 .∆]] (A.42)
2qt
1 q
= (1 − ln ) (A.43)
2qt qt
A.2 Normalized Charge Density 111

substituting in (A.37),

2qt
v = ln q + (A.44)
1 − ln q + ln qt

This equation is solved for q. Let,

ln q = x (A.45)
2qt
v =x+ (A.46)
1 + ln qt − x
v(1 + ln qt ) − vx − x(1 + ln qt ) + x2 − 2qt = 0 (A.47)
p
v + (1 + ln qt ) − (v + (1 + ln qt )2 − 4v(1 + ln qt ) + 8qt
x= (A.48)
2

For subthreshold region, normalized inversion charge density will be |q| << 1 and | ln q| >> |2q|. The
initial value is taken at a point where | ln q| = 2.|2q| which gives

qt = 0.301 (A.49)

1 + ln qt = −0.201491 (A.50)

substituting in (A.48),
p
v − 0.201491 − (v − 0.201491)2 − 4v(−0.201491) + 8(0.301)
x= (A.51)
p 2
v − 0.201491 − (v + 0.402982)v + 2.446562
x = ln q = (A.52)
2
A.2 Normalized Charge Density 112

Once the initial guess is known, the final value is obtained by using analytical method as shown below

γ
nq0 = 1 + p (A.53)
2 ψp
 
nq0 p
v = ψp − 2φ − vch − ln 4.0 · · ψp (A.54)
γ
1h p i
lnq0 = v − 0.201491 − v · (v + 0.402982) + 2.446562 (A.55)
2
q0 = elnq0 (A.56)

if lnq0 <= −80.0

   
nq0 nq0 p
qs/d = f = q0 · 1 + ψp − 2φ − vch − lnq0 − ln 2 · 2 · q0 · + 2 · ψp (A.57)
γ γ

In this equation, if ln q0 becomes very large and negative then q0 = eln q0 may be out of range of precision
limit of the simulator. Therefore it is approximated as follows
if ln q0 < −110 , q0 = e−100
if ln q0 > −90 , q0 = eln q0
5 z
else q0 = exp(−100 + 20( 64 + 2 + z 2 ( 15 2 2
16 − z (1.25 − z ))))
ln q0 +100
where z = 20 .
The above polynomial provides smooth derivatives for q. For the derivation of polynomial coefficients,
refer to Appendix A.
For ln q0 > −80

nq nq p
f = 2q0 + ln (2q0(2q0 + 2 ψp ) − (vp − 2φf − vch ) (A.58)
γ γ
nq0
γ +
√1
0 1 ψp
f =2+ + nq0 p (A.59)
q0 γ · q0 + ψp
f
q1 = q0 − (A.60)
f0

The accuracy of this initial guess is further improved by following procedure

nq nq p
f = 2q1 + ln (2q1(2q1 + 2 ψp ) − (vp − 2φf − vch ) (A.61)
γ γ
nq1
γ +
√1
0 1 ψp
f =2+ + nq1 p (A.62)
q1 γ · q1 + ψp
A.2 Normalized Charge Density 113

Applying Halley’s method,

nq0 2
+ √1

00 1 1 γ ψp
f =− 2 −h 3
i h p i −  nq0 p  (A.63)
q1 n q0
(ψp ) 2 · γ · q1 + ψp γ · q1 + ψp
00
!
f f ·f
qs/d = q1 − 0 · 1 + 2 (A.64)
f 2 · f0

For detailed derivation of IV and CV, please refer to [4].

Bibliography

[1] Y. Tsividis, Operation and Modeling of the MOS Transistor. Oxford University Press.

[2] J.-M. Sallese, M. Bucher, F. Krummenacher, and P. Fazan, “Inversion Charge Linearization
in MOSFET Modeling and Rigorous Derivation of the EKV Compact Model,” Solid-State
Electronics, vol. 47, no. 4, pp. 677 – 683, 2003.

[3] F. Pregaldiny, F. Krummenacher, B. Diagne, F. Pecheux, J.-M. Sallese, and C. Lallement,

“Explicit modeling of the double-gate MOSFET with VHDL-AMS,” International Journal
of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 19, no. 3, pp. 239–
256, May 2006.

[4] H. Agarwal, C. Gupta, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, S. Salahuddin, and

C. Hu, “BSIM6 Technical Manual,” 2015. [Online]. Available: http://bsim.berkeley.edu/
models/bsimbulk/

114
Appendix B

List of Publications

B.1 Journal Papers

• H. Agarwal, C. Gupta, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, “ Anomalous
Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling”,
IEEE Transactions on Electron Devices, Vol. 64, Issue 2, pp. 376-383, 2017.

• P. Kushwaha, Bala Krishna K, H. Agarwal, S. Khandelwal, J. P. Duarte, C. Hu, and Y.

S. Chauhan “Geometrically Scalable Thermal Resistance Model for FDSOI Transistors”,
Microelectronics Journal, Vol. 56, pp. 171 - 176, 2016.

• Y.-K. Lin, S. Khandelwal, A. Medury, H. Agarwal, H.-L. Chang, Y. S. Chauhan, and

C. Hu, “Modeling of Sub-surface Leakage Current in Low Vth Short Channel MOSFET
at Accumulation Bias”, IEEE Transactions on Electron Devices, Vol. 63, pp. 1840 -
1845, 2016.

• B. K. Kompala, P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, C. Hu and Y. S.

Chauhan, “Modeling of Nonlinear Thermal Resistance in FinFETs”, Japanese Journal
of Applied Physics, Vol. 55, pp. 04ED11, 2016.

• S. Khandelwal, H. Agarwal, P. Kushwaha, J. P. Duarte, A. Medury, Y. S. Chauhan, S.

Salahuddin, and C. Hu, “Unified Compact Model Covering Drift-Diffusion to Ballistic
Carrier Transport”, IEEE Electron Device Letters, Vol. 37, Issue 2, pp. 134-137, 2016

• H. Agarwal, P. Kushwaha, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Anal-

115
B.2 Conference Papers 116

ysis and Modeling of Flicker Noise in Lateral Asymmetric Channel MOSFETs”, Solid
State Electronics, Vol. 115, Part A, pp. 33 - 38, Jan. 2016.

• H. Agarwal, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, “Analytical Modeling

of Flicker Noise in Halo Implanted MOSFETs”, IEEE Journal of Electron Devices
Society, Vol. 3, Issue 4, pp. 355-360, 2015.

• H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and

Y. S. Chauhan, “Analytical Modeling and Experimental Validation of Threshold Voltage
in BSIM6 MOSFET Model”, IEEE Journal of Electron Devices Society, Vol. 3, Issue
3, pp. 240-243, 2015.

• S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S. Chauhan, and C. Hu,

“Modeling STI Edge Parasitic Current for Accurate Circuit Simulations”, Vol. 34, Issue 8,
pp. 1291-1294, IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, 2015.

• P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu,

Y. S. Chauhan, Modeling the Impact of Substrate Depletion in FDSOI MOSFETs in Solid
State Electronics, Vol. 104, Issue 2, pp. 6-11, 2015 .

• Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khan-

delwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad and C. Hu, “BSIM6:
Analog and RF Compact Model for Bulk MOSFET”, IEEE Transactions on Electron
Devices, Vol. 61, Issue 2, pp. 234-244, 2014.

B.2 Conference Papers

• H. Agarwal, C. Gupta, S. Khandelwal, S. Dey, K. Chan, C. Hu, and Y. S. Chauhan,

“ Analysis and Modeling of Low Frequency Noise in Presence of Doping Non-Uniformity
in MOSFETs”, IEEE International Conference on Emerging Electronics (ICEE),
2016.
B.2 Conference Papers 117

• C. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal, and Y. S. Chauhan, “Impact

of Back Plane Doping on RF Performance of FD-SOI Transistor using Industry Stan-
dard BSIM-IMG Model”, IEEE International Conference on Emerging Electronics
(ICEE), 2016.

• A. Dasgupta, H. Agarwal, A. Agarwal, and Y. S. Chauhan, “Modeling of Flicker Noise

in Quasi-ballistic devices”, IEEE International Conference on Emerging Electronics
(ICEE), 2016.

• N. Mohamed, H. Agarwal H. Agarwal, C. Gupta, and Y. S. Chauhan, “Modeling of NQS

Effect in Bulk MOSFETs for RF Circuit Design in Sub-THz Regime”, IEEE Interna-
tional Conference on Emerging Electronics (ICEE), 2016.

• C. Gupta, H. Agarwal, S. Khandelwal, Y. K. Lin, Akira Ito, C. Hu and Y. S. Chauhan,

Modeling of Zero-VTH MOSFET with Industry Standard BSIM6 Model“, International
Conference on Solid State Devices and Materials (SSDM), Tsukuba, Japan, September
2016.

• H. Agarwal, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. K. Lin, H. L. Chang, H. Wu,

P. D. Ye, C. Hu, and Y. S. Chauhan, ”Modeling of GeOI and Validation with Ge-CMOS
Inverter Circuit using BSIM-IMG Industry Standard Model“, IEEE International Con-
ference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, August
2016.

• P. Kushwaha, R. Agarwal, H. Agarwal, C. Gupta, S. Khandelwal, J. P. Duarte, Y. K. Lin,

H. L. Chang, C. Hu, and Y. S. Chauhan, ”Modeling of Threshold Voltage for Operating
Point using Industry standard BSIM-IMG Model“, IEEE International Conference on
Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, August 2016.

• P. Kushwaha, H. Agarwal, Y. S. Chauhan, M. Bhoir and N. R. Mohapatra, S. Khandel-

wal, J. P. Duarte, Y.-Kai Lin, H.-Lin Chang and C. Hu, ”Predictive Effective Mobility
Model for FDSOI Transistors using Technology Parameters“, IEEE International Con-
ference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, August
2016.
B.2 Conference Papers 118

• C. Gupta, H. Agarwal, S. Khandelwal, Y. K. Lin, R. Gillon, C. Hu and Y. S. Chauhan,

Modeling of High Voltage LDMOSFET using Industry Standard BSIM6 MOS Model”,
IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC),
Hong Kong, August 2016.

• H. Agarwal, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Analysis and Modeling of

Asymmetric Channel MOSFET”, International Workshop on Physics of Semiconduc-
tor Devices (IWPSD), Bangalore, India, Dec. 2015.

• C. Gupta, H. Agarwal, Akira Ito, S. Ghosh, P. Khushwaha, C. Hu, and Y. S. Chauhan,

“Modeling of Zero-Vth MOSFET with Industry Standard BSIM6 Model”, International
Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec.
2015.

• N. Mohamed, H. Agarwal, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, “Scaling

Capabilities of Industry-Standard BSIM6 MOSFET Model”, International Workshop
on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.

• J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta,

and Y. S. Chauhan “BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit
Design”, IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria,
Sept. 2015

• P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S.

Chauhan, “BSIM-IMG: Compact Model for RF-SOI MOSFETs”, IEEE Device Re-
search Conference (DRC), Columbus, USA, June 2015.

• P. Kushwaha, C. Yadav,H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, S. Khan-

delwal, Y. S. Chauhan, C. Hu, BSIM-IMG with Improved Surface Potential Calculation
in IEEE Indicon, 2014.

• C. Yadav, P. Kushwaha, H. Agarwal, Y. S. Chauhan, Threshold Voltage Modeling of

GaN Based Normally-Off Tri-gate Transistor in IEEE Indicon, 2014.

• A. Dutta, S. Sirohi, T. Ethirajan, H. Agarwal, Y. S. Chauhan, R. Q Williams, “BSIM6

B.2 Conference Papers 119

-Benchmarking the Next Generation MOSFET Model for RF Applications”, IEEE In-
ternational Conference on VLSI Design, Mumbai, India, Jan. 2014.

• J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwaha, S. Khandewal, R. Gillon, Y. S. Chauhan,

“High Voltage LDMOSFET Modeling using BSIM6 as Intrinsic-MOS Model”, IEEE
PrimeAsia, Visakhapatnam, Dec. 2013.

• H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri,

C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu, “Recent
Enhancements in BSIM6 Bulk MOSFET Model”, IEEE International Conference on
Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Scotland,
Sept. 2013.

• H. Agarwal, and Y. S. Chauhan, “Flicker Nosie Modeling in BSIM6 Compact Model”,

12th MOS-AK Workshop, Venice, Italy, Sept. 2014.

• H. Agarwal, S. Khandelwal, Y. S. Chauhan, C. Hu, “Noise Modeling in BSIM6 Compact

Model” NSTI Nanotech, Washigton D.C., USA, June 2014.

• Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte,

S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad and C. Hu, “BSIM Compact MOS-
FET Models for SPICE Simulation”, IEEE International Conference Mixed Design of
Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 2013.