Professional Documents
Culture Documents
Front End: Back End: Design Verification:: Hanoi, April 2020
Front End: Back End: Design Verification:: Hanoi, April 2020
JOB DESCRIPTION
My client provides the best semiconductor design service for all customers who make the world one-step further
with innovative and useful technologies. We offer a wide range of customer interfaces from Spec. to RTL, netlist, and
GDS. We also offer the customized IP, design technologies and platforms. We serve as a Total Solution Provider that
provides the turnkey solution including package, test, and quality control.
For global development vision, my client is looking for talents to join our new set-up Design Center in Hanoi with
following wonderful job opportunities:
Description:
Front End:
Create vector related analysis, test synthesis / DFT / STA / sdc cleanup / UPF clock
Back End:
APR (Auto Place Route)/ PV (Physical Verification), STA, UPF
Design Verification:
Plan the verification of complex digital design blocks by fully understanding the design specification
and interacting with design engineers to identify important verification scenarios
Create a constrained-random verification environment using System Verilog and UVM
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements:
50 PROFESSIONAL ENGINEERS
Experience 3 ~ 10 years or more
Priority candidates who have experience working in the Design Center
50 ENGINEERS
Graduated in electronics related industry (electronics and electronics, information technology, etc.)
Fresh graduation students are welcome
Experience Requirements:
Prefer candidates with qualifications related to the work done
Know Shell / Perl / Tcl / Python is advantage
Priority to candidates with experience SoC Design Service in a foreign enterprise
Know English or Korean
For Design Verification (DV), potential candidates are:
- Experience in the verification of designs such as CPUs, networking or peripheral controllers
- Experience with verification methodology such as UVM/OVM/VMM
- Experience with SystemVerilog, SVA, C, C++ and functional coverage.
Benefits/ Allowances:
1. Location: Hà Nội
2. Working time: From Monday to Friday
3. Salary: Negotiable + Lunch Allowance + Salary on 13th
4. Relocation support package (once paid, applied for candidates from Danang to the South)
5. Others: to be discussed in the interview